1 <!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
3 <!-- This defines instructions that store from a register to RAM -->
5 <!-- Note that these pages also define equivalent load instructions, -->
6 <!-- these are described in fixedload.mdwn -->
8 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
9 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
10 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
11 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
12 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
13 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
15 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
27 MEM(EA, 1) <- (RS)[XLEN-8:XLEN-1]
29 Special Registers Altered:
43 MEM(EA, 1) <- (RS)[56:63]
45 Special Registers Altered:
49 # Store Byte with Update
58 MEM(EA, 1) <- (RS)[56:63]
61 Special Registers Altered:
65 # Store Byte with Update Indexed
74 MEM(EA, 1) <- (RS)[56:63]
77 Special Registers Altered:
91 MEM(EA, 2) <- (RS)[48:63]
93 Special Registers Altered:
97 # Store Halfword Indexed
107 MEM(EA, 2) <- (RS)[48:63]
109 Special Registers Altered:
113 # Store Halfword with Update
122 MEM(EA, 2) <- (RS)[48:63]
125 Special Registers Altered:
129 # Store Halfword with Update Indexed
138 MEM(EA, 2) <- (RS)[48:63]
141 Special Registers Altered:
155 MEM(EA, 4) <- (RS)[32:63]
157 Special Registers Altered:
171 MEM(EA, 4) <- (RS)[32:63]
173 Special Registers Altered:
177 # Store Word with Update
186 MEM(EA, 4) <- (RS)[32:63]
189 Special Registers Altered:
193 # Store Word with Update Indexed
202 MEM(EA, 4) <- (RS)[32:63]
205 Special Registers Altered:
211 <!-- Section 3.3.3.1 64-bit Fixed-Point Store Instructions page 57 -->
222 EA <- b + EXTS(DS || 0b00)
225 Special Registers Altered:
229 # Store Doubleword Indexed
241 Special Registers Altered:
245 # Store Doubleword with Update
253 EA <- (RA) + EXTS(DS || 0b00)
257 Special Registers Altered:
261 # Store Doubleword with Update Indexed
273 Special Registers Altered:
278 <!-- Section 3.3.4 Fixed Point Load and Store Quadword Instructions pages 58 - 59 -->
280 <!-- For stq, the contents of an even-odd pair of GPRs is stored into the quadword -->
281 <!-- in storage addressed by EA as follows. In Big-Endian mode, the even-numbered -->
282 <!-- GPR is stored into the doubleword in storage addressed by EA and the -->
283 <!-- odd-numbered GPR is stored into the doubleword addressed by EA+8. In -->
284 <!-- Little-Endian mode, the even-numbered GPR is stored byte-reversed into the -->
285 <!-- doubleword in storage addressed by EA+8 and the odd-numbered GPR is stored -->
286 <!-- byte-reversed into the doubleword addressed by EA. -->
298 EA <- b + EXTS(DS || 0b00)
301 Special Registers Altered:
305 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
307 # Store Halfword Byte-Reverse Indexed
317 MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
319 Special Registers Altered:
323 # Store Word Byte-Reverse Indexed
333 MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
336 Special Registers Altered:
340 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
342 # Store Doubleword Byte-Reverse Indexed
352 MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55]
353 || (RS)[40:47] || (RS)[32:39]
354 || (RS)[24:31] || (RS)[16:23]
355 || (RS)[8:15] || (RS)[0:7])
357 Special Registers Altered:
362 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
364 # Store Multiple Word
376 MEM(EA, 4) <- GPR(r)[32:63]
380 Special Registers Altered:
384 <!-- Checked March 2021 -->