openpower/isa/fpload.mdwn

   1 <!-- X Instructions here described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- Section 4.6.1 Floating-point storage access instructions. P 140 - 143 -->
   4
   5 # Load Floating-Point Single
   6
   7 D-Form
   8
   9 * lfs FRT,D(RA)
  10
  11 Pseudo-code:
  12
  13     EA <- (RA|0) + EXTS(D)
  14     FRT <- DOUBLE(MEM(EA, 4))
  15
  16 Description:
  17
  18     Let the effective address (EA) be the sum (RA|0)+D.
  19     The word in storage addressed by EA is interpreted as
  20     a floating-point single-precision operand. This word is
  21     converted to floating-point double format (see
  22     page 138) and placed into register FRT.
  23
  24 Special Registers Altered:
  25
  26     None
  27
  28 # Load Floating-Point Single Indexed
  29
  30 X-Form
  31
  32 * lfsx FRT,RA,RB
  33
  34 Pseudo-code:
  35
  36     EA <- (RA|0) + (RB)
  37     FRT <- DOUBLE(MEM(EA, 4))
  38
  39 Description:
  40
  41     Let the effective address (EA) be the sum (RA|0)+(RB).
  42
  43     The word in storage addressed by EA is interpreted as
  44     a floating-point single-precision operand. This word is
  45     converted to floating-point double format (see
  46     page 138) and placed into register FRT.
  47
  48 Special Registers Altered:
  49
  50     None
  51
  52 # Load Floating-Point Single with Update
  53
  54 D-Form
  55
  56 * lfsu FRT,D(RA)
  57
  58 Pseudo-code:
  59
  60     EA <- (RA) + EXTS(D)
  61     FRT <- DOUBLE(MEM(EA, 4))
  62     RA <- EA
  63
  64 Special Registers Altered:
  65
  66     None
  67
  68 # Load Floating-Point Single with Update Indexed
  69
  70 X-Form
  71
  72 * lfsux FRT,RA,RB
  73
  74 Pseudo-code:
  75
  76     EA <- (RA) + (RB)
  77     FRT <- DOUBLE(MEM(EA, 4))
  78     RA <- EA
  79
  80 Special Registers Altered:
  81
  82     None
  83
  84 # Load Floating-Point Double
  85
  86 D-Form
  87
  88 * lfd FRT,D(RA)
  89
  90 Pseudo-code:
  91
  92     EA <- (RA|0) + EXTS(D)
  93     FRT <- MEM(EA, 8)
  94
  95 Special Registers Altered:
  96
  97     None
  98
  99 # Load Floating-Point Double Indexed
 100
 101 X-Form
 102
 103 * lfdx FRT,RA,RB
 104
 105 Pseudo-code:
 106
 107     EA <- (RA|0) + (RB)
 108     FRT <- MEM(EA, 8)
 109
 110 Special Registers Altered:
 111
 112     None
 113
 114 # Load Floating-Point Double with Update
 115
 116 D-Form
 117
 118 * lfdu FRT,D(RA)
 119
 120 Pseudo-code:
 121
 122     EA <- (RA) + EXTS(D)
 123     FRT <- MEM(EA, 8)
 124     RA <- EA
 125
 126 Special Registers Altered:
 127
 128     None
 129
 130 # Load Floating-Point Double with Update Indexed
 131
 132 X-Form
 133
 134 * lfdux FRT,RA,RB
 135
 136 Pseudo-code:
 137
 138     EA <- (RA) + (RB)
 139     FRT <- MEM(EA, 8)
 140     RA <- EA
 141
 142 Special Registers Altered:
 143
 144     None
 145
 146 # Load Floating-Point as Integer Word Algebraic Indexed
 147
 148 X-Form
 149
 150 * lfiwax FRT,RA,RB
 151
 152 Pseudo-code:
 153
 154     EA <- (RA|0) + (RB)
 155     FRT <- EXTS(MEM(EA, 4))
 156
 157 Special Registers Altered:
 158
 159     None
 160
 161 # Load Floating-Point as Integer Word Zero Indexed
 162
 163 X-Form
 164
 165 * lfiwzx FRT,RA,RB
 166
 167 Pseudo-code:
 168
 169     EA <- (RA|0) + (RB)
 170     FRT <- [0]*32 || MEM(EA, 4)
 171
 172 Special Registers Altered:
 173
 174     None