openpower/isa/fpload.mdwn

   1 <!-- X Instructions here described in PowerISA Version 3.0 B Book 1 -->
   2
   3 <!-- Section 4.6.1 Floating-point storage access instructions. P 140 - 143 -->
   4
   5 # Load Floating-Point Single
   6
   7 D-Form
   8
   9 * lfs FRT,D(RA)
  10
  11 Pseudo-code:
  12
  13     EA <- (RA|0) + EXTS(D)
  14     FRT <- DOUBLE(MEM(EA, 4))
  15
  16 Description:
  17
  18     Let the effective address (EA) be the sum (RA|0)+D.
  19     The word in storage addressed by EA is interpreted as
  20     a floating-point single-precision operand. This word is
  21     converted to floating-point double format (see
  22     page 138) and placed into register FRT.
  23
  24 Special Registers Altered:
  25
  26     None
  27
  28 # Load Floating-Point Single Indexed
  29
  30 X-Form
  31
  32 * lfsx FRT,RA,RB
  33
  34 Pseudo-code:
  35
  36     EA <- (RA|0) + (RB)
  37     FRT <- DOUBLE(MEM(EA, 4))
  38
  39 Special Registers Altered:
  40
  41     None
  42
  43 # Load Floating-Point Single with Update
  44
  45 D-Form
  46
  47 * lfsu FRT,D(RA)
  48
  49 Pseudo-code:
  50
  51     EA <- (RA) + EXTS(D)
  52     FRT <- DOUBLE(MEM(EA, 4))
  53     RA <- EA
  54
  55 Special Registers Altered:
  56
  57     None
  58
  59 # Load Floating-Point Single with Update Indexed
  60
  61 X-Form
  62
  63 * lfsux FRT,RA,RB
  64
  65 Pseudo-code:
  66
  67     EA <- (RA) + (RB)
  68     FRT <- DOUBLE(MEM(EA, 4))
  69     RA <- EA
  70
  71 Special Registers Altered:
  72
  73     None
  74
  75 # Load Floating-Point Double
  76
  77 D-Form
  78
  79 * lfd FRT,D(RA)
  80
  81 Pseudo-code:
  82
  83     EA <- (RA|0) + EXTS(D)
  84     FRT <- MEM(EA, 8)
  85
  86 Special Registers Altered:
  87
  88     None
  89
  90 # Load Floating-Point Double Indexed
  91
  92 X-Form
  93
  94 * lfdx FRT,RA,RB
  95
  96 Pseudo-code:
  97
  98     EA <- (RA|0) + (RB)
  99     FRT <- MEM(EA, 8)
 100
 101 Special Registers Altered:
 102
 103     None
 104
 105 # Load Floating-Point Double with Update
 106
 107 D-Form
 108
 109 * lfdu FRT,D(RA)
 110
 111 Pseudo-code:
 112
 113     EA <- (RA) + EXTS(D)
 114     FRT <- MEM(EA, 8)
 115     RA <- EA
 116
 117 Special Registers Altered:
 118
 119     None
 120
 121 # Load Floating-Point Double with Update Indexed
 122
 123 X-Form
 124
 125 * lfdux FRT,RA,RB
 126
 127 Pseudo-code:
 128
 129     EA <- (RA) + (RB)
 130     FRT <- MEM(EA, 8)
 131     RA <- EA
 132
 133 Special Registers Altered:
 134
 135     None
 136
 137 # Load Floating-Point as Integer Word Algebraic Indexed
 138
 139 X-Form
 140
 141 * lfiwax FRT,RA,RB
 142
 143 Pseudo-code:
 144
 145     EA <- (RA|0) + (RB)
 146     FRT <- EXTS(MEM(EA, 4))
 147
 148 Special Registers Altered:
 149
 150     None
 151
 152 # Load Floating-Point as Integer Word Zero Indexed
 153
 154 X-Form
 155
 156 * lfiwzx FRT,RA,RB
 157
 158 Pseudo-code:
 159
 160     EA <- (RA|0) + (RB)
 161     FRT <- [0]*32 || MEM(EA, 4)
 162
 163 Special Registers Altered:
 164
 165     None