1 <!-- This defines DRAFT instructions that are to be proposed for SV -->
3 <!-- This defines instructions that load from RAM to a register -->
4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
6 <!-- Note that these pages also define equivalent store instructions, -->
7 <!-- these are described in pifixedstore.mdwn -->
11 # Load Byte and Zero with Post-Update Indexed
20 RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
25 Let the effective address (EA) be register RA.
27 The byte in storage addressed by EA is loaded into RT[56:63].
28 RT[0:55] are set to 0.
30 The sum (RA) + (RB) is placed into register RA.
32 If RA=0 or RA=RT, the instruction form is invalid.
34 Special Registers Altered:
38 # Load Halfword and Zero with Post-Update Indexed
47 RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
52 Let the effective address (EA) be register RA.
53 The halfword in storage addressed by EA is loaded into RT[48:63].
54 RT[0:47] are set to 0.
56 The sum (RA) + (RB) is placed into register RA.
58 If RA=0 or RA=RT, the instruction form is invalid.
60 Special Registers Altered:
64 # Load Halfword Algebraic with Post-Update Indexed
73 RT <- EXTS(MEM(EA, 2))
78 Let the effective address (EA) be the register RA.
80 The halfword in storage addressed by EA is loaded into RT[48:63].
81 RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
83 The sum (RA) + (RB) is placed into register RA.
85 If RA=0 or RA=RT, the instruction form is invalid.
87 Special Registers Altered:
91 # Load Word and Zero with Post-Update Indexed
100 RT <- [0] * 32 || MEM(EA, 4)
105 Let the effective address (EA) be the register RA.
107 The halfword in storage addressed by EA is loaded into RT[48:63].
108 RT[0:47] are filled with a copy of bit 0 of the loaded halfword.
110 The sum (RA) + (RB) is placed into register RA.
112 If RA=0 or RA=RT, the instruction form is invalid.
114 Special Registers Altered:
118 # Load Word Algebraic with Post-Update Indexed
127 RT <- EXTS(MEM(EA, 4))
132 Let the effective address (EA) be the register RA.
134 The word in storage addressed by EA is loaded into RT[32:63].
135 RT[0:31] are filled with a copy of bit 0 of the loaded word.
137 The sum (RA) + (RB) is placed into register RA.
139 If RA=0 or RA=RT, the instruction form is invalid.
141 Special Registers Altered:
145 # Load Doubleword with Post-Update Indexed
159 Let the effective address (EA) be the register RA.
161 The doubleword in storage addressed by EA is loaded into RT.
163 The sum (RA) + (RB) is placed into register RA.
165 If RA=0 or RA=RT, the instruction form is invalid.
167 Special Registers Altered: