openpower/isa/pifixedstore.mdwn

   1 <!-- This defines DRAFT instructions described in SV -->
   2
   3 <!-- This defines instructions that store from a register to RAM -->
   4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
   5
   6 # Store Byte with Update
   7
   8 D-Form
   9
  10 * stbup RS,D(RA)
  11
  12 Pseudo-code:
  13
  14     EA <- (RA) + EXTS(D)
  15     ea <- (RA)
  16     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
  17     RA <- EA
  18
  19 Description:
  20
  21     Let the effective address (EA) be the sum (RA)+ D.
  22     (RS)[56:63] are stored into the byte in storage addressed
  23     by EA.
  24
  25     EA is placed into register RA.
  26
  27     If RA=0, the instruction form is invalid.
  28
  29 Special Registers Altered:
  30
  31     None
  32
  33 # Store Byte with Update Indexed
  34
  35 X-Form
  36
  37 * stbupx RS,RA,RB
  38
  39 Pseudo-code:
  40
  41     EA <- (RA) + (RB)
  42     ea <- (RA)
  43     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
  44     RA <- EA
  45
  46 Description:
  47
  48     Let the effective address (EA) be the sum (RA)+ (RB).
  49     (RS)[56:63] are stored into the byte in storage addressed
  50     by EA.
  51
  52     EA is placed into register RA.
  53
  54     If RA=0, the instruction form is invalid.
  55
  56 Special Registers Altered:
  57
  58     None
  59
  60 # Store Halfword with Update
  61
  62 D-Form
  63
  64 * sthup RS,D(RA)
  65
  66 Pseudo-code:
  67
  68     EA <- (RA) + EXTS(D)
  69     ea <- (RA)
  70     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
  71     RA <- EA
  72
  73 Description:
  74
  75 Let the effective address (EA) be the sum (RA|0)+ D.
  76 (RS)[48:63] are stored into the halfword in storage
  77 addressed by EA.
  78
  79 Special Registers Altered:
  80
  81     None
  82
  83 # Store Halfword with Update Indexed
  84
  85 X-Form
  86
  87 * sthupx RS,RA,RB
  88
  89 Pseudo-code:
  90
  91     EA <- (RA) + (RB)
  92     ea <- (RA)
  93     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
  94     RA <- EA
  95
  96 Special Registers Altered:
  97
  98     None
  99
 100 # Store Word with Update
 101
 102 D-Form
 103
 104 * stwup RS,D(RA)
 105
 106 Pseudo-code:
 107
 108     EA <- (RA) + EXTS(D)
 109     ea <- (RA)
 110     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
 111     RA <- EA
 112
 113 Special Registers Altered:
 114
 115     None
 116
 117 # Store Word with Update Indexed
 118
 119 X-Form
 120
 121 * stwupx RS,RA,RB
 122
 123 Pseudo-code:
 124
 125     EA <- (RA) + (RB)
 126     ea <- (RA)
 127     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
 128     RA <- EA
 129
 130 Special Registers Altered:
 131
 132     None
 133
 134 # Store Doubleword with Update
 135
 136 DS-Form
 137
 138 * stdup RS,DS(RA)
 139
 140 Pseudo-code:
 141
 142     EA <- (RA) + EXTS(DS || 0b00)
 143     ea <- (RA)
 144     MEM(ea, 8) <- (RS)
 145     RA <- EA
 146
 147 Special Registers Altered:
 148
 149     None
 150
 151 # Store Doubleword with Update Indexed
 152
 153 X-Form
 154
 155 * stdupx RS,RA,RB
 156
 157 Pseudo-code:
 158
 159     EA <- (RA) + (RB)
 160     ea <- (RA)
 161     MEM(ea, 8) <- (RS)
 162     RA <- EA
 163
 164 Special Registers Altered:
 165
 166     None
 167