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[libreriscv.git] / openpower / isa / sprset.mdwn
1 # Move To Special Purpose Register
2
3 * mtspr SPR,RS
4
5 n <- spr[5:9] || spr[0:4]
6 switch (n)
7 case(13): see Book III
8 case(808, 809, 810, 811):
9 default:
10 if length(SPR(n)) = 64 then
11 SPR(n) <- (RS)
12 else
13 SPR(n) <- (RS) [32:63]
14
15 # Move From Special Purpose Register
16
17 * mfspr RT,SPR
18
19 n <- spr[5:9] || spr[0:4]
20 switch (n)
21 case(129): see Book III
22 case(808, 809, 810, 811):
23 default:
24 if length(SPR(n)) = 64 then
25 RT <- SPR(n)
26 else
27 RT <- [0]*32 || SPR(n)
28
29 # Move to CR from XER Extended
30
31 * mcrxrx BF
32
33 CR[4×BF+32:4×BF+35] <- XER[OV] || XER[OV32] || XER[CA] || XER[CA32]
34
35 # Move To One Condition Register Field
36
37 * mtocrf FXM,RS
38
39 count <- 0
40 do i = 0 to 7
41 if FXM[i] = 1 then
42 n <- i
43 count <- count + 1
44 if count = 1 then
45 CR[4*n+32:4*n+35] <- (RS)[4*n+32:4*n+35]
46 else CR <- undefined
47
48 # Move To Condition Register Fields
49
50 * mtcrf FXM,RS
51
52 mask <- FXM[0]*4 || FXM[1]*4 || ... FXM[7]*4
53 CR <- ((RS)[32:63] & mask) | (CR & ¬mask)
54
55 # Move From One Condition Register Field
56
57 * mfocrf RT,FXM
58
59 RT <- undefined
60 count <- 0
61 do i = 0 to 7
62 if FXM[i] = 1 then
63 n <- i
64 count <- count + 1
65 if count = 1 then
66 RT <- [0]*64
67 RT[4 *n+32:4*n+35] <- CR[4*n+32:4* n+35]
68
69 # Move From Condition Register
70
71 * mfcr RT
72
73 RT <- [0]*32 || CR
74
75 # Set Boolean
76
77 * setb RT,BFA
78
79 if CR[4×BFA+32] = 1 then
80 RT <- 0xFFFF_FFFF_FFFF_FFFF
81 else if CR[4×BFA+33]=1 then
82 RT <- 0x0000_0000_0000_0001
83 else
84 RT <- 0x0000_0000_0000_0000
85