f8b361a9c9600d8ab5a845b7583ce16e2aa66581
[libreriscv.git] / openpower / isa / sprset.mdwn
1 # Move To Special Purpose Register
2
3 XFX-Form
4
5 * mtspr SPR,RS
6
7 Pseudo-code:
8
9 n <- spr[5:9] || spr[0:4]
10 switch (n)
11 case(13): see(Book_III_p974)
12 case(808, 809, 810, 811):
13 default:
14 if length(SPR(n)) = 64 then
15 SPR(n) <- (RS)
16 else
17 SPR(n) <- (RS) [32:63]
18
19 Special Registers Altered:
20
21 See spec 3.3.17
22
23 # Move From Special Purpose Register
24
25 XFX-Form
26
27 * mfspr RT,SPR
28
29 Pseudo-code:
30
31 n <- spr[5:9] || spr[0:4]
32 switch (n)
33 case(129): see(Book_III_p975)
34 case(808, 809, 810, 811):
35 default:
36 if length(SPR(n)) = 64 then
37 RT <- SPR(n)
38 else
39 RT <- [0]*32 || SPR(n)
40
41 Special Registers Altered:
42
43 None
44
45 # Move to CR from XER Extended
46
47 X-Form
48
49 * mcrxrx BF
50
51 Pseudo-code:
52
53 CR[4*BF+32:4*BF+35] <- XER[OV] || XER[OV32] || XER[CA] || XER[CA32]
54
55 Special Registers Altered:
56
57 CR field BF
58
59 # Move To One Condition Register Field
60
61 XFX-Form
62
63 * mtocrf FXM,RS
64
65 Pseudo-code:
66
67 count <- 0
68 do i = 0 to 7
69 if FXM[i] = 1 then
70 n <- i
71 count <- count + 1
72 if count = 1 then
73 CR[4*n+32:4*n+35] <- (RS)[4*n+32:4*n+35]
74 else CR <- undefined
75
76 Special Registers Altered:
77
78 CR field selected by FXM
79
80 # Move To Condition Register Fields
81
82 XFX-Form
83
84 * mtcrf FXM,RS
85
86 Pseudo-code:
87
88 mask <- ([FXM[0]]*4 || [FXM[1]]*4 || [FXM[2]]*4 || [FXM[3]]*4 ||
89 [FXM[4]]*4 || [FXM[5]]*4 || [FXM[6]]*4 || [FXM[7]]*4)
90 CR <- ((RS)[32:63] & mask) | (CR & ¬mask)
91
92 Special Registers Altered:
93
94 CR fields selected by mask
95
96 # Move From One Condition Register Field
97
98 XFX-Form
99
100 * mfocrf RT,FXM
101
102 Pseudo-code:
103
104 RT <- undefined
105 count <- 0
106 do i = 0 to 7
107 if FXM[i] = 1 then
108 n <- i
109 count <- count + 1
110 if count = 1 then
111 RT <- [0]*64
112 RT[4*n+32:4*n+35] <- CR[4*n+32:4* n+35]
113
114 Special Registers Altered:
115
116 None
117
118 # Move From Condition Register
119
120 XFX-Form
121
122 * mfcr RT
123
124 Pseudo-code:
125
126 RT <- [0]*32 || CR
127
128 Special Registers Altered:
129
130 None
131
132 # Set Boolean
133
134 X-Form
135
136 * setb RT,BFA
137
138 Pseudo-code:
139
140 if CR[4*BFA+32] = 1 then
141 RT <- 0xFFFF_FFFF_FFFF_FFFF
142 else if CR[4*BFA+33]=1 then
143 RT <- 0x0000_0000_0000_0001
144 else
145 RT <- 0x0000_0000_0000_0000
146
147 Special Registers Altered:
148
149 None
150
151 # Move To Machine State Register
152
153 X-Form
154
155 * mtmsr RS,L
156
157 Pseudo-code:
158
159 if L = 0 then
160 MSR[48] <- (RS)[48] | (RS)[49]
161 MSR[58] <- ((RS)[58] | (RS)[49]) & ¬(MSR[41] & MSR[3] & (¬(RS)[49]))
162 MSR[59] <- ((RS)[59] | (RS)[49]) & ¬(MSR[41] & MSR[3] & (¬(RS)[49]))
163 MSR[32:40] <- (RS)[32:40]
164 MSR[42:47] <- (RS)[42:47]
165 MSR[49:50] <- (RS)[49:50]
166 MSR[52:57] <- (RS)[52:57]
167 MSR[60:62] <- (RS)[60:62]
168 else
169 MSR[48] <- (RS)[48]
170 MSR[62] <- (RS)[62]
171
172 Special Registers Altered:
173
174 MSR
175
176 # Move To Machine State Register
177
178 X-Form
179
180 * mtmsrd RS,L
181
182 Pseudo-code:
183
184 if L = 0 then
185 MSR[48] <- (RS)[48] | (RS)[49]
186 MSR[58] <- ((RS)[58] | (RS)[49]) & ¬(MSR[41] & MSR[3] & (¬(RS)[49]))
187 MSR[59] <- ((RS)[59] | (RS)[49]) & ¬(MSR[41] & MSR[3] & (¬(RS)[49]))
188 MSR[0:2] <- (RS)[0:2]
189 MSR[3:28] <- (RS)[3:28]
190 MSR[32:40] <- (RS)[32:40]
191 MSR[42:47] <- (RS)[42:47]
192 MSR[49:50] <- (RS)[49:50]
193 MSR[52:57] <- (RS)[52:57]
194 MSR[60:62] <- (RS)[60:62]
195 else
196 MSR[48] <- (RS)[48]
197 MSR[62] <- (RS)[62]
198
199 Special Registers Altered:
200
201 MSR
202
203 # Move From Machine State Register
204
205 X-Form
206
207 * mfmsr RT
208
209 Pseudo-code:
210
211 RT <- MSR
212
213 Special Registers Altered:
214
215 None
216