openpower/isa/svfixedarith.mdwn

   1 # [DRAFT] Multiply and Add Extended Doubleword
   2
   3 VA-Form
   4
   5 * madded RT,RA,RB,RC
   6
   7 Pseudo-code:
   8
   9     <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
  10     <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+MAXVL
  11     <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]
  12     prod[0:127] <- (RA) * (RB)
  13     sum[0:127] <- ([0] * 64 || (RC)) + prod
  14     RT <- sum[64:127]
  15     RS <- sum[0:63]
  16
  17 Special Registers Altered:
  18
  19     None
  20
  21 # [DRAFT] Divide/Modulo Double-width Doubleword Unsigned
  22
  23 VA-Form
  24
  25 * divrem2du   RT,RA,RB,RC
  26
  27 Pseudo-code:
  28
  29     <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
  30     <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+MAXVL
  31     <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]
  32     if ((RC) <u (RB)) & ((RB) != [0]*XLEN) then
  33         dividend[0:(XLEN*2)-1] <- (RC) || (RA)
  34         divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
  35         result <- dividend / divisor
  36         modulo <- dividend % divisor
  37         RT <- result[XLEN:(XLEN*2)-1]
  38         RS <- modulo[XLEN:(XLEN*2)-1]
  39         overflow <- 0
  40     else
  41         overflow <- 1
  42         RT <- [1]*XLEN
  43         RS <- [0]*XLEN
  44
  45 Special Registers Altered:
  46
  47     None
  48
  49 # [DRAFT] Double-width Shift Left Doubleword
  50
  51 Z23-Form
  52
  53 * dsld    RT,RA,RB,sm  (Rc=0)
  54 * dsld.   RT,RA,RB,sm  (Rc=1)
  55
  56 Pseudo-code:
  57
  58     switch(sm)
  59         case(0):
  60             hi <- (RT)
  61             lo <- (RA)
  62             sh <- (RB)
  63         case(1):
  64             hi <- (RA)
  65             lo <- (RT)
  66             sh <- (RB)
  67         case(2):
  68             hi <- (RA)
  69             lo <- (RB)
  70             sh <- (RT)
  71         default:
  72             hi <- [0] * 64
  73             lo <- (RA)
  74             sh <- (RB)
  75     n <- sh[58:63]
  76     mask[0:63] <- MASK(n, 63)
  77     v[0:63] <- (hi & mask) | (lo & ¬mask)
  78     RT <- ROTL64(v, n)
  79
  80 Special Registers Altered:
  81
  82     CR0                    (if Rc=1)
  83
  84 # [DRAFT] Double-width Shift Right Doubleword
  85
  86 Z23-Form
  87
  88 * dsrd    RT,RA,RB,sm  (Rc=0)
  89 * dsrd.   RT,RA,RB,sm  (Rc=1)
  90
  91 Pseudo-code:
  92
  93     switch(sm)
  94         case(0):
  95             hi <- (RT)
  96             lo <- (RA)
  97             sh <- (RB)
  98         case(1):
  99             hi <- (RA)
 100             lo <- (RT)
 101             sh <- (RB)
 102         case(2):
 103             hi <- (RA)
 104             lo <- (RB)
 105             sh <- (RT)
 106         default:
 107             hi <- (RA)
 108             lo <- [0] * 64
 109             sh <- (RB)
 110     n <- sh[58:63]
 111     mask[0:63] <- MASK(0, 63 - n)
 112     v[0:63] <- (hi & ¬mask) | (lo & mask)
 113     RT <- ROTL64(v, 64 - n)
 114
 115 Special Registers Altered:
 116
 117     CR0                    (if Rc=1)