openpower/isa/svfparith.mdwn

   1 <!-- SVP64 FP Instructions here described are based on -->
   2 <!--  PowerISA Version 3.0 B Book 1 -->
   3
   4 <!-- FRS in each of these does not need to be explicitly declared -->
   5 <!-- FRS is automatically calculated by SVP64 to FRT+VL (default elwidth) -->
   6 <!-- (Vector FRS data sequentially starts immediately after FRT vectors) -->
   7
   8 # Floating Add FFT/DCT [Single]
   9
  10 A-Form
  11
  12 * faddso FRT,FRA,FRB (Rc=0)
  13 * faddso. FRT,FRA,FRB (Rc=1)
  14
  15 Pseudo-code:
  16
  17     FRT <- FPADD32(FRA, FRB)
  18     FRS <- FPSUB32(FRA, FRB)
  19
  20 Special Registers Altered:
  21
  22     FPRF FR FI
  23     FX OX UX XX
  24     VXSNAN VXISI
  25     CR1          (if Rc=1)
  26
  27 # Floating Add FFT/DCT [Double]
  28
  29 A-Form
  30
  31 * faddo FRT,FRA,FRB (Rc=0)
  32 * faddo. FRT,FRA,FRB (Rc=1)
  33
  34 Pseudo-code:
  35
  36     FRT <- FPADD64(FRA, FRB)
  37     FRS <- FPSUB64(FRA, FRB)
  38
  39 Special Registers Altered:
  40
  41     FPRF FR FI
  42     FX OX UX XX
  43     VXSNAN VXISI
  44     CR1          (if Rc=1)
  45
  46 # Floating Subtract FFT/DCT [Single]
  47
  48 A-Form
  49
  50 * fsubso FRT,FRA,FRB (Rc=0)
  51 * fsubso. FRT,FRA,FRB (Rc=1)
  52
  53 Pseudo-code:
  54
  55     FRT <- FPSUB32(FRA, FRB)
  56     FRS <- FPADD32(FRA, FRB)
  57
  58 Special Registers Altered:
  59
  60     FPRF FR FI
  61     FX OX UX XX
  62     VXSNAN VXISI
  63     CR1          (if Rc=1)
  64
  65 # Floating Subtract FFT/DCT [Double]
  66
  67 A-Form
  68
  69 * fsubo FRT,FRA,FRB (Rc=0)
  70 * fsubo. FRT,FRA,FRB (Rc=1)
  71
  72 Pseudo-code:
  73
  74     FRT <- FPSUB64(FRA, FRB)
  75     FRS <- FPADD64(FRA, FRB)
  76
  77 Special Registers Altered:
  78
  79     FPRF FR FI
  80     FX OX UX XX
  81     VXSNAN VXISI
  82     CR1          (if Rc=1)
  83
  84 # Floating Multiply FFT/DCT [Single]
  85
  86 A-Form
  87
  88 * fmulso FRT,FRA,FRC (Rc=0)
  89 * fmulso. FRT,FRA,FRC (Rc=1)
  90
  91 Pseudo-code:
  92
  93     FRT <- FPMUL32(FRA, FRC)
  94     FRS <- FPMUL32(FRA, FRC, -1)
  95
  96 Special Registers Altered:
  97
  98     FPRF FR FI
  99     FX OX UX XX
 100     VXSNAN VXISI
 101     CR1          (if Rc=1)
 102
 103 # Floating Multiply FFT/DCT [Double]
 104
 105 A-Form
 106
 107 * fmulo FRT,FRA,FRC (Rc=0)
 108 * fmulo. FRT,FRA,FRC (Rc=1)
 109
 110 Pseudo-code:
 111
 112     FRT <- FPMUL64(FRA, FRC)
 113     FRS <- FPMUL64(FRA, FRC, -1)
 114
 115 Special Registers Altered:
 116
 117     FPRF FR FI
 118     FX OX UX XX
 119     VXSNAN VXISI
 120     CR1          (if Rc=1)
 121
 122 # Floating Divide FFT/DCT [Single]
 123
 124 A-Form
 125
 126 * fdivso FRT,FRA,FRB (Rc=0)
 127 * fdivso. FRT,FRA,FRB (Rc=1)
 128
 129 Pseudo-code:
 130
 131     FRT <- FPDIV32(FRA, FRB)
 132     FRS <- FPDIV32(FRA, FRB, -1)
 133
 134 Special Registers Altered:
 135
 136     FPRF FR FI
 137     FX OX UX XX
 138     VXSNAN VXISI
 139     CR1          (if Rc=1)
 140
 141 # Floating Divide FFT/DCT [Double]
 142
 143 A-Form
 144
 145 * fdivo FRT,FRA,FRB (Rc=0)
 146 * fdivo. FRT,FRA,FRB (Rc=1)
 147
 148 Pseudo-code:
 149
 150     FRT <- FPDIV64(FRA, FRB)
 151     FRS <- FPDIV64(FRA, FRB, -1)
 152
 153 Special Registers Altered:
 154
 155     FPRF FR FI
 156     FX OX UX XX
 157     VXSNAN VXISI
 158     CR1          (if Rc=1)
 159
 160 # Floating Multiply-Add FFT/DCT [Single]
 161
 162 A-Form
 163
 164 * fmaddso FRT,FRA,FRC,FRB (Rc=0)
 165 * fmaddso. FRT,FRA,FRC,FRB (Rc=1)
 166
 167 Pseudo-code:
 168
 169     FRT <- FPMULADD32(FRA, FRC, FRB, 1, 1)
 170     FRS <- FPMULADD32(FRA, FRC, FRB, 1, -1)
 171
 172 Special Registers Altered:
 173
 174     FPRF FR FI
 175     FX OX UX XX
 176     VXSNAN VXISI VXIMZ
 177     CR1          (if Rc=1)
 178
 179 # Floating Multiply-Sub FFT/DCT [Single]
 180
 181 A-Form
 182
 183 * fmsubso FRT,FRA,FRC,FRB (Rc=0)
 184 * fmsubso. FRT,FRA,FRC,FRB (Rc=1)
 185
 186 Pseudo-code:
 187
 188     FRT <- FPMULADD32(FRA, FRC, FRB, 1, -1)
 189     FRS <- FPMULADD32(FRA, FRC, FRB, 1, 1)
 190
 191 Special Registers Altered:
 192
 193     FPRF FR FI
 194     FX OX UX XX
 195     VXSNAN VXISI VXIMZ
 196     CR1          (if Rc=1)
 197
 198 # Floating Negative Multiply-Add FFT/DCT [Single]
 199
 200 A-Form
 201
 202 * fnmaddso FRT,FRA,FRC,FRB (Rc=0)
 203 * fnmaddso. FRT,FRA,FRC,FRB (Rc=1)
 204
 205 Pseudo-code:
 206
 207     FRT <- FPMULADD32(FRA, FRC, FRB, -1, -1)
 208     FRS <- FPMULADD32(FRA, FRC, FRB, -1, 1)
 209
 210 Special Registers Altered:
 211
 212     FPRF FR FI
 213     FX OX UX XX
 214     VXSNAN VXISI VXIMZ
 215     CR1          (if Rc=1)
 216
 217 # Floating Negative Multiply-Sub FFT/DCT [Single]
 218
 219 A-Form
 220
 221 * fnmsubso FRT,FRA,FRC,FRB (Rc=0)
 222 * fnmsubso. FRT,FRA,FRC,FRB (Rc=1)
 223
 224 Pseudo-code:
 225
 226     FRT <- FPMULADD32(FRA, FRC, FRB, -1, 1)
 227     FRS <- FPMULADD32(FRA, FRC, FRB, -1, -1)
 228
 229 Special Registers Altered:
 230
 231     FPRF FR FI
 232     FX OX UX XX
 233     VXSNAN VXISI VXIMZ
 234     CR1          (if Rc=1)
 235