10 SRR1[0:32] <- MSR[0:32]
11 SRR1[37:41] <- MSR[37:41]
12 SRR1[48:63] <- MSR[48:63]
14 NIA <- 0x0000_0000_0000_0C00
16 Special Registers Altered:
20 # System Call Vectored
27 SRR1[33:36] <- undefined
28 SRR1[42:47] <- undefined
29 SRR1[0:32] <- MSR[0:32]
30 SRR1[37:41] <- MSR[37:41]
31 SRR1[48:63] <- MSR[48:63]
35 Special Registers Altered:
39 # Return From System Call Vectored
45 if (MSR[29:31] != 0b010) | (CTR[29:31] != 0b000) then
46 MSR[29:31] <- CTR[29:31]
51 MSR[4:28] <- CTR[4:28]
53 MSR[37:41] <- CTR[37:41]
54 MSR[49:50] <- CTR[49:50]
55 MSR[52:57] <- CTR[52:57]
56 MSR[60:63] <- CTR[60:63]
57 NIA <-iea LR[0:61] || 0b00
59 Special Registers Altered:
63 # Return From Interrupt Doubleword
69 MSR[51] <- (MSR[3] & SRR1[51]) | ((¬MSR[3] & MSR[51]))
70 MSR[3] <- (MSR[3] & SRR1[3])
71 if (MSR[29:31] != 0b010) | (SRR1[29:31] != 0b000) then
72 MSR[29:31] <- SRR1[29:31]
73 MSR[48] <- SRR1[48] | SRR1[49]
74 MSR[58] <- SRR1[88] | SRR1[49]
75 MSR[59] <- SRR1[59] | SRR1[49]
77 MSR[4:28] <- SRR1[4:28]
79 MSR[37:41] <- SRR1[37:41]
80 MSR[49:50] <- SRR1[49:50]
81 MSR[52:57] <- SRR1[52:57]
82 MSR[60:63] <- SRR1[60:63]
83 NIA <-iea SRR0[0:61] || 0b00
85 Special Registers Altered:
89 # Hypervisor Return From Interrupt Doubleword
95 if (MSR[29:31] != 0b010) | (HSRR1[29:31] != 0b000) then
96 MSR[29:31] <- HSRR1[29:31]
97 MSR[48] <- HSRR1[48] | HSRR1[49]
98 MSR[58] <- HSRR1[88] | HSRR1[49]
99 MSR[59] <- HSRR1[59] | HSRR1[49]
100 MSR[0:28] <- HSRR1[0:28]
102 MSR[37:41] <- HSRR1[37:41]
103 MSR[49:57] <- HSRR1[49:57]
104 MSR[60:63] <- HSRR1[60:63]
105 NIA <-iea HSRR0[0:61] || 0b00
107 Special Registers Altered: