12 SRR1[0:32] <- MSR[0:32]
13 SRR1[37:41] <- MSR[37:41]
14 SRR1[48:63] <- MSR[48:63]
16 NIA <- 0x0000_0000_0000_0C00
18 Special Registers Altered:
22 # System Call Vectored
31 SRR1[33:36] <- undefined
32 SRR1[42:47] <- undefined
33 SRR1[0:32] <- MSR[0:32]
34 SRR1[37:41] <- MSR[37:41]
35 SRR1[48:63] <- MSR[48:63]
39 Special Registers Altered:
43 # Return From System Call Vectored
51 if (MSR[29:31] != 0b010) | (CTR[29:31] != 0b000) then
52 MSR[29:31] <- CTR[29:31]
57 MSR[4:28] <- CTR[4:28]
59 MSR[37:41] <- CTR[37:41]
60 MSR[49:50] <- CTR[49:50]
61 MSR[52:57] <- CTR[52:57]
62 MSR[60:63] <- CTR[60:63]
63 NIA <-iea LR[0:61] || 0b00
65 Special Registers Altered:
69 # Return From Interrupt Doubleword
77 MSR[51] <- (MSR[3] & SRR1[51]) | ((¬MSR[3] & MSR[51]))
78 MSR[3] <- (MSR[3] & SRR1[3])
79 if (MSR[29:31] != 0b010) | (SRR1[29:31] != 0b000) then
80 MSR[29:31] <- SRR1[29:31]
81 MSR[48] <- SRR1[48] | SRR1[49]
82 MSR[58] <- SRR1[88] | SRR1[49]
83 MSR[59] <- SRR1[59] | SRR1[49]
85 MSR[4:28] <- SRR1[4:28]
87 MSR[37:41] <- SRR1[37:41]
88 MSR[49:50] <- SRR1[49:50]
89 MSR[52:57] <- SRR1[52:57]
90 MSR[60:63] <- SRR1[60:63]
91 NIA <-iea SRR0[0:61] || 0b00
93 Special Registers Altered:
97 # Hypervisor Return From Interrupt Doubleword
105 if (MSR[29:31] != 0b010) | (HSRR1[29:31] != 0b000) then
106 MSR[29:31] <- HSRR1[29:31]
107 MSR[48] <- HSRR1[48] | HSRR1[49]
108 MSR[58] <- HSRR1[88] | HSRR1[49]
109 MSR[59] <- HSRR1[59] | HSRR1[49]
110 MSR[0:28] <- HSRR1[0:28]
112 MSR[37:41] <- HSRR1[37:41]
113 MSR[49:57] <- HSRR1[49:57]
114 MSR[60:63] <- HSRR1[60:63]
115 NIA <-iea HSRR0[0:61] || 0b00
117 Special Registers Altered: