openpower/isans_letter.mdwn

   1 # Letter regarding ISAMUX / NS
   2
   3 * Revision 0.0 draft: 03 Mar 2020
   4 * Revision 0.1 addw review: 16 Apr 2020
   5 * Revision 0.9 pre-final: 18 Apr 2020
   6 * Revision 0.91 mention dual ISA: 22 Apr 2020
   7
   8 ## Why has Libre-SOC chosen PowerPC ?
   9
  10 For a hybrid CPU-VPU-GPU, intended for mass-volume adoption in tablets,
  11 netbooks, chromebooks and industrial embedded (SBC) systems, our choice
  12 was between Nyuzi, MIAOW, RISC-V, PowerPC, MIPS and OpenRISC.
  13
  14 Of all the options, the PowerPC architecture is more complete and far more
  15 mature.  It also has a deeper adoption by Linux distributions.
  16
  17 Following IBM's release of the Power Architecture instruction set to the
  18 Linux Foundation in August 2019 the barrier to using it is no more than
  19 that of using RISC-V.  We are encouraged that the OpenPOWER Foundation is
  20 supportive of what we are doing and helping, e.g by putting us in touch
  21 with people who can help us.
  22
  23 ## Summary
  24
  25 * We propose the standardisation of the way that the PowerPC Instruction
  26   Set Architecture (PPC ISA) is extended, enabling many different flavours
  27   within a well supported family to co-exist, long-term, without conflict,
  28   right across the board.
  29 * This is about more than just our project. Our proposals will facilitate
  30   the use of PPC in novel or niche applications without breaking the PPC
  31   ISA into incompatible islands.
  32 * PPC will gain a competitive market advantage by removing the need
  33   for separate VPU or GPU functions in RTL or ASICs thus enabling lower
  34   cost systems.  Libre-SOC's project is to extend the PPC to integrate
  35   the GPU and VPU functionality directly as part of the PPC ISA (example:
  36   Broadcom VideoCore IV being based around extensions to an ARC core).
  37 * Libre-SOC's extensions will be easily adopted, as the standard GNU/Linux
  38   distributions will very deliberately run unmodified on our ISA,
  39   including full compatibility with illegal instruction trap requirements.
  40
  41 ## One CPU multiple ISAs
  42
  43 This is a quick overview of the way that we would like to add changes
  44 that we are proposing to the PowerPC instruction set (ISA).  It is based on
  45 a Open Standardisation of the way that existing "mode switches",
  46 already found in the POWER instruction set, are added:
  47
  48 * FPSCR's "NI" bit, setting non-IEEE754 FP mode
  49 * MSR's "LE" bit (and associated HILE bit), setting little-endian mode
  50 * MSR's "SF" bit, setting either 32-bit or 64-bit mode
  51 * PCR's "compatibility" bits 60-62, V2.05 V2.06 V2.07 mode
  52
  53 [It is well-noted that unless each "mode switch" bit is set, any
  54 alternative (additional) instructions (and functionality) are completely
  55 inaccessible, and will result in "illegal instruction" traps being thrown.
  56 This is recognised as being critically important.]
  57
  58 These bits effectively create multiple, incompatible run-time switchable ISAs
  59 within one CPU.  They are selectable for the needs of the individual
  60 program (or OS) being run.
  61
  62 All of these bits are set by an instruction, that, once set, radically
  63 changes the entire behaviour and characteristics of subsequent instructions.
  64
  65 With these (and other) long-established precedents already in POWER,
  66 there is therefore essentially conceptually nothing new about what we
  67 propose: we simply seek that the process by which such "switching" is
  68 added is formalised and standardised, such that we (and others, including
  69 IBM itself) have a clear, well-defined standards-non-disruptive, atomic
  70 and non-intrusive path to extend the POWER ISA for use in markets that
  71 it presently cannot enter.
  72
  73 We advocate that some of "mode-setting" (escape-sequencing) bits be
  74 binary encoded, some unary encoded, and that some space marked for
  75 "offical" use, some "experimental", some "custom" and some "reserved".
  76 The available space in a suitably-chosen SPR to be formalised, and
  77 recommend the OpenPOWER Foundation be given the IANA-like role in
  78 atomically allocating mode bits.
  79
  80 Instructions that we need to add, which are a normal part of GPUs,
  81 include ATAN2, LOG, NORMALISE, YUV2RGB, Khronos Compliance FP mode
  82 (different from both IEEE754 and "NI" mode), and many more.  Many of
  83 these may turn out to be useful in a wider context: they however need
  84 to be fully isolated behind "mode-setting".
  85
  86 Some mode-setting instructions are privileged, ie can only be set by
  87 the kernel (eg 32 or 64 bit mode). Most of the escape sequences that we
  88 propose will be (have to be) usable without the need for an expensive
  89 system call overhead (because some of the instructions needed will be
  90 in extremely tight inner loops).
  91
  92 # About Libre-SOC Commercial Project
  93
  94 The Libre-SOC Commercial Product is a hybrid GPU-GPU-VPU intended for
  95 mass-volume production.  There is no separate GPU, because the CPU
  96 *is* the GPU.  There is no separate VPU, because the CPU *is* the GPU.
  97 There is not even a separate pipeline: the CPU pipelines *are* the
  98 GPU and VPU pipelines.
  99
 100 Closest equivalents include the ARC core (which has VPU extensions and
 101 3D extensions in the form of Broadcom's VideoCore IV) and the ICubeCorp
 102 IC3128.  Both are considered "hybrid" CPU-GPU-VPU processors.
 103
 104 "Normal" Commercial GPUs are entirely separate processors.  The development
 105 cost and complexity purely in terms of Software Drivers alone is immense.
 106 We reject that approach (and as a small team we do not have the resources
 107 anyway).
 108
 109 With the project being Libre - not proprietary and secretive and never
 110 to be published, ever - it is no good having the extensions as "custom"
 111 because "custom" is specifically for the cases where the augmented
 112 toolchain is never, under any circumstances, published and made public by
 113 the proprietary company (and would never be accepted upstream anyway).
 114 For business commercial reasons, Libre-SOC is the total opposite of this
 115 proprietary, secretive approach.
 116
 117 Therefore, to meet our business objectives:
 118
 119 * As shown from Nyuzi and Larrabee, although ideally suited to high
 120   performance compute tasks, a "traditional" general-purpose full
 121   IEEE754-compliant Vector ISA (such as that in POWER9) is not an adequate
 122   basis for a commercially competitive GPU.  Nyuzi's conclusion is that
 123   using such general-purpose Vector ISAs results in reaching only 25%
 124   performance (or requiring 4-fold increase in power consumption) to
 125   achieve par with current commercial-grade GPUs.
 126 * We are not going the "traditional" (separate custom GPU) route because
 127   it is not practical for a new team to design hardware and spend 8+
 128   man-years on massively complex inter-processor driver development as well
 129 * We cannot meet our objectives with a "custom extension" because the
 130   financial burden on our team to maintain a total hard fork of not just
 131   toolchains, but also entire GNU/Linux Distros, is highly undesirable,
 132   and completely impractical (we know for certain that Redhat would
 133   strongly object to any efforts to hard-fork Fedora)
 134 * We could invent our own custom GPU instruction set (or use and extend an existing one, to save a man-decade on toolchain development) however even to switch over to that "Dual ISA" GPU instruction set in the next clock cycle *still requires a PCR modeswitch bit* in order to avoid needing a full Inter-Processor Bus Architecture like on "traditional" GPUs.
 135 * If extending any instruction set, rather than have a Dual ISA (which needs the PCR modeswitch bit to access it) we would rather extend POWER.
 136 * We cannot "go ahead anyway" because to do so would be highly irresponsible
 137   and cause massive disruption to the POWER community.
 138
 139 With all impractical options eliminated the only remaining responsible
 140 option is to extend the POWER ISA in an atomically-managed (IANA-style)
 141 formal fashion, whilst (critically and absolutely essentially) always
 142 providing a PCR compatibility mode that is fully POWER compliant, including
 143 all illegal instruction traps.
 144