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97 % set default figure placement to htbp
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108 \addcontentsline{toc
}{chapter
}{Preamble
} \markboth{INTRODUCTION
}{}
110 This
document is an auto-generated version of the Draft SVP64
111 Specification available at
114 https://libre-soc.org/openpower/sv
117 for which the source code is available at
120 https://git.libre-soc.org/?p=libreriscv.git;a=tree;f=openpower;hb=HEAD
123 This PDF may be created with "make pdf" from the following file:
126 https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/Makefile;hb=HEAD
129 by executing the following commands:
132 git clone https://git.libre-soc.org/git/libreriscv.git libresoc
133 cd libresoc/libresoc/openpower
137 Simple-V Cray-style Vectors have been developed by the Libre-SOC Team,
138 sponsored by the NLnet Foundation and NGI POINTER under
139 EU Grants
871528 and
957073.
141 Simple-V is in DRAFT Status and will be submitted publicly
142 (non-confidentially) through the OPF ISA WG "External Submissions"
143 Process. Funding from NLnet, through their Privacy and Enhanced Trust
144 Programme, requires full transparency.
148 \part{Scalable Vectors
}
150 \chapter{Scalable Vectors for the Power ISA
}
151 \hypertarget{svux2fscalvecpowisa
}{}
152 \hypertarget{SVux7csv
}{}
153 \input{tex_out/sv.tex
}
154 \chapter{Other Vector ISAs
}\hypertarget{svux2fvector_isa_comparison
}{}
155 \input{tex_out/vector_isas.tex
}
156 \chapter{Overview
}\hypertarget{svux2foverview
}{}
157 \input{tex_out/overview.tex
}
158 \chapter{Compliancy Levels
}\hypertarget{svux2fcompliancy_levels
}{}
159 \input{tex_out/compliancy_levels.tex
}
160 \chapter{SVP64
}\hypertarget{svux2fsvp64
}{}
161 \input{tex_out/svp64.tex
}
162 \chapter{SPRs
}\hypertarget{svux2fsprs
}{}
163 \input{tex_out/sprs.tex
}
164 \chapter{Arithmetic Mode
}\hypertarget{svux2fnormal
}{}
165 \input{tex_out/normal.tex
}
166 \chapter{Load/Store Mode
}\hypertarget{svux2fldst
}{}
167 \input{tex_out/ldst.tex
}
168 \chapter{Condition Register Fields Mode
}\hypertarget{svux2fcr_ops
}{}
169 \input{tex_out/cr_ops.tex
}
170 \chapter{Branch Mode
}\hypertarget{svux2fbranches
}{}
171 \input{tex_out/branches.tex
}
172 \chapter{setvl instruction
}\hypertarget{svux2fsetvl
}{}
173 \input{tex_out/setvl.tex
}
174 \chapter{svstep instruction
}\hypertarget{svux2fsvstep
}{}
175 \input{tex_out/svstep.tex
}
176 \chapter{REMAP subsystem
}\hypertarget{svux2fremap
}{}
177 \input{tex_out/remap.tex
}
178 \chapter{Swizzle Move
}\hypertarget{svux2fmv.swizzle
}{}
179 \input{tex_out/mv_swizzle.tex
}
180 \chapter{Pack / Unpack
}\hypertarget{svux2fmv.vec
}{}
181 \input{tex_out/mv_vec.tex
}
184 \chapter{SVP64 Appendix
}\hypertarget{svp64ux2fappendix
}{}
185 \input{tex_out/svp64_appendix.tex
}
186 \chapter{SVP64 Quirks
}\hypertarget{svux2fsvp64_quirks
}{}
187 \input{tex_out/svp64_quirks.tex
}
188 \chapter{Simple-V pseudocode
}\hypertarget{svux2fpseudocode_simplev
}{}
189 \input{tex_out/pseudocode_simplev.tex
}
190 \chapter{SVP64 Augmentation Table
}\hypertarget{opcode_regs_deduped
}{}
193 \fontsize{7}{9}\selectfont
194 \input{tex_out/opcode_regs_deduped.tex
}
199 \part{Scalar Instructions
}
201 \chapter{Vector Assist ops
}\hypertarget{svux2fvector_ops
}{}
202 \input{tex_out/vector_ops.tex
}
203 \chapter{CR Weird ops
}\hypertarget{svux2fcr_int_predication
}{}
204 \input{tex_out/cr_int_predication.tex
}
205 \chapter{Bitmanip ops
}\hypertarget{svux2fbitmanip
}{}
206 \input{tex_out/bitmanip.tex
}
207 \chapter{FP/Integer conversion ops
}\hypertarget{svux2fint_fp_mv
}{}
208 \input{tex_out/int_fp_mv.tex
}
209 \chapter{FP Class ops
}\hypertarget{svux2ffclass
}{}
210 \input{tex_out/fclass.tex
}
211 \chapter{Audio/Video ops
}\hypertarget{svux2fav_opcodes
}{}
212 \input{tex_out/av_opcodes.tex
}
213 \chapter{Big Integer
}\hypertarget{svux2fbiginteger
}{}
214 \input{tex_out/big_integer.tex
}
217 \chapter{Big Integer Analysis
}\hypertarget{svux2fbigintegerux2fanalysis
}{}
218 \input{tex_out/big_integer_analysis.tex
}
219 \chapter{Bitmanip pseudocode
}\hypertarget{svux2fpseudocode_bitmanip
}{}
220 \input{tex_out/pseudocode_bitmanip.tex
}
221 \chapter{Floating Point pseudocode
}\hypertarget{svux2fpseudocode_svfparith
}{}
222 \input{tex_out/pseudocode_svfparith.tex
}
223 \chapter{Fixed Point pseudocode
}
224 \hypertarget{svux2fpseudocode_svfixedarith
}{}
225 \input{tex_out/pseudocode_svfixedarith.tex
}
228 \part{Scalar Power ISA pseudocode
}
231 \addcontentsline{toc
}{chapter
}{Preamble
} \markboth{INTRODUCTION
}{}
233 This section contains updated pseudocode from the Power ISA Specification
234 v3.0B to be executable. Several bugfixes in Power ISA v3.0B have been
235 found and reported as a direct result due to actually running the
236 pseudocode as executable code in a Simulator.
237 A Formal Correctness Proof Research Paper written by Boris
240 Additionally, with SVP64 performing element-width over-rides it is the
241 \textit{Scalar
} pseudocode that needs adapting to variable-length
242 (
\textbf{XLEN
}). Maintaining duplicate identical copies in every
243 respect
\textit{except
} for an XLEN as part of the Simple-V Specification
244 is completely pointless and a waste of time: the updates to include
246 of the Scalar Power ISA Specification. This has the added benefit
247 that it makes life much easier for
32-bit implementors, and has an
248 additional benefit of making it possible for the Scalar Power ISA
249 to extend to
128-bit in future (like RV128).
252 \chapter{Fixed Point Arithmetic pseudocode
}
253 \hypertarget{svux2fpseudocode_fixedarith
}{}
254 \input{tex_out/pseudocode_fixedarith.tex
}
255 \chapter{Fixed Point Logical pseudocode
}
256 \hypertarget{svux2fpseudocode_fixedlogical
}{}
257 \input{tex_out/pseudocode_fixedlogical.tex
}