openpower/simple_v_spec.tex

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 107 \fi
 108
 109 % set default figure placement to htbp
 110 \makeatletter\@addtoreset{chapter}{part}\makeatother%
 111 \def\fps@figure{htbp}
 112 \makeatother
 113
 114 % graphics path for primer
 115 \graphicspath{ {svp64-primer/img/} }
 116
 117 \date{}
 118
 119 \begin{document}
 120
 121 \chapter*{Preamble}
 122 \addcontentsline{toc}{chapter}{Preamble} \markboth{INTRODUCTION}{}
 123
 124 \textbf{Last modified date: \today}
 125
 126 This document is an auto-generated version of the Draft SVP64
 127 Specification available at
 128
 129 \begin{verbatim}
 130      https://libre-soc.org/openpower/sv
 131 \end{verbatim}
 132
 133 for which the source code is available at
 134
 135 \begin{verbatim}
 136      https://git.libre-soc.org/?p=libreriscv.git;a=tree;f=openpower;hb=HEAD
 137 \end{verbatim}
 138
 139 This PDF may be created with "make pdf" from the following file:
 140
 141 \begin{verbatim}
 142     https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/Makefile;hb=HEAD
 143 \end{verbatim}
 144
 145 by executing the following commands:
 146
 147 \begin{verbatim}
 148     git clone https://git.libre-soc.org/git/libreriscv.git libresoc
 149     cd libresoc/libresoc/openpower
 150     make pdf
 151 \end{verbatim}
 152
 153 Simple-V Cray-style Vectors have been developed by the Libre-SOC Team,
 154 sponsored by the NLnet Foundation and NGI POINTER under
 155 EU Grants 871528 and 957073.
 156
 157 Simple-V is in DRAFT Status and will be submitted publicly
 158 (non-confidentially) through the OPF ISA WG "External Submissions"
 159 Process. Funding from NLnet, through their Privacy and Enhanced Trust
 160 Programme, requires full transparency.
 161
 162 As this document is under continuous rapid revision please check frequently
 163 at:
 164
 165 \begin{verbatim}
 166     https://ftp.libre-soc.org/simple_v_spec.pdf
 167 \end{verbatim}
 168
 169 \subsection*{Contacts}
 170 \begin{itemize}
 171     \itemsep -0.2em
 172     \item Luke Kenneth Casson Leighton - Libre-SOC team lead and Red
 173     Semiconductor Ltd Director - lkcl@lkcl.net
 174     \item David Calderwood - Red Semiconductor Ltd Director -
 175     djac@calderwoodhan.com
 176     \item Toshaan Bharvani - OpenPOWER Foundation Technical Chair, VanTosh
 177     Director - toshaan@vantosh.com
 178     \item Dmitry Selyutin - Libre-SOC engineer, working on binutils SVP64 assembler - ghostmansd@gmail.com
 179     \item Jacob Lifshay - Libre-SOC engineer, CPU arch and verification - programmerjake@gmail.com
 180     \item Cesar Strauss - Libre-SOC engineer, CPU arch and verification - cestrauss@gmail.com
 181     \item Andrey Miroshnikov - Libre-SOC engineer, assisting with documentation - andrey@technepisteme.xyz
 182 \end{itemize}
 183
 184 \part{Scalable Vectors Primer}
 185 \input{svp64-primer/acronyms}
 186 \chapter*{Executive Summary}
 187 \include{svp64-primer/summary}
 188 \bibliography{svp64-primer/references}
 189 \bibliographystyle{ieeetr}
 190
 191 \tableofcontents
 192
 193 \part{Scalable Vectors}
 194
 195
 196 \chapter{Fields and Forms}
 197 \hypertarget{svux2ffields}{}
 198 \input{tex_out/fields.tex}
 199 \chapter{Scalable Vectors for the Power ISA}
 200 \hypertarget{svux2fscalvecpowisa}{}
 201 \hypertarget{SVux7csv}{}
 202 \input{tex_out/sv.tex}
 203 \chapter{Other Vector ISAs}\hypertarget{svux2fvector_isa_comparison}{}
 204 \input{tex_out/vector_isas.tex}
 205 \chapter{Overview}\hypertarget{svux2foverview}{}
 206 \input{tex_out/overview.tex}
 207 \chapter{Compliancy Levels}\hypertarget{svux2fcompliancy_levels}{}
 208 \input{tex_out/compliancy_levels.tex}
 209 \chapter{SVP64}\hypertarget{svux2fsvp64}{}
 210 \input{tex_out/svp64.tex}
 211 \chapter{SPRs}\hypertarget{svux2fsprs}{}
 212 \input{tex_out/sprs.tex}
 213 \chapter{Arithmetic Mode}\hypertarget{svux2fnormal}{}
 214 \input{tex_out/normal.tex}
 215 \chapter{Load/Store Mode}\hypertarget{svux2fldst}{}
 216 \input{tex_out/ldst.tex}
 217 \chapter{Condition Register Fields Mode}\hypertarget{svux2fcr_ops}{}
 218 \input{tex_out/cr_ops.tex}
 219 \chapter{Branch Mode}\hypertarget{svux2fbranches}{}
 220 \input{tex_out/branches.tex}
 221 \chapter{setvl instruction}\hypertarget{svux2fsetvl}{}
 222 \input{tex_out/setvl.tex}
 223 \chapter{svstep instruction}\hypertarget{svux2fsvstep}{}
 224 \input{tex_out/svstep.tex}
 225 \chapter{REMAP subsystem}\hypertarget{svux2fremap}{}
 226 \input{tex_out/remap.tex}
 227 \chapter{Swizzle Move}\hypertarget{svux2fmv.swizzle}{}
 228 \input{tex_out/mv_swizzle.tex}
 229 \chapter{Pack / Unpack}\hypertarget{svux2fmv.vec}{}
 230 \input{tex_out/mv_vec.tex}
 231
 232 \begin{appendices}
 233 \chapter{SVP64 Appendix}\hypertarget{svp64ux2fappendix}{}
 234 \hypertarget{svux2fsvp64ux2fappendix}{}
 235 \input{tex_out/svp64_appendix.tex}
 236 \chapter{SVP64 Quirks}\hypertarget{svux2fsvp64_quirks}{}
 237 \input{tex_out/svp64_quirks.tex}
 238 \chapter{REMAP algorithms}\hypertarget{svux2fremapux2fappendix}{}
 239 \input{tex_out/remap_appendix.tex}
 240 \chapter{Simple-V pseudocode}\hypertarget{svux2fpseudocode_simplev}{}
 241 \input{tex_out/pseudocode_simplev.tex}
 242
 243 \chapter{SVP64 Augmentation Table}\hypertarget{opcode_regs_deduped}{}
 244 \begin{landscape}
 245 {
 246 \fontsize{7}{9}\selectfont
 247 \input{tex_out/opcode_regs_deduped.tex}
 248 }
 249 \end{landscape}
 250
 251 \chapter{Comparison Table}\hypertarget{svux2fcomparison_table}{}
 252 \begin{landscape}
 253 {
 254 \fontsize{7}{9}\selectfont
 255 \input{tex_out/comparison_table.tex}
 256 }
 257 \end{landscape}
 258
 259 \end{appendices}
 260
 261 \part{Scalar Instructions}
 262
 263 \chapter{SV Vector ops}\hypertarget{svux2fvector_ops}{}
 264 \input{tex_out/vector_ops.tex}
 265 \chapter{CR Weird ops}\hypertarget{svux2fcr_int_predication}{}
 266 \hypertarget{cr_int_predication}{}
 267 \input{tex_out/cr_int_predication.tex}
 268 \chapter{Bitmanip ops}\hypertarget{svux2fbitmanip}{}
 269 \input{tex_out/bitmanip.tex}
 270 \chapter{FP/Int Conversion ops}\hypertarget{svux2fint_fp_mv}{}
 271 \input{tex_out/int_fp_mv.tex}
 272 \chapter{FP Class ops}\hypertarget{svux2ffclass}{}
 273 \input{tex_out/fclass.tex}
 274 \chapter{Audio and Video Opcodes}\hypertarget{svux2fav_opcodes}{}
 275 \hypertarget{av_opcodes}{}
 276 \input{tex_out/av_opcodes.tex}
 277 \chapter{Big Integer}\hypertarget{svux2fbiginteger}{}
 278 \input{tex_out/big_integer.tex}
 279 \chapter{Transcendentals}\hypertarget{transcendentals}{}
 280 \input{tex_out/transcendentals.tex}
 281 \chapter{Acquire/Release Atomic Memory}\hypertarget{atomics}{}
 282 \input{tex_out/atomics.tex}
 283
 284 \begin{appendices}
 285 \chapter{Big Integer Analysis}\hypertarget{svux2fbigintegerux2fanalysis}{}
 286 \input{tex_out/big_integer_analysis.tex}
 287 \chapter{Bitmanip pseudocode}\hypertarget{svux2fpseudocode_bitmanip}{}
 288 \input{tex_out/pseudocode_bitmanip.tex}
 289 \chapter{Floating Point pseudocode}\hypertarget{isaux2fsvfparith}{}
 290 \input{tex_out/pseudocode_svfparith.tex}
 291 \chapter{Fixed Point pseudocode}
 292 \hypertarget{isaux2fsvfixedarith}{}
 293 \input{tex_out/pseudocode_svfixedarith.tex}
 294 \end{appendices}
 295
 296 \part{Scalar Power ISA pseudocode}
 297 \backmatter % temporary fix for too many appenfices
 298 %\setcounter{chapter}{0}
 299 %\renewcommand{\thechapter}{\Alph{chapter}}
 300
 301 \chapter*{Preamble}
 302 \addcontentsline{toc}{chapter}{Preamble} \markboth{INTRODUCTION}{}
 303
 304 This section contains updated pseudocode from the Power ISA Specification
 305 v3.0B to be executable.  Several bugfixes in Power ISA v3.0B have been
 306 found and reported as a direct result due to actually running the
 307 pseudocode as executable code in a Simulator.
 308 A Formal Correctness Proof Research Paper written by Boris
 309 Shingarov.
 310
 311 Additionally, with SVP64 performing element-width over-rides it is the
 312 \textit{Scalar} pseudocode that needs adapting to variable-length
 313 (\textbf{XLEN}).  Maintaining duplicate identical copies in every
 314 respect \textit{except} for an XLEN as part of the Simple-V Specification
 315 is completely pointless and a waste of time: the updates to include
 316 XLEN need to be part
 317 of the Scalar Power ISA Specification.  This has the added benefit
 318 that it makes life much easier for 32-bit implementors, and has an
 319 additional benefit of making it possible for the Scalar Power ISA
 320 to extend to 128-bit in future (like RV128).
 321
 322 \begin{appendices}
 323 \chapter{Binary Coded Decimal pseudocode}
 324 \hypertarget{svux2fpseudocode_bcd}{}
 325 \input{tex_out/pseudocode_bcd.tex}
 326 \chapter{Branch pseudocode}
 327 \hypertarget{openpowerux2fisaux2fbranch}{}
 328 \hypertarget{svux2fpseudocode_branch}{}
 329 \input{tex_out/pseudocode_branch.tex}
 330 \chapter{Fixed Point Compare pseudocode}
 331 \hypertarget{svux2fpseudocode_comparefixed}{}
 332 \input{tex_out/pseudocode_comparefixed.tex}
 333 \chapter{Condition Register pseudocode}
 334 \hypertarget{svux2fpseudocode_condition}{}
 335 \input{tex_out/pseudocode_condition.tex}
 336
 337 \chapter{Fixed Point Arithmetic pseudocode}
 338 \hypertarget{svux2fpseudocode_fixedarith}{}
 339 \input{tex_out/pseudocode_fixedarith.tex}
 340 \chapter{Fixed Point Load pseudocode}
 341 \hypertarget{svux2fpseudocode_fixedload}{}
 342 \input{tex_out/pseudocode_fixedload.tex}
 343 \chapter{Fixed Point Logical pseudocode}
 344 \hypertarget{svux2fpseudocode_fixedlogical}{}
 345 \input{tex_out/pseudocode_fixedlogical.tex}
 346 \chapter{Fixed Point Rotate pseudocode}
 347 \hypertarget{svux2fpseudocode_fixedshift}{}
 348 \input{tex_out/pseudocode_fixedshift.tex}
 349
 350 \chapter{Fixed Point Store pseudocode}
 351 \hypertarget{svux2fpseudocode_fixedstore}{}
 352 \input{tex_out/pseudocode_fixedstore.tex}
 353 \chapter{Fixed Point Trap pseudocode}
 354 \hypertarget{svux2fpseudocode_fixedtrap}{}
 355 \input{tex_out/pseudocode_fixedtrap.tex}
 356 \chapter{Special Purpose Register pseudocode}
 357 \hypertarget{svux2fpseudocode_sprset}{}
 358 \input{tex_out/pseudocode_sprset.tex}
 359 \chapter{String Load/Store pseudocode}
 360 \hypertarget{svux2fpseudocode_stringldst}{}
 361 \input{tex_out/pseudocode_stringldst.tex}
 362 \chapter{System Call pseudocode}
 363 \hypertarget{svux2fpseudocode_system}{}
 364 \input{tex_out/pseudocode_system.tex}
 365
 366 \chapter{Floating Point Load pseudocode}
 367 \hypertarget{svux2fpseudocode_fpload}{}
 368 \input{tex_out/pseudocode_fpload.tex}
 369 \chapter{Floating Point Store pseudocode}
 370 \hypertarget{svux2fpseudocode_fpstore}{}
 371 \input{tex_out/pseudocode_fpstore.tex}
 372 \chapter{Floating Point Move pseudocode}
 373 \hypertarget{svux2fpseudocode_fpmove}{}
 374 \input{tex_out/pseudocode_fpmove.tex}
 375 \chapter{Floating Point Arithmetic pseudocode}
 376 \hypertarget{svux2fpseudocode_fparith}{}
 377 \input{tex_out/pseudocode_fparith.tex}
 378 \chapter{Floating Point Integer Conversion pseudocode}
 379 \hypertarget{svux2fpseudocode_fpcvt}{}
 380 \input{tex_out/pseudocode_fpcvt.tex}
 381
 382 \end{appendices}
 383
 384
 385
 386
 387 \end{document}