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100 % Fix footnotes in tables (requires footnote package)
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114 \ifx\paragraph\undefined\else
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123 % set default figure placement to htbp
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125 \def\fps@figure
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128 % graphics path for primer
129 \graphicspath{ {svp64-primer/img/
} }
136 \addcontentsline{toc
}{chapter
}{Preamble
} \markboth{INTRODUCTION
}{}
138 \textbf{Last modified date:
\today}
140 This
document is an auto-generated version of the Draft SVP64
141 Specification available at
144 https://libre-soc.org/openpower/sv
147 for which the source code is available at
150 https://git.libre-soc.org/?p=libreriscv.git;a=tree;f=openpower;hb=HEAD
153 This PDF may be created with "make pdf" from the following file:
156 https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/Makefile;hb=HEAD
159 by executing the following commands:
162 git clone https://git.libre-soc.org/git/libreriscv.git libresoc
163 cd libresoc/libresoc/openpower
167 Simple-V Cray-style Vectors have been developed by the Libre-SOC Team,
168 sponsored by the NLnet Foundation and NGI POINTER under
169 EU Grants
871528 and
957073.
171 Simple-V is in DRAFT Status and will be submitted publicly
172 (non-confidentially) through the OPF ISA WG "External Submissions"
173 Process. Funding from NLnet, through their Privacy and Enhanced Trust
174 Programme, requires full transparency.
176 As this
document is under continuous rapid revision please check frequently
180 https://ftp.libre-soc.org/simple_v_spec.pdf
183 \subsection*
{Contacts
}
184 For questions, comments, and clarification, please contact the following:
187 \item Libre-SOC ISA Dev Mailing List - libre-soc-isa@lists.libre-soc.org
188 \item Luke Kenneth Casson Leighton - Libre-SOC team lead and Red
189 Semiconductor Ltd Director - lkcl@lkcl.net
190 \item David Calderwood - Red Semiconductor Ltd Director -
191 djac@calderwoodhan.com
192 \item Toshaan Bharvani - OpenPOWER Foundation Technical Chair, VanTosh
193 Director - toshaan@vantosh.com
194 \item Konstantinos Margaritis - Engineer and Founder of VectorCamp, writing optimised assembler for a number of SIMD/Vector ISAs - konstantinos@vectorcamp.gr
195 \item Dmitry Selyutin - Libre-SOC engineer, working on binutils SVP64 assembler - ghostmansd@gmail.com
196 \item Jacob Lifshay - Libre-SOC engineer, CPU arch and verification - programmerjake@gmail.com
197 \item Cesar Strauss - Libre-SOC engineer, CPU arch and verification - cestrauss@gmail.com
198 \item Andrey Miroshnikov - Libre-SOC engineer, assisting with documentation - andrey@technepisteme.xyz
202 \subsection*
{Executive Summary
}
203 \hypertarget{svux2fexecutive_summary
}{}
204 \input{tex_out/executive_summary.tex
}
208 \addcontentsline{toc
}{chapter
}{Comparison Table
} \markboth{INTRODUCTION
}{}
209 \hypertarget{svux2fcomparison_table
}{}
211 \fontsize{6}{8}\selectfont
212 \input{tex_out/comparison_table.tex
}
216 \part{Scalable Vectors Primer
}
217 \input{svp64-primer/acronyms
}
218 %\chapter*{Executive Summary}
219 \include{svp64-primer/summary
}
220 \bibliography{svp64-primer/references
}
221 \bibliographystyle{ieeetr
}
226 \part{Scalable Vectors for the Power ISA
}
229 \chapter{Fields and Forms
}
230 \hypertarget{svux2ffields
}{}
231 \input{tex_out/fields.tex
}
232 \chapter{Scalable Vectors for the Power ISA
}
233 \hypertarget{svux2fscalvecpowisa
}{}
234 \hypertarget{SVux7csv
}{}
235 \input{tex_out/sv.tex
}
236 \chapter{Other Vector ISAs
}\hypertarget{svux2fvector_isa_comparison
}{}
237 \input{tex_out/vector_isas.tex
}
238 \chapter{Overview
}\hypertarget{svux2foverview
}{}
239 \input{tex_out/overview.tex
}
240 \chapter{Compliancy Levels
}\hypertarget{svux2fcompliancy_levels
}{}
241 \input{tex_out/compliancy_levels.tex
}
242 \chapter{SVP64
}\hypertarget{svux2fsvp64
}{}
243 \input{tex_out/svp64.tex
}
244 \chapter{SPRs
}\hypertarget{svux2fsprs
}{}
245 \input{tex_out/sprs.tex
}
246 \chapter{Arithmetic Mode
}\hypertarget{svux2fnormal
}{}
247 \input{tex_out/normal.tex
}
248 \chapter{Load/Store Mode
}\hypertarget{svux2fldst
}{}
249 \input{tex_out/ldst.tex
}
250 \chapter{Condition Register Fields Mode
}\hypertarget{svux2fcr_ops
}{}
251 \input{tex_out/cr_ops.tex
}
252 \chapter{Branch Mode
}\hypertarget{svux2fbranches
}{}
253 \input{tex_out/branches.tex
}
254 \chapter{setvl instruction
}\hypertarget{svux2fsetvl
}{}
255 \input{tex_out/setvl.tex
}
256 \chapter{svstep instruction
}\hypertarget{svux2fsvstep
}{}
257 \input{tex_out/svstep.tex
}
258 \chapter{REMAP subsystem
}\hypertarget{svux2fremap
}{}
259 \input{tex_out/remap.tex
}
260 \chapter{Swizzle Move
}\hypertarget{svux2fmv.swizzle
}{}
261 \input{tex_out/mv_swizzle.tex
}
262 \chapter{Pack / Unpack
}\hypertarget{svux2fmv.vec
}{}
263 \input{tex_out/mv_vec.tex
}
266 \chapter{SVP64 Appendix
}\hypertarget{svp64ux2fappendix
}{}
267 \hypertarget{svux2fsvp64ux2fappendix
}{}
268 \input{tex_out/svp64_appendix.tex
}
269 \chapter{SVP64 Quirks
}\hypertarget{svux2fsvp64_quirks
}{}
270 \input{tex_out/svp64_quirks.tex
}
271 \chapter{REMAP algorithms
}\hypertarget{svux2fremapux2fappendix
}{}
272 \input{tex_out/remap_appendix.tex
}
273 \chapter{Simple-V pseudocode
}\hypertarget{svux2fpseudocode_simplev
}{}
274 \input{tex_out/pseudocode_simplev.tex
}
275 \chapter{Simple-V Analysis
}\hypertarget{svux2fsv_analysis
}{}
276 \input{tex_out/sv_analysis.tex
}
278 \chapter{SVP64 Augmentation Table
}\hypertarget{opcode_regs_deduped
}{}
281 \fontsize{7}{9}\selectfont
282 \input{tex_out/opcode_regs_deduped.tex
}
289 \part{Scalar Instructions
}
291 \chapter*
{Preamble
}{}
293 As explained in the Simple-V introduction
294 these are all intentionally and specifically Scalar instructions.
295 Each section is free-standing, has no connection, dependence or
296 relationship to any other section, including no direct critical dependence
297 either way on Simple-V.
298 They have with almost no exceptions been specifically crafted to
299 have a justification for their inclusion in the Power ISA as Scalar
300 instructions purely on their own merit.
303 \item The biginteger multiply-and-add instruction is similar
304 to Intel's mulx in that it produces a pair of results.
305 \item JavaScript(tm) rounding is present in ARM as fjcvtzs
306 and would save an astounding
35 instructions with
5 branches.
307 \item Whilst there exist CR bit manipulation and copying
308 instructions there are no CR Field manipulation instructions,
309 putting pressure on GPRs if several CR fits need to be analysed.
310 \item one single instruction, bmask, is proposed that covers
311 the whole of x86 BMI1 and AMD TBM, combined, and provides more.
314 All of these have nothing to do with Simple-V at all: they make
315 the Power ISA better at modern general-purpose compute, bringing
318 That said: by a wonderful coincidence, should they be included, then
319 Simple-V's capabilities increase significantly. For example the CRweird
320 instructions combined with the bitmanip instructions, alongside
321 Vectorised Rc=
1 turn CR Fields into
322 extremely powerful Predicate masks. bmask not only
323 covers the BMI and TBM instructions of Intel and AMD it also
324 includes the RVV set-before-first and set-after-first instructions.
326 The clean and clear separation between Vectorisation Prefix and Scalar
327 Suffix is what makes it possible for both Scalar-only and Scalable-Vectors
328 to benefit. It also makes proposal much easier, as there is no
331 It is however important to note that the rationale for these instructions
332 comes from a more general-purpose modern computing paradigm that is
333 outside of IBM's much more focussed and specialist traditional customer
334 base. We deeply respect IBM's curator role of the Power ISA of the past
25
335 years as much as we appreciate their courage in transferring that role
336 to the OpenPOWER Foundation ISA Working Group.
338 \chapter{SV Vector-assist Scalar ops
}\hypertarget{svux2fvector_ops
}{}
339 \input{tex_out/vector_ops.tex
}
340 \chapter{CR Weird ops
}\hypertarget{svux2fcr_int_predication
}{}
341 \hypertarget{cr_int_predication
}{}
342 \input{tex_out/cr_int_predication.tex
}
343 \chapter{Bitmanip ops
}\hypertarget{svux2fbitmanip
}{}
344 \input{tex_out/bitmanip.tex
}
345 \chapter{FP/Int Conversion ops
}\hypertarget{svux2fint_fp_mv
}{}
346 \input{tex_out/int_fp_mv.tex
}
347 \chapter{FP Class ops
}\hypertarget{svux2ffclass
}{}
348 \input{tex_out/fclass.tex
}
349 \chapter{Audio and Video Opcodes
}\hypertarget{svux2fav_opcodes
}{}
350 \hypertarget{av_opcodes
}{}
351 \input{tex_out/av_opcodes.tex
}
352 \chapter{Big Integer
}\hypertarget{svux2fbiginteger
}{}
353 \input{tex_out/big_integer.tex
}
354 \chapter{Transcendentals
}\hypertarget{transcendentals
}{}
355 \input{tex_out/transcendentals.tex
}
356 %\chapter{Acquire/Release Atomic Memory}\hypertarget{atomics}{}
357 %\input{tex_out/atomics.tex}
360 \chapter{Big Integer Analysis
}\hypertarget{svux2fbigintegerux2fanalysis
}{}
361 \input{tex_out/big_integer_analysis.tex
}
362 \chapter{Bitmanip pseudocode
}\hypertarget{svux2fpseudocode_bitmanip
}{}
363 \input{tex_out/pseudocode_bitmanip.tex
}
364 \chapter{Floating Point pseudocode
}\hypertarget{isaux2fsvfparith
}{}
365 \input{tex_out/pseudocode_svfparith.tex
}
366 \chapter{Fixed Point pseudocode
}
367 \hypertarget{isaux2fsvfixedarith
}{}
368 \input{tex_out/pseudocode_svfixedarith.tex
}
372 \part{Scalar Power ISA pseudocode
}
373 \backmatter % temporary fix for too many appenfices
374 %\setcounter{chapter}{0}
375 %\renewcommand{\thechapter}{\Alph{chapter}}
378 \addcontentsline{toc
}{chapter
}{Preamble
} \markboth{INTRODUCTION
}{}
380 This section contains updated pseudocode from the Power ISA Specification
381 v3.0B to be executable. Several bugfixes in Power ISA v3.0B have been
382 found and reported as a direct result due to actually running the
383 pseudocode as executable code in a Simulator.
384 A Formal Correctness Proof Research Paper written by Boris
387 Additionally, with SVP64 performing element-width over-rides it is the
388 \textit{Scalar
} pseudocode that needs adapting to variable-length
389 (
\textbf{XLEN
}). Maintaining duplicate identical copies in every
390 respect
\textit{except
} for an XLEN as part of the Simple-V Specification
391 is completely pointless and a waste of time: the updates to include
393 of the Scalar Power ISA Specification. This has the added benefit
394 that it makes life much easier for
32-bit implementors, and has an
395 additional benefit of making it possible for the Scalar Power ISA
396 to extend to
128-bit in future (like RV128).
399 \chapter{Binary Coded Decimal pseudocode
}
400 \hypertarget{svux2fpseudocode_bcd
}{}
401 \input{tex_out/pseudocode_bcd.tex
}
402 \chapter{Branch pseudocode
}
403 \hypertarget{openpowerux2fisaux2fbranch
}{}
404 \hypertarget{svux2fpseudocode_branch
}{}
405 \input{tex_out/pseudocode_branch.tex
}
406 \chapter{Fixed Point Compare pseudocode
}
407 \hypertarget{svux2fpseudocode_comparefixed
}{}
408 \input{tex_out/pseudocode_comparefixed.tex
}
409 \chapter{Condition Register pseudocode
}
410 \hypertarget{svux2fpseudocode_condition
}{}
411 \input{tex_out/pseudocode_condition.tex
}
413 \chapter{Fixed Point Arithmetic pseudocode
}
414 \hypertarget{svux2fpseudocode_fixedarith
}{}
415 \input{tex_out/pseudocode_fixedarith.tex
}
416 \chapter{Fixed Point Load pseudocode
}
417 \hypertarget{svux2fpseudocode_fixedload
}{}
418 \input{tex_out/pseudocode_fixedload.tex
}
419 \chapter{Fixed Point Logical pseudocode
}
420 \hypertarget{svux2fpseudocode_fixedlogical
}{}
421 \input{tex_out/pseudocode_fixedlogical.tex
}
422 \chapter{Fixed Point Rotate pseudocode
}
423 \hypertarget{svux2fpseudocode_fixedshift
}{}
424 \input{tex_out/pseudocode_fixedshift.tex
}
426 \chapter{Fixed Point Store pseudocode
}
427 \hypertarget{svux2fpseudocode_fixedstore
}{}
428 \input{tex_out/pseudocode_fixedstore.tex
}
429 \chapter{Fixed Point Trap pseudocode
}
430 \hypertarget{svux2fpseudocode_fixedtrap
}{}
431 \input{tex_out/pseudocode_fixedtrap.tex
}
432 \chapter{Special Purpose Register pseudocode
}
433 \hypertarget{svux2fpseudocode_sprset
}{}
434 \input{tex_out/pseudocode_sprset.tex
}
435 \chapter{String Load/Store pseudocode
}
436 \hypertarget{svux2fpseudocode_stringldst
}{}
437 \input{tex_out/pseudocode_stringldst.tex
}
438 \chapter{System Call pseudocode
}
439 \hypertarget{svux2fpseudocode_system
}{}
440 \input{tex_out/pseudocode_system.tex
}
442 \chapter{Floating Point Load pseudocode
}
443 \hypertarget{svux2fpseudocode_fpload
}{}
444 \input{tex_out/pseudocode_fpload.tex
}
445 \chapter{Floating Point Store pseudocode
}
446 \hypertarget{svux2fpseudocode_fpstore
}{}
447 \input{tex_out/pseudocode_fpstore.tex
}
448 \chapter{Floating Point Move pseudocode
}
449 \hypertarget{svux2fpseudocode_fpmove
}{}
450 \input{tex_out/pseudocode_fpmove.tex
}
451 \chapter{Floating Point Arithmetic pseudocode
}
452 \hypertarget{svux2fpseudocode_fparith
}{}
453 \input{tex_out/pseudocode_fparith.tex
}
454 \chapter{Floating Point Integer Conversion pseudocode
}
455 \hypertarget{svux2fpseudocode_fpcvt
}{}
456 \input{tex_out/pseudocode_fpcvt.tex
}