openpower/simple_v_spec.tex

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 108
 109 % set default figure placement to htbp
 110 \makeatletter\@addtoreset{chapter}{part}\makeatother%
 111 \def\fps@figure{htbp}
 112 \makeatother
 113
 114 % graphics path for primer
 115 \graphicspath{ {svp64-primer/img/} }
 116
 117 \date{}
 118
 119 \begin{document}
 120
 121 \chapter*{Preamble}
 122 \addcontentsline{toc}{chapter}{Preamble} \markboth{INTRODUCTION}{}
 123
 124 \textbf{Last modified date: \today}
 125
 126 This document is an auto-generated version of the Draft SVP64
 127 Specification available at
 128
 129 \begin{verbatim}
 130      https://libre-soc.org/openpower/sv
 131 \end{verbatim}
 132
 133 for which the source code is available at
 134
 135 \begin{verbatim}
 136      https://git.libre-soc.org/?p=libreriscv.git;a=tree;f=openpower;hb=HEAD
 137 \end{verbatim}
 138
 139 This PDF may be created with "make pdf" from the following file:
 140
 141 \begin{verbatim}
 142     https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/Makefile;hb=HEAD
 143 \end{verbatim}
 144
 145 by executing the following commands:
 146
 147 \begin{verbatim}
 148     git clone https://git.libre-soc.org/git/libreriscv.git libresoc
 149     cd libresoc/libresoc/openpower
 150     make pdf
 151 \end{verbatim}
 152
 153 Simple-V Cray-style Vectors have been developed by the Libre-SOC Team,
 154 sponsored by the NLnet Foundation and NGI POINTER under
 155 EU Grants 871528 and 957073.
 156
 157 Simple-V is in DRAFT Status and will be submitted publicly
 158 (non-confidentially) through the OPF ISA WG "External Submissions"
 159 Process. Funding from NLnet, through their Privacy and Enhanced Trust
 160 Programme, requires full transparency.
 161
 162 As this document is under continuous rapid revision please check frequently
 163 at:
 164
 165 \begin{verbatim}
 166     https://ftp.libre-soc.org/simple_v_spec.pdf
 167 \end{verbatim}
 168
 169 \subsection*{Contacts}
 170 For questions, comments, and clarification, please contact the following:
 171 \begin{itemize}
 172     \itemsep -0.3em
 173     \item Libre-SOC ISA Dev Mailing List - libre-soc-isa@lists.libre-soc.org
 174     \item Luke Kenneth Casson Leighton - Libre-SOC team lead and Red
 175     Semiconductor Ltd Director - lkcl@lkcl.net
 176     \item David Calderwood - Red Semiconductor Ltd Director -
 177     djac@calderwoodhan.com
 178     \item Toshaan Bharvani - OpenPOWER Foundation Technical Chair, VanTosh
 179     Director - toshaan@vantosh.com
 180     \item Konstantinos Margaritis -  Engineer and Founder of VectorCamp, writing optimised assembler for a number of SIMD/Vector ISAs  - konstantinos@vectorcamp.gr
 181     \item Dmitry Selyutin - Libre-SOC engineer, working on binutils SVP64 assembler - ghostmansd@gmail.com
 182     \item Jacob Lifshay - Libre-SOC engineer, CPU arch and verification - programmerjake@gmail.com
 183     \item Cesar Strauss - Libre-SOC engineer, CPU arch and verification - cestrauss@gmail.com
 184     \item Andrey Miroshnikov - Libre-SOC engineer, assisting with documentation - andrey@technepisteme.xyz
 185 \end{itemize}
 186
 187 \part{Scalable Vectors Primer}
 188 \input{svp64-primer/acronyms}
 189 \chapter*{Executive Summary}
 190 \include{svp64-primer/summary}
 191 \bibliography{svp64-primer/references}
 192 \bibliographystyle{ieeetr}
 193
 194 \tableofcontents
 195
 196 \part{Scalable Vectors}
 197
 198
 199 \chapter{Fields and Forms}
 200 \hypertarget{svux2ffields}{}
 201 \input{tex_out/fields.tex}
 202 \chapter{Scalable Vectors for the Power ISA}
 203 \hypertarget{svux2fscalvecpowisa}{}
 204 \hypertarget{SVux7csv}{}
 205 \input{tex_out/sv.tex}
 206 \chapter{Other Vector ISAs}\hypertarget{svux2fvector_isa_comparison}{}
 207 \input{tex_out/vector_isas.tex}
 208 \chapter{Overview}\hypertarget{svux2foverview}{}
 209 \input{tex_out/overview.tex}
 210 \chapter{Compliancy Levels}\hypertarget{svux2fcompliancy_levels}{}
 211 \input{tex_out/compliancy_levels.tex}
 212 \chapter{SVP64}\hypertarget{svux2fsvp64}{}
 213 \input{tex_out/svp64.tex}
 214 \chapter{SPRs}\hypertarget{svux2fsprs}{}
 215 \input{tex_out/sprs.tex}
 216 \chapter{Arithmetic Mode}\hypertarget{svux2fnormal}{}
 217 \input{tex_out/normal.tex}
 218 \chapter{Load/Store Mode}\hypertarget{svux2fldst}{}
 219 \input{tex_out/ldst.tex}
 220 \chapter{Condition Register Fields Mode}\hypertarget{svux2fcr_ops}{}
 221 \input{tex_out/cr_ops.tex}
 222 \chapter{Branch Mode}\hypertarget{svux2fbranches}{}
 223 \input{tex_out/branches.tex}
 224 \chapter{setvl instruction}\hypertarget{svux2fsetvl}{}
 225 \input{tex_out/setvl.tex}
 226 \chapter{svstep instruction}\hypertarget{svux2fsvstep}{}
 227 \input{tex_out/svstep.tex}
 228 \chapter{REMAP subsystem}\hypertarget{svux2fremap}{}
 229 \input{tex_out/remap.tex}
 230 \chapter{Swizzle Move}\hypertarget{svux2fmv.swizzle}{}
 231 \input{tex_out/mv_swizzle.tex}
 232 \chapter{Pack / Unpack}\hypertarget{svux2fmv.vec}{}
 233 \input{tex_out/mv_vec.tex}
 234
 235 \begin{appendices}
 236 \chapter{SVP64 Appendix}\hypertarget{svp64ux2fappendix}{}
 237 \hypertarget{svux2fsvp64ux2fappendix}{}
 238 \input{tex_out/svp64_appendix.tex}
 239 \chapter{SVP64 Quirks}\hypertarget{svux2fsvp64_quirks}{}
 240 \input{tex_out/svp64_quirks.tex}
 241 \chapter{REMAP algorithms}\hypertarget{svux2fremapux2fappendix}{}
 242 \input{tex_out/remap_appendix.tex}
 243 \chapter{Simple-V pseudocode}\hypertarget{svux2fpseudocode_simplev}{}
 244 \input{tex_out/pseudocode_simplev.tex}
 245
 246 \chapter{SVP64 Augmentation Table}\hypertarget{opcode_regs_deduped}{}
 247 \begin{landscape}
 248 {
 249 \fontsize{7}{9}\selectfont
 250 \input{tex_out/opcode_regs_deduped.tex}
 251 }
 252 \end{landscape}
 253
 254 \chapter{Comparison Table}\hypertarget{svux2fcomparison_table}{}
 255 \begin{landscape}
 256 {
 257 \fontsize{7}{9}\selectfont
 258 \input{tex_out/comparison_table.tex}
 259 }
 260 \end{landscape}
 261
 262 \end{appendices}
 263
 264 \part{Scalar Instructions}
 265
 266 \chapter{SV Vector ops}\hypertarget{svux2fvector_ops}{}
 267 \input{tex_out/vector_ops.tex}
 268 \chapter{CR Weird ops}\hypertarget{svux2fcr_int_predication}{}
 269 \hypertarget{cr_int_predication}{}
 270 \input{tex_out/cr_int_predication.tex}
 271 \chapter{Bitmanip ops}\hypertarget{svux2fbitmanip}{}
 272 \input{tex_out/bitmanip.tex}
 273 \chapter{FP/Int Conversion ops}\hypertarget{svux2fint_fp_mv}{}
 274 \input{tex_out/int_fp_mv.tex}
 275 \chapter{FP Class ops}\hypertarget{svux2ffclass}{}
 276 \input{tex_out/fclass.tex}
 277 \chapter{Audio and Video Opcodes}\hypertarget{svux2fav_opcodes}{}
 278 \hypertarget{av_opcodes}{}
 279 \input{tex_out/av_opcodes.tex}
 280 \chapter{Big Integer}\hypertarget{svux2fbiginteger}{}
 281 \input{tex_out/big_integer.tex}
 282 \chapter{Transcendentals}\hypertarget{transcendentals}{}
 283 \input{tex_out/transcendentals.tex}
 284 \chapter{Acquire/Release Atomic Memory}\hypertarget{atomics}{}
 285 \input{tex_out/atomics.tex}
 286
 287 \begin{appendices}
 288 \chapter{Big Integer Analysis}\hypertarget{svux2fbigintegerux2fanalysis}{}
 289 \input{tex_out/big_integer_analysis.tex}
 290 \chapter{Bitmanip pseudocode}\hypertarget{svux2fpseudocode_bitmanip}{}
 291 \input{tex_out/pseudocode_bitmanip.tex}
 292 \chapter{Floating Point pseudocode}\hypertarget{isaux2fsvfparith}{}
 293 \input{tex_out/pseudocode_svfparith.tex}
 294 \chapter{Fixed Point pseudocode}
 295 \hypertarget{isaux2fsvfixedarith}{}
 296 \input{tex_out/pseudocode_svfixedarith.tex}
 297 \end{appendices}
 298
 299 \part{Scalar Power ISA pseudocode}
 300 \backmatter % temporary fix for too many appenfices
 301 %\setcounter{chapter}{0}
 302 %\renewcommand{\thechapter}{\Alph{chapter}}
 303
 304 \chapter*{Preamble}
 305 \addcontentsline{toc}{chapter}{Preamble} \markboth{INTRODUCTION}{}
 306
 307 This section contains updated pseudocode from the Power ISA Specification
 308 v3.0B to be executable.  Several bugfixes in Power ISA v3.0B have been
 309 found and reported as a direct result due to actually running the
 310 pseudocode as executable code in a Simulator.
 311 A Formal Correctness Proof Research Paper written by Boris
 312 Shingarov.
 313
 314 Additionally, with SVP64 performing element-width over-rides it is the
 315 \textit{Scalar} pseudocode that needs adapting to variable-length
 316 (\textbf{XLEN}).  Maintaining duplicate identical copies in every
 317 respect \textit{except} for an XLEN as part of the Simple-V Specification
 318 is completely pointless and a waste of time: the updates to include
 319 XLEN need to be part
 320 of the Scalar Power ISA Specification.  This has the added benefit
 321 that it makes life much easier for 32-bit implementors, and has an
 322 additional benefit of making it possible for the Scalar Power ISA
 323 to extend to 128-bit in future (like RV128).
 324
 325 \begin{appendices}
 326 \chapter{Binary Coded Decimal pseudocode}
 327 \hypertarget{svux2fpseudocode_bcd}{}
 328 \input{tex_out/pseudocode_bcd.tex}
 329 \chapter{Branch pseudocode}
 330 \hypertarget{openpowerux2fisaux2fbranch}{}
 331 \hypertarget{svux2fpseudocode_branch}{}
 332 \input{tex_out/pseudocode_branch.tex}
 333 \chapter{Fixed Point Compare pseudocode}
 334 \hypertarget{svux2fpseudocode_comparefixed}{}
 335 \input{tex_out/pseudocode_comparefixed.tex}
 336 \chapter{Condition Register pseudocode}
 337 \hypertarget{svux2fpseudocode_condition}{}
 338 \input{tex_out/pseudocode_condition.tex}
 339
 340 \chapter{Fixed Point Arithmetic pseudocode}
 341 \hypertarget{svux2fpseudocode_fixedarith}{}
 342 \input{tex_out/pseudocode_fixedarith.tex}
 343 \chapter{Fixed Point Load pseudocode}
 344 \hypertarget{svux2fpseudocode_fixedload}{}
 345 \input{tex_out/pseudocode_fixedload.tex}
 346 \chapter{Fixed Point Logical pseudocode}
 347 \hypertarget{svux2fpseudocode_fixedlogical}{}
 348 \input{tex_out/pseudocode_fixedlogical.tex}
 349 \chapter{Fixed Point Rotate pseudocode}
 350 \hypertarget{svux2fpseudocode_fixedshift}{}
 351 \input{tex_out/pseudocode_fixedshift.tex}
 352
 353 \chapter{Fixed Point Store pseudocode}
 354 \hypertarget{svux2fpseudocode_fixedstore}{}
 355 \input{tex_out/pseudocode_fixedstore.tex}
 356 \chapter{Fixed Point Trap pseudocode}
 357 \hypertarget{svux2fpseudocode_fixedtrap}{}
 358 \input{tex_out/pseudocode_fixedtrap.tex}
 359 \chapter{Special Purpose Register pseudocode}
 360 \hypertarget{svux2fpseudocode_sprset}{}
 361 \input{tex_out/pseudocode_sprset.tex}
 362 \chapter{String Load/Store pseudocode}
 363 \hypertarget{svux2fpseudocode_stringldst}{}
 364 \input{tex_out/pseudocode_stringldst.tex}
 365 \chapter{System Call pseudocode}
 366 \hypertarget{svux2fpseudocode_system}{}
 367 \input{tex_out/pseudocode_system.tex}
 368
 369 \chapter{Floating Point Load pseudocode}
 370 \hypertarget{svux2fpseudocode_fpload}{}
 371 \input{tex_out/pseudocode_fpload.tex}
 372 \chapter{Floating Point Store pseudocode}
 373 \hypertarget{svux2fpseudocode_fpstore}{}
 374 \input{tex_out/pseudocode_fpstore.tex}
 375 \chapter{Floating Point Move pseudocode}
 376 \hypertarget{svux2fpseudocode_fpmove}{}
 377 \input{tex_out/pseudocode_fpmove.tex}
 378 \chapter{Floating Point Arithmetic pseudocode}
 379 \hypertarget{svux2fpseudocode_fparith}{}
 380 \input{tex_out/pseudocode_fparith.tex}
 381 \chapter{Floating Point Integer Conversion pseudocode}
 382 \hypertarget{svux2fpseudocode_fpcvt}{}
 383 \input{tex_out/pseudocode_fpcvt.tex}
 384
 385 \end{appendices}
 386
 387
 388
 389
 390 \end{document}