openpower/simple_v_spec.tex

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 107 \fi
 108
 109 % set default figure placement to htbp
 110 \makeatletter\@addtoreset{chapter}{part}\makeatother%
 111 \def\fps@figure{htbp}
 112 \makeatother
 113
 114 % graphics path for primer
 115 \graphicspath{ {svp64-primer/img/} }
 116
 117 \date{}
 118
 119 \begin{document}
 120
 121 \chapter*{Preamble}
 122 \addcontentsline{toc}{chapter}{Preamble} \markboth{INTRODUCTION}{}
 123
 124 \textbf{Last modified date: \today}
 125
 126 This document is an auto-generated version of the Draft SVP64
 127 Specification available at
 128
 129 \begin{verbatim}
 130      https://libre-soc.org/openpower/sv
 131 \end{verbatim}
 132
 133 for which the source code is available at
 134
 135 \begin{verbatim}
 136      https://git.libre-soc.org/?p=libreriscv.git;a=tree;f=openpower;hb=HEAD
 137 \end{verbatim}
 138
 139 This PDF may be created with "make pdf" from the following file:
 140
 141 \begin{verbatim}
 142     https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/Makefile;hb=HEAD
 143 \end{verbatim}
 144
 145 by executing the following commands:
 146
 147 \begin{verbatim}
 148     git clone https://git.libre-soc.org/git/libreriscv.git libresoc
 149     cd libresoc/libresoc/openpower
 150     make pdf
 151 \end{verbatim}
 152
 153 Simple-V Cray-style Vectors have been developed by the Libre-SOC Team,
 154 sponsored by the NLnet Foundation and NGI POINTER under
 155 EU Grants 871528 and 957073.
 156
 157 Simple-V is in DRAFT Status and will be submitted publicly
 158 (non-confidentially) through the OPF ISA WG "External Submissions"
 159 Process. Funding from NLnet, through their Privacy and Enhanced Trust
 160 Programme, requires full transparency.
 161
 162 As this document is under continuous rapid revision please check frequently
 163 at:
 164
 165 \begin{verbatim}
 166     https://ftp.libre-soc.org/simple_v_spec.pdf
 167 \end{verbatim}
 168
 169
 170 \part{Scalable Vectors Primer}
 171 \input{svp64-primer/acronyms}
 172 \chapter*{Executive Summary}
 173 \include{svp64-primer/summary}
 174 \bibliography{svp64-primer/references}
 175 \bibliographystyle{ieeetr}
 176
 177 \tableofcontents
 178
 179 \part{Scalable Vectors}
 180
 181
 182 \chapter{Fields and Forms}
 183 \hypertarget{svux2ffields}{}
 184 \input{tex_out/fields.tex}
 185 \chapter{Scalable Vectors for the Power ISA}
 186 \hypertarget{svux2fscalvecpowisa}{}
 187 \hypertarget{SVux7csv}{}
 188 \input{tex_out/sv.tex}
 189 \chapter{Other Vector ISAs}\hypertarget{svux2fvector_isa_comparison}{}
 190 \input{tex_out/vector_isas.tex}
 191 \chapter{Overview}\hypertarget{svux2foverview}{}
 192 \input{tex_out/overview.tex}
 193 \chapter{Compliancy Levels}\hypertarget{svux2fcompliancy_levels}{}
 194 \input{tex_out/compliancy_levels.tex}
 195 \chapter{SVP64}\hypertarget{svux2fsvp64}{}
 196 \input{tex_out/svp64.tex}
 197 \chapter{SPRs}\hypertarget{svux2fsprs}{}
 198 \input{tex_out/sprs.tex}
 199 \chapter{Arithmetic Mode}\hypertarget{svux2fnormal}{}
 200 \input{tex_out/normal.tex}
 201 \chapter{Load/Store Mode}\hypertarget{svux2fldst}{}
 202 \input{tex_out/ldst.tex}
 203 \chapter{Condition Register Fields Mode}\hypertarget{svux2fcr_ops}{}
 204 \input{tex_out/cr_ops.tex}
 205 \chapter{Branch Mode}\hypertarget{svux2fbranches}{}
 206 \input{tex_out/branches.tex}
 207 \chapter{setvl instruction}\hypertarget{svux2fsetvl}{}
 208 \input{tex_out/setvl.tex}
 209 \chapter{svstep instruction}\hypertarget{svux2fsvstep}{}
 210 \input{tex_out/svstep.tex}
 211 \chapter{REMAP subsystem}\hypertarget{svux2fremap}{}
 212 \input{tex_out/remap.tex}
 213 \chapter{Swizzle Move}\hypertarget{svux2fmv.swizzle}{}
 214 \input{tex_out/mv_swizzle.tex}
 215 \chapter{Pack / Unpack}\hypertarget{svux2fmv.vec}{}
 216 \input{tex_out/mv_vec.tex}
 217
 218 \begin{appendices}
 219 \chapter{SVP64 Appendix}\hypertarget{svp64ux2fappendix}{}
 220 \hypertarget{svux2fsvp64ux2fappendix}{}
 221 \input{tex_out/svp64_appendix.tex}
 222 \chapter{SVP64 Quirks}\hypertarget{svux2fsvp64_quirks}{}
 223 \input{tex_out/svp64_quirks.tex}
 224 \chapter{REMAP algorithms}\hypertarget{svux2fremapux2fappendix}{}
 225 \input{tex_out/remap_appendix.tex}
 226 \chapter{Simple-V pseudocode}\hypertarget{svux2fpseudocode_simplev}{}
 227 \input{tex_out/pseudocode_simplev.tex}
 228
 229 \chapter{SVP64 Augmentation Table}\hypertarget{opcode_regs_deduped}{}
 230 \begin{landscape}
 231 {
 232 \fontsize{7}{9}\selectfont
 233 \input{tex_out/opcode_regs_deduped.tex}
 234 }
 235 \end{landscape}
 236
 237 \chapter{Comparison Table}\hypertarget{svux2fcomparison_table}{}
 238 \begin{landscape}
 239 {
 240 \fontsize{7}{9}\selectfont
 241 \input{tex_out/comparison_table.tex}
 242 }
 243 \end{landscape}
 244
 245 \end{appendices}
 246
 247 \part{Scalar Instructions}
 248
 249 \chapter{SV Vector ops}\hypertarget{svux2fvector_ops}{}
 250 \input{tex_out/vector_ops.tex}
 251 \chapter{CR Weird ops}\hypertarget{svux2fcr_int_predication}{}
 252 \hypertarget{cr_int_predication}{}
 253 \input{tex_out/cr_int_predication.tex}
 254 \chapter{Bitmanip ops}\hypertarget{svux2fbitmanip}{}
 255 \input{tex_out/bitmanip.tex}
 256 \chapter{FP/Int Conversion ops}\hypertarget{svux2fint_fp_mv}{}
 257 \input{tex_out/int_fp_mv.tex}
 258 \chapter{FP Class ops}\hypertarget{svux2ffclass}{}
 259 \input{tex_out/fclass.tex}
 260 \chapter{Audio and Video Opcodes}\hypertarget{svux2fav_opcodes}{}
 261 \hypertarget{av_opcodes}{}
 262 \input{tex_out/av_opcodes.tex}
 263 \chapter{Big Integer}\hypertarget{svux2fbiginteger}{}
 264 \input{tex_out/big_integer.tex}
 265 \chapter{Transcendentals}\hypertarget{transcendentals}{}
 266 \input{tex_out/transcendentals.tex}
 267 \chapter{Acquire/Release Atomic Memory}\hypertarget{atomics}{}
 268 \input{tex_out/atomics.tex}
 269
 270 \begin{appendices}
 271 \chapter{Big Integer Analysis}\hypertarget{svux2fbigintegerux2fanalysis}{}
 272 \input{tex_out/big_integer_analysis.tex}
 273 \chapter{Bitmanip pseudocode}\hypertarget{svux2fpseudocode_bitmanip}{}
 274 \input{tex_out/pseudocode_bitmanip.tex}
 275 \chapter{Floating Point pseudocode}\hypertarget{isaux2fsvfparith}{}
 276 \input{tex_out/pseudocode_svfparith.tex}
 277 \chapter{Fixed Point pseudocode}
 278 \hypertarget{isaux2fsvfixedarith}{}
 279 \input{tex_out/pseudocode_svfixedarith.tex}
 280 \end{appendices}
 281
 282 \part{Scalar Power ISA pseudocode}
 283 \backmatter % temporary fix for too many appenfices
 284 %\setcounter{chapter}{0}
 285 %\renewcommand{\thechapter}{\Alph{chapter}}
 286
 287 \chapter*{Preamble}
 288 \addcontentsline{toc}{chapter}{Preamble} \markboth{INTRODUCTION}{}
 289
 290 This section contains updated pseudocode from the Power ISA Specification
 291 v3.0B to be executable.  Several bugfixes in Power ISA v3.0B have been
 292 found and reported as a direct result due to actually running the
 293 pseudocode as executable code in a Simulator.
 294 A Formal Correctness Proof Research Paper written by Boris
 295 Shingarov.
 296
 297 Additionally, with SVP64 performing element-width over-rides it is the
 298 \textit{Scalar} pseudocode that needs adapting to variable-length
 299 (\textbf{XLEN}).  Maintaining duplicate identical copies in every
 300 respect \textit{except} for an XLEN as part of the Simple-V Specification
 301 is completely pointless and a waste of time: the updates to include
 302 XLEN need to be part
 303 of the Scalar Power ISA Specification.  This has the added benefit
 304 that it makes life much easier for 32-bit implementors, and has an
 305 additional benefit of making it possible for the Scalar Power ISA
 306 to extend to 128-bit in future (like RV128).
 307
 308 \begin{appendices}
 309 \chapter{Binary Coded Decimal pseudocode}
 310 \hypertarget{svux2fpseudocode_bcd}{}
 311 \input{tex_out/pseudocode_bcd.tex}
 312 \chapter{Branch pseudocode}
 313 \hypertarget{openpowerux2fisaux2fbranch}{}
 314 \hypertarget{svux2fpseudocode_branch}{}
 315 \input{tex_out/pseudocode_branch.tex}
 316 \chapter{Fixed Point Compare pseudocode}
 317 \hypertarget{svux2fpseudocode_comparefixed}{}
 318 \input{tex_out/pseudocode_comparefixed.tex}
 319 \chapter{Condition Register pseudocode}
 320 \hypertarget{svux2fpseudocode_condition}{}
 321 \input{tex_out/pseudocode_condition.tex}
 322
 323 \chapter{Fixed Point Arithmetic pseudocode}
 324 \hypertarget{svux2fpseudocode_fixedarith}{}
 325 \input{tex_out/pseudocode_fixedarith.tex}
 326 \chapter{Fixed Point Load pseudocode}
 327 \hypertarget{svux2fpseudocode_fixedload}{}
 328 \input{tex_out/pseudocode_fixedload.tex}
 329 \chapter{Fixed Point Logical pseudocode}
 330 \hypertarget{svux2fpseudocode_fixedlogical}{}
 331 \input{tex_out/pseudocode_fixedlogical.tex}
 332 \chapter{Fixed Point Rotate pseudocode}
 333 \hypertarget{svux2fpseudocode_fixedshift}{}
 334 \input{tex_out/pseudocode_fixedshift.tex}
 335
 336 \chapter{Fixed Point Store pseudocode}
 337 \hypertarget{svux2fpseudocode_fixedstore}{}
 338 \input{tex_out/pseudocode_fixedstore.tex}
 339 \chapter{Fixed Point Trap pseudocode}
 340 \hypertarget{svux2fpseudocode_fixedtrap}{}
 341 \input{tex_out/pseudocode_fixedtrap.tex}
 342 \chapter{Special Purpose Register pseudocode}
 343 \hypertarget{svux2fpseudocode_sprset}{}
 344 \input{tex_out/pseudocode_sprset.tex}
 345 \chapter{String Load/Store pseudocode}
 346 \hypertarget{svux2fpseudocode_stringldst}{}
 347 \input{tex_out/pseudocode_stringldst.tex}
 348 \chapter{System Call pseudocode}
 349 \hypertarget{svux2fpseudocode_system}{}
 350 \input{tex_out/pseudocode_system.tex}
 351
 352 \chapter{Floating Point Load pseudocode}
 353 \hypertarget{svux2fpseudocode_fpload}{}
 354 \input{tex_out/pseudocode_fpload.tex}
 355 \chapter{Floating Point Store pseudocode}
 356 \hypertarget{svux2fpseudocode_fpstore}{}
 357 \input{tex_out/pseudocode_fpstore.tex}
 358 \chapter{Floating Point Move pseudocode}
 359 \hypertarget{svux2fpseudocode_fpmove}{}
 360 \input{tex_out/pseudocode_fpmove.tex}
 361 \chapter{Floating Point Arithmetic pseudocode}
 362 \hypertarget{svux2fpseudocode_fparith}{}
 363 \input{tex_out/pseudocode_fparith.tex}
 364 \chapter{Floating Point Integer Conversion pseudocode}
 365 \hypertarget{svux2fpseudocode_fpcvt}{}
 366 \input{tex_out/pseudocode_fpcvt.tex}
 367
 368 \end{appendices}
 369
 370
 371
 372
 373 \end{document}