openpower/simple_v_spec.tex

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 105 \makeatletter\@addtoreset{chapter}{part}\makeatother%
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 107 \makeatother
 108
 109
 110 \date{}
 111
 112 \begin{document}
 113
 114 \chapter*{Preamble}
 115 \addcontentsline{toc}{chapter}{Preamble} \markboth{INTRODUCTION}{}
 116
 117 This document is an auto-generated version of the Draft SVP64
 118 Specification available at
 119
 120 \begin{verbatim}
 121      https://libre-soc.org/openpower/sv
 122 \end{verbatim}
 123
 124 for which the source code is available at
 125
 126 \begin{verbatim}
 127      https://git.libre-soc.org/?p=libreriscv.git;a=tree;f=openpower;hb=HEAD
 128 \end{verbatim}
 129
 130 This PDF may be created with "make pdf" from the following file:
 131
 132 \begin{verbatim}
 133     https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/Makefile;hb=HEAD
 134 \end{verbatim}
 135
 136 by executing the following commands:
 137
 138 \begin{verbatim}
 139     git clone https://git.libre-soc.org/git/libreriscv.git libresoc
 140     cd libresoc/libresoc/openpower
 141     make pdf
 142 \end{verbatim}
 143
 144 Simple-V Cray-style Vectors have been developed by the Libre-SOC Team,
 145 sponsored by the NLnet Foundation and NGI POINTER under
 146 EU Grants 871528 and 957073.
 147
 148 Simple-V is in DRAFT Status and will be submitted publicly
 149 (non-confidentially) through the OPF ISA WG "External Submissions"
 150 Process. Funding from NLnet, through their Privacy and Enhanced Trust
 151 Programme, requires full transparency.
 152
 153 \tableofcontents
 154
 155 \part{Scalable Vectors}
 156
 157 \chapter{Fields and Forms}
 158 \hypertarget{svux2ffields}{}
 159 \input{tex_out/fields.tex}
 160 \chapter{Scalable Vectors for the Power ISA}
 161 \hypertarget{svux2fscalvecpowisa}{}
 162 \hypertarget{SVux7csv}{}
 163 \input{tex_out/sv.tex}
 164 \chapter{Other Vector ISAs}\hypertarget{svux2fvector_isa_comparison}{}
 165 \input{tex_out/vector_isas.tex}
 166 \chapter{Comparison Table}\hypertarget{svux2fcomparison_table}{}
 167 \input{tex_out/comparison_table.tex}
 168 \chapter{Overview}\hypertarget{svux2foverview}{}
 169 \input{tex_out/overview.tex}
 170 \chapter{Compliancy Levels}\hypertarget{svux2fcompliancy_levels}{}
 171 \input{tex_out/compliancy_levels.tex}
 172 \chapter{SVP64}\hypertarget{svux2fsvp64}{}
 173 \input{tex_out/svp64.tex}
 174 \chapter{SPRs}\hypertarget{svux2fsprs}{}
 175 \input{tex_out/sprs.tex}
 176 \chapter{Arithmetic Mode}\hypertarget{svux2fnormal}{}
 177 \input{tex_out/normal.tex}
 178 \chapter{Load/Store Mode}\hypertarget{svux2fldst}{}
 179 \input{tex_out/ldst.tex}
 180 \chapter{Condition Register Fields Mode}\hypertarget{svux2fcr_ops}{}
 181 \input{tex_out/cr_ops.tex}
 182 \chapter{Branch Mode}\hypertarget{svux2fbranches}{}
 183 \input{tex_out/branches.tex}
 184 \chapter{setvl instruction}\hypertarget{svux2fsetvl}{}
 185 \input{tex_out/setvl.tex}
 186 \chapter{svstep instruction}\hypertarget{svux2fsvstep}{}
 187 \input{tex_out/svstep.tex}
 188 \chapter{REMAP subsystem}\hypertarget{svux2fremap}{}
 189 \input{tex_out/remap.tex}
 190 \chapter{Swizzle Move}\hypertarget{svux2fmv.swizzle}{}
 191 \input{tex_out/mv_swizzle.tex}
 192 \chapter{Pack / Unpack}\hypertarget{svux2fmv.vec}{}
 193 \input{tex_out/mv_vec.tex}
 194
 195 \begin{appendices}
 196 \chapter{SVP64 Appendix}\hypertarget{svp64ux2fappendix}{}
 197 \hypertarget{svux2fsvp64ux2fappendix}{}
 198 \input{tex_out/svp64_appendix.tex}
 199 \chapter{SVP64 Quirks}\hypertarget{svux2fsvp64_quirks}{}
 200 \input{tex_out/svp64_quirks.tex}
 201 \chapter{REMAP algorithms}\hypertarget{svux2fremapux2fappendix}{}
 202 \input{tex_out/remap_appendix.tex}
 203 \chapter{Simple-V pseudocode}\hypertarget{svux2fpseudocode_simplev}{}
 204 \input{tex_out/pseudocode_simplev.tex}
 205 \chapter{SVP64 Augmentation Table}\hypertarget{opcode_regs_deduped}{}
 206 \begin{landscape}
 207 {
 208 \fontsize{7}{9}\selectfont
 209 \input{tex_out/opcode_regs_deduped.tex}
 210 }
 211 \end{landscape}
 212 \end{appendices}
 213
 214 \part{Scalar Instructions}
 215
 216 \chapter{SV Vector ops}\hypertarget{svux2fvector_ops}{}
 217 \input{tex_out/vector_ops.tex}
 218 \chapter{CR Weird ops}\hypertarget{svux2fcr_int_predication}{}
 219 \hypertarget{cr_int_predication}{}
 220 \input{tex_out/cr_int_predication.tex}
 221 \chapter{Bitmanip ops}\hypertarget{svux2fbitmanip}{}
 222 \input{tex_out/bitmanip.tex}
 223 \chapter{FP/Int Conversion ops}\hypertarget{svux2fint_fp_mv}{}
 224 \input{tex_out/int_fp_mv.tex}
 225 \chapter{FP Class ops}\hypertarget{svux2ffclass}{}
 226 \input{tex_out/fclass.tex}
 227 \chapter{Audio and Video Opcodes}\hypertarget{svux2fav_opcodes}{}
 228 \hypertarget{av_opcodes}{}
 229 \input{tex_out/av_opcodes.tex}
 230 \chapter{Big Integer}\hypertarget{svux2fbiginteger}{}
 231 \input{tex_out/big_integer.tex}
 232 \chapter{Transcendentals}\hypertarget{transcendentals}{}
 233 \input{tex_out/transcendentals.tex}
 234 \chapter{Acquire/Release Atomic Memory}\hypertarget{atomics}{}
 235 \input{tex_out/atomics.tex}
 236
 237 \begin{appendices}
 238 \chapter{Big Integer Analysis}\hypertarget{svux2fbigintegerux2fanalysis}{}
 239 \input{tex_out/big_integer_analysis.tex}
 240 \chapter{Bitmanip pseudocode}\hypertarget{svux2fpseudocode_bitmanip}{}
 241 \input{tex_out/pseudocode_bitmanip.tex}
 242 \chapter{Floating Point pseudocode}\hypertarget{isaux2fsvfparith}{}
 243 \input{tex_out/pseudocode_svfparith.tex}
 244 \chapter{Fixed Point pseudocode}
 245 \hypertarget{isaux2fsvfixedarith}{}
 246 \input{tex_out/pseudocode_svfixedarith.tex}
 247 \end{appendices}
 248
 249 \part{Scalar Power ISA pseudocode}
 250 \backmatter % temporary fix for too many appenfices
 251 %\setcounter{chapter}{0}
 252 %\renewcommand{\thechapter}{\Alph{chapter}}
 253
 254 \chapter*{Preamble}
 255 \addcontentsline{toc}{chapter}{Preamble} \markboth{INTRODUCTION}{}
 256
 257 This section contains updated pseudocode from the Power ISA Specification
 258 v3.0B to be executable.  Several bugfixes in Power ISA v3.0B have been
 259 found and reported as a direct result due to actually running the
 260 pseudocode as executable code in a Simulator.
 261 A Formal Correctness Proof Research Paper written by Boris
 262 Shingarov.
 263
 264 Additionally, with SVP64 performing element-width over-rides it is the
 265 \textit{Scalar} pseudocode that needs adapting to variable-length
 266 (\textbf{XLEN}).  Maintaining duplicate identical copies in every
 267 respect \textit{except} for an XLEN as part of the Simple-V Specification
 268 is completely pointless and a waste of time: the updates to include
 269 XLEN need to be part
 270 of the Scalar Power ISA Specification.  This has the added benefit
 271 that it makes life much easier for 32-bit implementors, and has an
 272 additional benefit of making it possible for the Scalar Power ISA
 273 to extend to 128-bit in future (like RV128).
 274
 275 \begin{appendices}
 276 \chapter{Binary Coded Decimal pseudocode}
 277 \hypertarget{svux2fpseudocode_bcd}{}
 278 \input{tex_out/pseudocode_bcd.tex}
 279 \chapter{Branch pseudocode}
 280 \hypertarget{openpowerux2fisaux2fbranch}{}
 281 \hypertarget{svux2fpseudocode_branch}{}
 282 \input{tex_out/pseudocode_branch.tex}
 283 \chapter{Fixed Point Compare pseudocode}
 284 \hypertarget{svux2fpseudocode_comparefixed}{}
 285 \input{tex_out/pseudocode_comparefixed.tex}
 286 \chapter{Condition Register pseudocode}
 287 \hypertarget{svux2fpseudocode_condition}{}
 288 \input{tex_out/pseudocode_condition.tex}
 289
 290 \chapter{Fixed Point Arithmetic pseudocode}
 291 \hypertarget{svux2fpseudocode_fixedarith}{}
 292 \input{tex_out/pseudocode_fixedarith.tex}
 293 \chapter{Fixed Point Load pseudocode}
 294 \hypertarget{svux2fpseudocode_fixedload}{}
 295 \input{tex_out/pseudocode_fixedload.tex}
 296 \chapter{Fixed Point Logical pseudocode}
 297 \hypertarget{svux2fpseudocode_fixedlogical}{}
 298 \input{tex_out/pseudocode_fixedlogical.tex}
 299 \chapter{Fixed Point Rotate pseudocode}
 300 \hypertarget{svux2fpseudocode_fixedshift}{}
 301 \input{tex_out/pseudocode_fixedshift.tex}
 302
 303 \chapter{Fixed Point Store pseudocode}
 304 \hypertarget{svux2fpseudocode_fixedstore}{}
 305 \input{tex_out/pseudocode_fixedstore.tex}
 306 \chapter{Fixed Point Trap pseudocode}
 307 \hypertarget{svux2fpseudocode_fixedtrap}{}
 308 \input{tex_out/pseudocode_fixedtrap.tex}
 309 \chapter{Special Purpose Register pseudocode}
 310 \hypertarget{svux2fpseudocode_sprset}{}
 311 \input{tex_out/pseudocode_sprset.tex}
 312 \chapter{String Load/Store pseudocode}
 313 \hypertarget{svux2fpseudocode_stringldst}{}
 314 \input{tex_out/pseudocode_stringldst.tex}
 315 \chapter{System Call pseudocode}
 316 \hypertarget{svux2fpseudocode_system}{}
 317 \input{tex_out/pseudocode_system.tex}
 318
 319 \chapter{Floating Point Load pseudocode}
 320 \hypertarget{svux2fpseudocode_fpload}{}
 321 \input{tex_out/pseudocode_fpload.tex}
 322 \chapter{Floating Point Store pseudocode}
 323 \hypertarget{svux2fpseudocode_fpstore}{}
 324 \input{tex_out/pseudocode_fpstore.tex}
 325 \chapter{Floating Point Move pseudocode}
 326 \hypertarget{svux2fpseudocode_fpmove}{}
 327 \input{tex_out/pseudocode_fpmove.tex}
 328 \chapter{Floating Point Arithmetic pseudocode}
 329 \hypertarget{svux2fpseudocode_fparith}{}
 330 \input{tex_out/pseudocode_fparith.tex}
 331 \chapter{Floating Point Integer Conversion pseudocode}
 332 \hypertarget{svux2fpseudocode_fpcvt}{}
 333 \input{tex_out/pseudocode_fpcvt.tex}
 334
 335 \end{appendices}
 336
 337
 338
 339
 340 \end{document}