openpower/simple_v_spec.tex

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 111 % set default figure placement to htbp
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 113 \def\fps@figure{htbp}
 114 \makeatother
 115
 116 % graphics path for primer
 117 \graphicspath{ {svp64-primer/img/} }
 118
 119 \date{}
 120
 121 \begin{document}
 122
 123 \chapter*{Preamble}
 124 \addcontentsline{toc}{chapter}{Preamble} \markboth{INTRODUCTION}{}
 125
 126 \textbf{Last modified date: \today}
 127
 128 This document is an auto-generated version of the Draft SVP64
 129 Specification available at
 130
 131 \begin{verbatim}
 132      https://libre-soc.org/openpower/sv
 133 \end{verbatim}
 134
 135 for which the source code is available at
 136
 137 \begin{verbatim}
 138      https://git.libre-soc.org/?p=libreriscv.git;a=tree;f=openpower;hb=HEAD
 139 \end{verbatim}
 140
 141 This PDF may be created with "make pdf" from the following file:
 142
 143 \begin{verbatim}
 144     https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/Makefile;hb=HEAD
 145 \end{verbatim}
 146
 147 by executing the following commands:
 148
 149 \begin{verbatim}
 150     git clone https://git.libre-soc.org/git/libreriscv.git libresoc
 151     cd libresoc/libresoc/openpower
 152     make pdf
 153 \end{verbatim}
 154
 155 Simple-V Cray-style Vectors have been developed by the Libre-SOC Team,
 156 sponsored by the NLnet Foundation and NGI POINTER under
 157 EU Grants 871528 and 957073.
 158
 159 Simple-V is in DRAFT Status and will be submitted publicly
 160 (non-confidentially) through the OPF ISA WG "External Submissions"
 161 Process. Funding from NLnet, through their Privacy and Enhanced Trust
 162 Programme, requires full transparency.
 163
 164 As this document is under continuous rapid revision please check frequently
 165 at:
 166
 167 \begin{verbatim}
 168     https://ftp.libre-soc.org/simple_v_spec.pdf
 169 \end{verbatim}
 170
 171 \subsection*{Contacts}
 172 For questions, comments, and clarification, please contact the following:
 173 \begin{itemize}
 174     \itemsep -0.3em
 175     \item Libre-SOC ISA Dev Mailing List - libre-soc-isa@lists.libre-soc.org
 176     \item Luke Kenneth Casson Leighton - Libre-SOC team lead and Red
 177     Semiconductor Ltd Director - lkcl@lkcl.net
 178     \item David Calderwood - Red Semiconductor Ltd Director -
 179     djac@calderwoodhan.com
 180     \item Toshaan Bharvani - OpenPOWER Foundation Technical Chair, VanTosh
 181     Director - toshaan@vantosh.com
 182     \item Konstantinos Margaritis -  Engineer and Founder of VectorCamp, writing optimised assembler for a number of SIMD/Vector ISAs  - konstantinos@vectorcamp.gr
 183     \item Dmitry Selyutin - Libre-SOC engineer, working on binutils SVP64 assembler - ghostmansd@gmail.com
 184     \item Jacob Lifshay - Libre-SOC engineer, CPU arch and verification - programmerjake@gmail.com
 185     \item Cesar Strauss - Libre-SOC engineer, CPU arch and verification - cestrauss@gmail.com
 186     \item Andrey Miroshnikov - Libre-SOC engineer, assisting with documentation - andrey@technepisteme.xyz
 187 \end{itemize}
 188
 189 \newpage
 190 \subsection*{Executive Summary}
 191 \hypertarget{svux2fexecutive_summary}{}
 192 \input{tex_out/executive_summary.tex}
 193
 194 \newpage
 195 \begin{landscape}
 196 \addcontentsline{toc}{chapter}{Comparison Table} \markboth{INTRODUCTION}{}
 197 \hypertarget{svux2fcomparison_table}{}
 198 {
 199 \fontsize{6}{8}\selectfont
 200 \input{tex_out/comparison_table.tex}
 201 }
 202 \end{landscape}
 203
 204 \part{Scalable Vectors Primer}
 205 \input{svp64-primer/acronyms}
 206 %\chapter*{Executive Summary}
 207 \include{svp64-primer/summary}
 208 \bibliography{svp64-primer/references}
 209 \bibliographystyle{ieeetr}
 210
 211 \tableofcontents
 212
 213 % Part II
 214 \part{Scalable Vectors for the Power ISA}
 215
 216
 217 \chapter{Fields and Forms}
 218 \hypertarget{svux2ffields}{}
 219 \input{tex_out/fields.tex}
 220 \chapter{Scalable Vectors for the Power ISA}
 221 \hypertarget{svux2fscalvecpowisa}{}
 222 \hypertarget{SVux7csv}{}
 223 \input{tex_out/sv.tex}
 224 \chapter{Other Vector ISAs}\hypertarget{svux2fvector_isa_comparison}{}
 225 \input{tex_out/vector_isas.tex}
 226 \chapter{Overview}\hypertarget{svux2foverview}{}
 227 \input{tex_out/overview.tex}
 228 \chapter{Compliancy Levels}\hypertarget{svux2fcompliancy_levels}{}
 229 \input{tex_out/compliancy_levels.tex}
 230 \chapter{SVP64}\hypertarget{svux2fsvp64}{}
 231 \input{tex_out/svp64.tex}
 232 \chapter{SPRs}\hypertarget{svux2fsprs}{}
 233 \input{tex_out/sprs.tex}
 234 \chapter{Arithmetic Mode}\hypertarget{svux2fnormal}{}
 235 \input{tex_out/normal.tex}
 236 \chapter{Load/Store Mode}\hypertarget{svux2fldst}{}
 237 \input{tex_out/ldst.tex}
 238 \chapter{Condition Register Fields Mode}\hypertarget{svux2fcr_ops}{}
 239 \input{tex_out/cr_ops.tex}
 240 \chapter{Branch Mode}\hypertarget{svux2fbranches}{}
 241 \input{tex_out/branches.tex}
 242 \chapter{setvl instruction}\hypertarget{svux2fsetvl}{}
 243 \input{tex_out/setvl.tex}
 244 \chapter{svstep instruction}\hypertarget{svux2fsvstep}{}
 245 \input{tex_out/svstep.tex}
 246 \chapter{REMAP subsystem}\hypertarget{svux2fremap}{}
 247 \input{tex_out/remap.tex}
 248 \chapter{Swizzle Move}\hypertarget{svux2fmv.swizzle}{}
 249 \input{tex_out/mv_swizzle.tex}
 250 \chapter{Pack / Unpack}\hypertarget{svux2fmv.vec}{}
 251 \input{tex_out/mv_vec.tex}
 252
 253 \begin{appendices}
 254 \chapter{SVP64 Appendix}\hypertarget{svp64ux2fappendix}{}
 255 \hypertarget{svux2fsvp64ux2fappendix}{}
 256 \input{tex_out/svp64_appendix.tex}
 257 \chapter{SVP64 Quirks}\hypertarget{svux2fsvp64_quirks}{}
 258 \input{tex_out/svp64_quirks.tex}
 259 \chapter{REMAP algorithms}\hypertarget{svux2fremapux2fappendix}{}
 260 \input{tex_out/remap_appendix.tex}
 261 \chapter{Simple-V pseudocode}\hypertarget{svux2fpseudocode_simplev}{}
 262 \input{tex_out/pseudocode_simplev.tex}
 263
 264 \chapter{SVP64 Augmentation Table}\hypertarget{opcode_regs_deduped}{}
 265 \begin{landscape}
 266 {
 267 \fontsize{7}{9}\selectfont
 268 \input{tex_out/opcode_regs_deduped.tex}
 269 }
 270 \end{landscape}
 271
 272 \end{appendices}
 273
 274 % Part III
 275 \part{Scalar Instructions}
 276
 277 \chapter*{Preamble}{}
 278
 279 As explained in the Simple-V introduction
 280 these are all intentionally and specifically Scalar instructions.
 281 They have with almost no exceptions been specifically crafted to
 282 have a justification for their inclusion in the Power ISA as Scalar
 283 instructions purely on their own merit.
 284
 285 \begin{itemize}
 286         \item The biginteger multiply-and-add instruction is similar
 287         to Intel's mulx in that it produces a pair of results.
 288         \item Javascript(tm) rounding is present in ARM as fjcvtzs
 289         and would save an astounding 35 instructions with 5 branches.
 290         \item Whilst there exist CR bit manipulation and copying
 291         instructions there are no CR Field manipulation instructions,
 292         putting pressure on GPRs if several CR fits need to be analysed.
 293         \item one single instruction, bmask, is proposed that covers
 294         the whole of x86 BMI1 and AMD TBM, combined, and provides more.
 295 \end{itemize}
 296
 297 All of these have nothing to do with Simple-V at all: they make
 298 the Power ISA better at modern general-purpose compute, bringing
 299 it up-to-date.
 300
 301 That said: by a wonderful coincidence, should they be included, then
 302 Simple-V's capabilities increase significantly. For example the CRweird
 303 instructions combined with the bitmanip instructions, alongside
 304 Vectorised Rc=1 turn CR Fields into
 305 extremely powerful Predicate masks. bmask not only
 306 covers the BMI and TBM instructions of Intel and AMD it also
 307 includes the RVV set-before-first and set-after-first instructions.
 308
 309 The clean and clear separation between Vectorisation Prefix and Scalar
 310 Suffix is what makes it possible for both Scalar-only and Scalable-Vectors
 311 to benefit.  It also makes proposal much easier, as there is no
 312 inter-dependence.
 313
 314 It is however important to note that the rationale for these instructions
 315 comes from a more general-purpose modern computing paradigm that is
 316 outside of IBM's much more focussed and specialist traditional customer
 317 base. We deeply respect IBM's curator role of the Power ISA of the past 25
 318 years as much as we appreciate their courage in transferring that role
 319 to the OpenPOWER Foundation ISA Working Group.
 320
 321 \chapter{SV Vector ops}\hypertarget{svux2fvector_ops}{}
 322 \input{tex_out/vector_ops.tex}
 323 \chapter{CR Weird ops}\hypertarget{svux2fcr_int_predication}{}
 324 \hypertarget{cr_int_predication}{}
 325 \input{tex_out/cr_int_predication.tex}
 326 \chapter{Bitmanip ops}\hypertarget{svux2fbitmanip}{}
 327 \input{tex_out/bitmanip.tex}
 328 \chapter{FP/Int Conversion ops}\hypertarget{svux2fint_fp_mv}{}
 329 \input{tex_out/int_fp_mv.tex}
 330 \chapter{FP Class ops}\hypertarget{svux2ffclass}{}
 331 \input{tex_out/fclass.tex}
 332 \chapter{Audio and Video Opcodes}\hypertarget{svux2fav_opcodes}{}
 333 \hypertarget{av_opcodes}{}
 334 \input{tex_out/av_opcodes.tex}
 335 \chapter{Big Integer}\hypertarget{svux2fbiginteger}{}
 336 \input{tex_out/big_integer.tex}
 337 \chapter{Transcendentals}\hypertarget{transcendentals}{}
 338 \input{tex_out/transcendentals.tex}
 339 \chapter{Acquire/Release Atomic Memory}\hypertarget{atomics}{}
 340 \input{tex_out/atomics.tex}
 341
 342 \begin{appendices}
 343 \chapter{Big Integer Analysis}\hypertarget{svux2fbigintegerux2fanalysis}{}
 344 \input{tex_out/big_integer_analysis.tex}
 345 \chapter{Bitmanip pseudocode}\hypertarget{svux2fpseudocode_bitmanip}{}
 346 \input{tex_out/pseudocode_bitmanip.tex}
 347 \chapter{Floating Point pseudocode}\hypertarget{isaux2fsvfparith}{}
 348 \input{tex_out/pseudocode_svfparith.tex}
 349 \chapter{Fixed Point pseudocode}
 350 \hypertarget{isaux2fsvfixedarith}{}
 351 \input{tex_out/pseudocode_svfixedarith.tex}
 352 \end{appendices}
 353
 354 % Part IV
 355 \part{Scalar Power ISA pseudocode}
 356 \backmatter % temporary fix for too many appenfices
 357 %\setcounter{chapter}{0}
 358 %\renewcommand{\thechapter}{\Alph{chapter}}
 359
 360 \chapter*{Preamble}
 361 \addcontentsline{toc}{chapter}{Preamble} \markboth{INTRODUCTION}{}
 362
 363 This section contains updated pseudocode from the Power ISA Specification
 364 v3.0B to be executable.  Several bugfixes in Power ISA v3.0B have been
 365 found and reported as a direct result due to actually running the
 366 pseudocode as executable code in a Simulator.
 367 A Formal Correctness Proof Research Paper written by Boris
 368 Shingarov.
 369
 370 Additionally, with SVP64 performing element-width over-rides it is the
 371 \textit{Scalar} pseudocode that needs adapting to variable-length
 372 (\textbf{XLEN}).  Maintaining duplicate identical copies in every
 373 respect \textit{except} for an XLEN as part of the Simple-V Specification
 374 is completely pointless and a waste of time: the updates to include
 375 XLEN need to be part
 376 of the Scalar Power ISA Specification.  This has the added benefit
 377 that it makes life much easier for 32-bit implementors, and has an
 378 additional benefit of making it possible for the Scalar Power ISA
 379 to extend to 128-bit in future (like RV128).
 380
 381 \begin{appendices}
 382 \chapter{Binary Coded Decimal pseudocode}
 383 \hypertarget{svux2fpseudocode_bcd}{}
 384 \input{tex_out/pseudocode_bcd.tex}
 385 \chapter{Branch pseudocode}
 386 \hypertarget{openpowerux2fisaux2fbranch}{}
 387 \hypertarget{svux2fpseudocode_branch}{}
 388 \input{tex_out/pseudocode_branch.tex}
 389 \chapter{Fixed Point Compare pseudocode}
 390 \hypertarget{svux2fpseudocode_comparefixed}{}
 391 \input{tex_out/pseudocode_comparefixed.tex}
 392 \chapter{Condition Register pseudocode}
 393 \hypertarget{svux2fpseudocode_condition}{}
 394 \input{tex_out/pseudocode_condition.tex}
 395
 396 \chapter{Fixed Point Arithmetic pseudocode}
 397 \hypertarget{svux2fpseudocode_fixedarith}{}
 398 \input{tex_out/pseudocode_fixedarith.tex}
 399 \chapter{Fixed Point Load pseudocode}
 400 \hypertarget{svux2fpseudocode_fixedload}{}
 401 \input{tex_out/pseudocode_fixedload.tex}
 402 \chapter{Fixed Point Logical pseudocode}
 403 \hypertarget{svux2fpseudocode_fixedlogical}{}
 404 \input{tex_out/pseudocode_fixedlogical.tex}
 405 \chapter{Fixed Point Rotate pseudocode}
 406 \hypertarget{svux2fpseudocode_fixedshift}{}
 407 \input{tex_out/pseudocode_fixedshift.tex}
 408
 409 \chapter{Fixed Point Store pseudocode}
 410 \hypertarget{svux2fpseudocode_fixedstore}{}
 411 \input{tex_out/pseudocode_fixedstore.tex}
 412 \chapter{Fixed Point Trap pseudocode}
 413 \hypertarget{svux2fpseudocode_fixedtrap}{}
 414 \input{tex_out/pseudocode_fixedtrap.tex}
 415 \chapter{Special Purpose Register pseudocode}
 416 \hypertarget{svux2fpseudocode_sprset}{}
 417 \input{tex_out/pseudocode_sprset.tex}
 418 \chapter{String Load/Store pseudocode}
 419 \hypertarget{svux2fpseudocode_stringldst}{}
 420 \input{tex_out/pseudocode_stringldst.tex}
 421 \chapter{System Call pseudocode}
 422 \hypertarget{svux2fpseudocode_system}{}
 423 \input{tex_out/pseudocode_system.tex}
 424
 425 \chapter{Floating Point Load pseudocode}
 426 \hypertarget{svux2fpseudocode_fpload}{}
 427 \input{tex_out/pseudocode_fpload.tex}
 428 \chapter{Floating Point Store pseudocode}
 429 \hypertarget{svux2fpseudocode_fpstore}{}
 430 \input{tex_out/pseudocode_fpstore.tex}
 431 \chapter{Floating Point Move pseudocode}
 432 \hypertarget{svux2fpseudocode_fpmove}{}
 433 \input{tex_out/pseudocode_fpmove.tex}
 434 \chapter{Floating Point Arithmetic pseudocode}
 435 \hypertarget{svux2fpseudocode_fparith}{}
 436 \input{tex_out/pseudocode_fparith.tex}
 437 \chapter{Floating Point Integer Conversion pseudocode}
 438 \hypertarget{svux2fpseudocode_fpcvt}{}
 439 \input{tex_out/pseudocode_fpcvt.tex}
 440
 441 \end{appendices}
 442
 443
 444
 445
 446 \end{document}