openpower/simple_v_spec.tex

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 105 \makeatletter\@addtoreset{chapter}{part}\makeatother%
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 108
 109
 110 \date{}
 111
 112 \begin{document}
 113
 114 \chapter*{Preamble}
 115 \addcontentsline{toc}{chapter}{Preamble} \markboth{INTRODUCTION}{}
 116
 117 This document is an auto-generated version of the Draft SVP64
 118 Specification available at
 119
 120 \begin{verbatim}
 121      https://libre-soc.org/openpower/sv
 122 \end{verbatim}
 123
 124 for which the source code is available at
 125
 126 \begin{verbatim}
 127      https://git.libre-soc.org/?p=libreriscv.git;a=tree;f=openpower;hb=HEAD
 128 \end{verbatim}
 129
 130 This PDF may be created with "make pdf" from the following file:
 131
 132 \begin{verbatim}
 133     https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/Makefile;hb=HEAD
 134 \end{verbatim}
 135
 136 by executing the following commands:
 137
 138 \begin{verbatim}
 139     git clone https://git.libre-soc.org/git/libreriscv.git libresoc
 140     cd libresoc/libresoc/openpower
 141     make pdf
 142 \end{verbatim}
 143
 144 Simple-V Cray-style Vectors have been developed by the Libre-SOC Team,
 145 sponsored by the NLnet Foundation and NGI POINTER under
 146 EU Grants 871528 and 957073.
 147
 148 Simple-V is in DRAFT Status and will be submitted publicly
 149 (non-confidentially) through the OPF ISA WG "External Submissions"
 150 Process. Funding from NLnet, through their Privacy and Enhanced Trust
 151 Programme, requires full transparency.
 152
 153 \tableofcontents
 154
 155 \part{Scalable Vectors}
 156
 157 \chapter{Fields and Forms}
 158 \hypertarget{svux2ffields}{}
 159 \input{tex_out/fields.tex}
 160 \chapter{Scalable Vectors for the Power ISA}
 161 \hypertarget{svux2fscalvecpowisa}{}
 162 \hypertarget{SVux7csv}{}
 163 \input{tex_out/sv.tex}
 164 \chapter{Other Vector ISAs}\hypertarget{svux2fvector_isa_comparison}{}
 165 \input{tex_out/vector_isas.tex}
 166 \chapter{Overview}\hypertarget{svux2foverview}{}
 167 \input{tex_out/overview.tex}
 168 \chapter{Compliancy Levels}\hypertarget{svux2fcompliancy_levels}{}
 169 \input{tex_out/compliancy_levels.tex}
 170 \chapter{SVP64}\hypertarget{svux2fsvp64}{}
 171 \input{tex_out/svp64.tex}
 172 \chapter{SPRs}\hypertarget{svux2fsprs}{}
 173 \input{tex_out/sprs.tex}
 174 \chapter{Arithmetic Mode}\hypertarget{svux2fnormal}{}
 175 \input{tex_out/normal.tex}
 176 \chapter{Load/Store Mode}\hypertarget{svux2fldst}{}
 177 \input{tex_out/ldst.tex}
 178 \chapter{Condition Register Fields Mode}\hypertarget{svux2fcr_ops}{}
 179 \input{tex_out/cr_ops.tex}
 180 \chapter{Branch Mode}\hypertarget{svux2fbranches}{}
 181 \input{tex_out/branches.tex}
 182 \chapter{setvl instruction}\hypertarget{svux2fsetvl}{}
 183 \input{tex_out/setvl.tex}
 184 \chapter{svstep instruction}\hypertarget{svux2fsvstep}{}
 185 \input{tex_out/svstep.tex}
 186 \chapter{REMAP subsystem}\hypertarget{svux2fremap}{}
 187 \input{tex_out/remap.tex}
 188 \chapter{Swizzle Move}\hypertarget{svux2fmv.swizzle}{}
 189 \input{tex_out/mv_swizzle.tex}
 190 \chapter{Pack / Unpack}\hypertarget{svux2fmv.vec}{}
 191 \input{tex_out/mv_vec.tex}
 192
 193 \begin{appendices}
 194 \chapter{SVP64 Appendix}\hypertarget{svp64ux2fappendix}{}
 195 \input{tex_out/svp64_appendix.tex}
 196 \chapter{SVP64 Quirks}\hypertarget{svux2fsvp64_quirks}{}
 197 \input{tex_out/svp64_quirks.tex}
 198 \chapter{Simple-V pseudocode}\hypertarget{svux2fpseudocode_simplev}{}
 199 \input{tex_out/pseudocode_simplev.tex}
 200 \chapter{SVP64 Augmentation Table}\hypertarget{opcode_regs_deduped}{}
 201 \begin{landscape}
 202 {
 203 \fontsize{7}{9}\selectfont
 204 \input{tex_out/opcode_regs_deduped.tex}
 205 }
 206 \end{landscape}
 207 \end{appendices}
 208
 209 \part{Scalar Instructions}
 210
 211 \chapter{Vector Assist ops}\hypertarget{svux2fvector_ops}{}
 212 \input{tex_out/vector_ops.tex}
 213 \chapter{CR Weird ops}\hypertarget{svux2fcr_int_predication}{}
 214 \input{tex_out/cr_int_predication.tex}
 215 \chapter{Bitmanip ops}\hypertarget{svux2fbitmanip}{}
 216 \input{tex_out/bitmanip.tex}
 217 \chapter{FP/Integer conversion ops}\hypertarget{svux2fint_fp_mv}{}
 218 \input{tex_out/int_fp_mv.tex}
 219 \chapter{FP Class ops}\hypertarget{svux2ffclass}{}
 220 \input{tex_out/fclass.tex}
 221 \chapter{Audio/Video ops}\hypertarget{svux2fav_opcodes}{}
 222 \input{tex_out/av_opcodes.tex}
 223 \chapter{Big Integer}\hypertarget{svux2fbiginteger}{}
 224 \input{tex_out/big_integer.tex}
 225
 226 \begin{appendices}
 227 \chapter{Big Integer Analysis}\hypertarget{svux2fbigintegerux2fanalysis}{}
 228 \input{tex_out/big_integer_analysis.tex}
 229 \chapter{Bitmanip pseudocode}\hypertarget{svux2fpseudocode_bitmanip}{}
 230 \input{tex_out/pseudocode_bitmanip.tex}
 231 \chapter{Floating Point pseudocode}\hypertarget{svux2fpseudocode_svfparith}{}
 232 \input{tex_out/pseudocode_svfparith.tex}
 233 \chapter{Fixed Point pseudocode}
 234 \hypertarget{svux2fpseudocode_svfixedarith}{}
 235 \input{tex_out/pseudocode_svfixedarith.tex}
 236 \end{appendices}
 237
 238 \part{Scalar Power ISA pseudocode}
 239
 240 \chapter*{Preamble}
 241 \addcontentsline{toc}{chapter}{Preamble} \markboth{INTRODUCTION}{}
 242
 243 This section contains updated pseudocode from the Power ISA Specification
 244 v3.0B to be executable.  Several bugfixes in Power ISA v3.0B have been
 245 found and reported as a direct result due to actually running the
 246 pseudocode as executable code in a Simulator.
 247 A Formal Correctness Proof Research Paper written by Boris
 248 Shingarov.
 249
 250 Additionally, with SVP64 performing element-width over-rides it is the
 251 \textit{Scalar} pseudocode that needs adapting to variable-length
 252 (\textbf{XLEN}).  Maintaining duplicate identical copies in every
 253 respect \textit{except} for an XLEN as part of the Simple-V Specification
 254 is completely pointless and a waste of time: the updates to include
 255 XLEN need to be part
 256 of the Scalar Power ISA Specification.  This has the added benefit
 257 that it makes life much easier for 32-bit implementors, and has an
 258 additional benefit of making it possible for the Scalar Power ISA
 259 to extend to 128-bit in future (like RV128).
 260
 261 \begin{appendices}
 262 \chapter{Binary Coded Decimal pseudocode}
 263 \hypertarget{svux2fpseudocode_bcd}{}
 264 \input{tex_out/pseudocode_bcd.tex}
 265 \chapter{Branch pseudocode}
 266 \hypertarget{svux2fpseudocode_branch}{}
 267 \input{tex_out/pseudocode_branch.tex}
 268 \chapter{Fixed Point Compare pseudocode}
 269 \hypertarget{svux2fpseudocode_comparefixed}{}
 270 \input{tex_out/pseudocode_comparefixed.tex}
 271 \chapter{Condition Register pseudocode}
 272 \hypertarget{svux2fpseudocode_condition}{}
 273 \input{tex_out/pseudocode_condition.tex}
 274
 275 \chapter{Fixed Point Arithmetic pseudocode}
 276 \hypertarget{svux2fpseudocode_fixedarith}{}
 277 \input{tex_out/pseudocode_fixedarith.tex}
 278 \chapter{Fixed Point Load pseudocode}
 279 \hypertarget{svux2fpseudocode_fixedload}{}
 280 \input{tex_out/pseudocode_fixedload.tex}
 281 \chapter{Fixed Point Logical pseudocode}
 282 \hypertarget{svux2fpseudocode_fixedlogical}{}
 283 \input{tex_out/pseudocode_fixedlogical.tex}
 284 \chapter{Fixed Point Rotate pseudocode}
 285 \hypertarget{svux2fpseudocode_fixedshift}{}
 286 \input{tex_out/pseudocode_fixedshift.tex}
 287
 288 \chapter{Fixed Point Store pseudocode}
 289 \hypertarget{svux2fpseudocode_fixedstore}{}
 290 \input{tex_out/pseudocode_fixedstore.tex}
 291 \chapter{Fixed Point Trap pseudocode}
 292 \hypertarget{svux2fpseudocode_fixedtrap}{}
 293 \input{tex_out/pseudocode_fixedtrap.tex}
 294 \chapter{Special Purpose Register pseudocode}
 295 \hypertarget{svux2fpseudocode_sprset}{}
 296 \input{tex_out/pseudocode_sprset.tex}
 297
 298 \chapter{String Load/Store pseudocode}
 299 \hypertarget{svux2fpseudocode_stringldst}{}
 300 \input{tex_out/pseudocode_stringldst.tex}
 301
 302 \chapter{System Call pseudocode}
 303 \hypertarget{svux2fpseudocode_system}{}
 304 \input{tex_out/pseudocode_system.tex}
 305
 306 \end{appendices}
 307
 308
 309
 310
 311 \end{document}