openpower/sv/16_bit_compressed.mdwn

   1 # 16 bit Compressed
   2
   3 See:
   4
   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=238>
   6 * <https://ftp.libre-soc.org/VLE_314-68105.pdf> VLE Encoding
   7
   8 This one is a conundrum.  OpenPOWER ISA was never designed with 16
   9 bit in mind.  VLE was added 10 years ago but only by way of marking
  10 an entire 64k page as "VLE".  With VLE not maintained it is not
  11 fully compatible with current PowerISA.
  12
  13 Here, in order to embed 16 bit into a predominantly 32 bit stream the
  14 overhead of using an entire 16 bits just to switch into Compressed mode
  15 is itself a significant overhead.  The situation is made worse by 5 bits
  16 being taken up by Major Opcode space, leaving only 11 bits to allocate
  17 to actual instructions.
  18
  19 In addition we would like to add SV-C32 which is a Vectorised version
  20 of 16 bit Compressed, and ideally have a variant that adds the 27-bit
  21 prefix format from SV-P64, as well.
  22
  23 Potential ways to reduce pressure on the 16 bit space are:
  24
  25 * To provide "paging".  This involves bank-switching to alternative optimised encodings for specific workloads
  26 * To enter "16 bit mode" for durations specified at the start
  27 * To reserve one bit of every 16 bit instruction to indicate that the 16 bit mode is to continue to be sustained
  28
  29 This latter would be useful in the Vector context to have an alternative
  30 meaning: as the bit which determines whether the instruction is 11-bit
  31 prefixed or 27-bit prefixed:
  32
  33     0 1 2 3 4 5 6 7 8 9 a b c d e f |
  34     |major op | 11 bit vector prefix|
  35     |16 bit opcode  alt vec. mode ^ |
  36     | extra vector prefix if alt set|
  37
  38 Using a major opcode to enter 16 bit mode, leaves 11 bits to find
  39 something to use them for:
  40
  41     0 1 2 3 4 5 6 7 8 9 a b c d e f |
  42     |major op | what to do here   1 |
  43     |16 bit    stay in 16bit mode 1 |
  44     |16 bit    stay in 16bit mode 1 |
  45     |16 bit       exit 16bit mode 0 |
  46
  47 One possibility is that the 11 bits are used for bank selection, with
  48 some room for additional context such as altering the registers used
  49 for the 16 bit operations (bank selection of which scalar regs)
  50
  51 Another is to use the 11 bits for only the utmost commonly used
  52 instructions.  That being the case then even one of those 11 bits would
  53 also need to be dedicated to saying if 16 bit mode is to be continued.
  54 10 bits remain for actual opcodes!
  55
  56 # Opcode Allocation Ideas
  57
  58 * one bit from the 16-bit mode is used to indicate that 32-bit mode
  59   is to be dropped into for only one single instruction
  60   <https://bugs.libre-soc.org/show_bug.cgi?id=238#c2>
  61
  62 ## Opcodes exploration (Attempt 1)
  63
  64 Switching between different encoding modes is controlled by M (alone)
  65 in 10-bit mode, and M and N in 16-bit mode.
  66
  67 * M in 10-bit mode if zero indicates that following instructions are
  68   standard OpenPOWER ISA 32-bit encoded (including, redundantly,
  69   further 10/16-bit instructions)
  70 * M in 10-bit mode if 1 indicates that following instructions are
  71   in 16-bit encoding mode
  72
  73 Once in 16-bit mode:
  74
  75 * 0b01 (M=1, N=0): stay in 16-bit mode
  76 * 0b00: leave 16-bit mode permanently (return to standard OpenPOWER ISA)
  77 * 0b10: leave 16-bit mode for one cycle (return to standard OpenPOWER ISA)
  78 * 0b11: free to be used for something completely different.
  79
  80 The current "top" idea for 0b11 is to use it for a new encoding format
  81 of predominantly "immediates-based" 16-bit instructions (branch-conditional,
  82 addi, mulli etc.)
  83
  84 The Compressed Major Opcode is in bits 5-7.
  85
  86 * M+N mode-switching is not available for C-Major 0b001 or 0b111
  87
  88 ### Immediate Opcodes
  89
  90 only available in 16-bit mode, and only available when M=1 and N=1
  91
  92     | 0 | 1  | 2 3 4 | | 567.8 | 9ab  | c d e     | f |
  93     | 1 | o2 |  RT   | | 010.1 | RB|0 | offs      | addi.
  94     | 1 | o2 |  RT   | | 011.1 | RB|0 | offs      | addis.
  95     | 1 | o2     | 0 | | 100.1 | RB   | offs      | cmpdi
  96     | 1 | o2     | 1 | | 100.1 | RB   | offs      | cmpwi
  97     | 1 | o2     | 0 | | 101.1 | RA   | offs      | ldi
  98     | 1 | o2     | 1 | | 101.1 | RA   | offs      | lwi
  99     | 1 | o2     | 0 | | 110.1 | RA   | offs      | flwi
 100     | 1 | o2     | 1 | | 110.1 | RA   | offs      | fldi
 101
 102 * Note that bc is included (below)
 103 * immediate is constructed from offs (LSBs) and o2 (MSB)
 104 * for loads, offset is aligned.  8byte: o2||offs||0b000 4byte: 0b00
 105 * RB|0 if RB is zero, addi. becomes "li"
 106
 107 ### Branch
 108
 109 10 bit mode may be expanded by 16 bit mode later, adding capabilities
 110 that do not fit in the extreme limited space.
 111
 112     | 16-bit mode | | 10-bit mode                 |
 113     | 0 | 1 | 234 | | 567.8  | 9  ab | c   de | f |
 114     | 0 | 0   000 | | 000.0  | 0  00 | 0   00 | 0 | illeg
 115     | 0 | 0   000 | | 000.1  | 0  00 | 0   00 | 0 | nop
 116     | N | offs2   | | 000.LK | offs!=0        | M | b, bl
 117     | 1 | offs2   | | 000.LK | BI    | BO1 oo | 1 | bc, bcl
 118     | N | BO3 BI3 | | 001.0  | LK BI | BO     | M | bclr, bclrl
 119
 120 16 bit mode:
 121
 122 * bc only available when N,M=0b11
 123 * offs2 extends offset in MSBs
 124 * BI3 extends BI in MSBs to allow selection of full CR
 125 * BO3 extends BO
 126 * bc offset constructed from oo as LSBs and offs2 as MSBs
 127 * bc BI allows selection of all bits from CR0 or CR1
 128 * bc CR check is always active (as if BO0=1) therefore BO1 inverts
 129
 130 10 bit mode:
 131
 132 * illegal (all zeros) covers part of branch (offs=0,M=0,LK=0)
 133 * nop also covers part of branch (offs=0,M=0,LK=1)
 134 * bc **not available** in 10-bit mode
 135 * BO[0] enables CR check, BO[1] inverts check
 136 * BI refers to CR0 only (4 bits of)
 137 * no Branch Conditional with immediate
 138 * no Absolute Address
 139 * CTR mode allowed with BO[2] for b only.
 140 * offs is to 2 byte (signed) aligned
 141 * all branches to 2 byte aligned
 142
 143 ### LD/ST
 144
 145     | 16-bit mode       | | 10-bit mode               |
 146     | 0   | 1   | 2 3 4 | | 567.8 | 9 a b | c d e | f |
 147     | RB2 | RA2 |  RT   | | 001.1 | 1  RA | 0  RB | M | fld
 148     | RA2 | RT2 |  RB   | | 001.1 | 1  RA | 1  RT | M | fst
 149     |     |     |  RT   | | 111.0 |  RA   |  RB   | M | ld
 150     |     |     |  RB   | | 111.1 |  RA   |  RT   | M | st
 151
 152 * elwidth overrides can set different widths
 153
 154 16 bit mode:
 155
 156 * F=1 is FLD, FST
 157 * RA2 extends RA to 3 bits (MSB)
 158 * RT2 extends RT to 3 bits (MSB)
 159
 160 10 bit mode:
 161
 162 * RA and RB are only 2 bit (0-3)
 163 * for LD, RT is implicitly RB: "ld RT=RB, RA(RB)"
 164 * for ST, there is no offset: "st RT, RA(0)"
 165
 166 ### Arithmetic
 167
 168     | 16-bit mode   | | 10-bit mode             |
 169     | 0 | 1 | 2 3 4 | | 567.8 | 9ab | c d e | f |
 170     | N |   |  RT   | | 010.0 | RB  | RA!=0 | M | add
 171     | N |   |  RT   | | 010.1 | RB  | RA    | M | mul
 172     | N |   | RT!=0 | | 011.0 | RB  | RA!=0 | M | sub.
 173     | N | 0 | 000   | | 011.0 | RB  | RA!=0 | M | cmpw
 174     | N | 1 | 000   | | 011.0 | RB  | RA!=0 | M | cmpl
 175     | N |   |  RT   | | 011.0 | RB  | 000   | M | neg.
 176
 177 10 bit mode:
 178
 179 * sub. default CR target is CR0
 180 * for (RA|0) when RA=0 the input is a zero immediate,
 181   meaning that sub. becomes neg.
 182 * RT is implicitly RB: "add RT(=RB), RA, RB"
 183
 184 ### Logical
 185
 186     | 16-bit mode   | | 10-bit mode             |
 187     | 0 | 1 | 2 3 4 | | 567.8 | 9ab | c d e | f |
 188     | N | 0 |  RT   | | 100.0 | RB  | RA!=0 | M | and
 189     | N | 0 |  RT   | | 100.1 | RB  | RA!=0 | M | nand
 190     | N | 0 |  RT   | | 101.0 | RB  | RA!=0 | M | or
 191     | N | 0 |  RT   | | 101.1 | RB  | RA!=0 | M | nor
 192     | N | 0 |  RT   | | 100.0 | RB  | 0 0 0 | M | extsw
 193     | N | 0 |  RT   | | 100.1 | RB  | 0 0 0 | M | cntlz
 194     | N | 0 |  RT   | | 101.0 | RB  | 0 0 0 | M | popcnt
 195     | N | 0 |  RT   | | 101.1 | RB  | 0 0 0 | M | not
 196
 197 16-bit mode only:
 198
 199     | 0 | 1 | 2 3 4 | | 567.8 | 9ab | c d e | f |
 200     | N | 1 |  RT   | | 100.0 | RB  | RA!=0 | M |
 201     | N | 1 |  RT   | | 100.1 | RB  | RA!=0 | M |
 202     | N | 1 |  RT   | | 101.0 | RB  | RA!=0 | M | xor
 203     | N | 1 |  RT   | | 101.1 | RB  | RA!=0 | M | eqv (xnor)
 204     | N | 1 |  RT   | | 100.0 | RB  | 0 0 0 | M | extsb
 205     | N | 1 |  RT   | | 100.1 | RB  | 0 0 0 | M | cnttz
 206     | N | 1 |  RT   | | 101.0 | RB  | 0 0 0 | M |
 207     | N | 1 |  RT   | | 101.1 | RB  | 0 0 0 | M | extsh
 208
 209 10 bit mode:
 210
 211 * for (RA|0) when RA=0 the input is a zero immediate,
 212   meaning that nor becomes not
 213 * cntlz, popcnt, exts **not available** in 10-bit mode
 214 * RT is implicitly RB: "and RT(=RB), RA, RB"
 215
 216 ### Floating Point
 217
 218 Note here that elwidth overrides (SV Prefix) can be used to select FP16/32/64
 219
 220     | 16-bit mode   | | 10-bit mode             |
 221     | 0 | 1 | 2 3 4 | | 567.8 | 9ab | c d e | f |
 222     | N |   |  RT   | | 011.1 | RB  | RA!=0 | M | fsub.
 223     | N | 0 |  RT   | | 110.0 | RB  | RA!=0 | M | fadd
 224     | N | 0 |  RT   | | 110.1 | RB  | RA!=0 | M | fmul
 225     | N | 0 |  RT   | | 011.1 | RB  | 0 0 0 | M | fneg.
 226     | N | 0 |  RT   | | 110.0 | RB  | 0 0 0 | M |
 227     | N | 0 |  RT   | | 110.1 | RB  | 0 0 0 | M |
 228
 229 16-bit mode only:
 230
 231     | 0 | 1 | 2 3 4 | | 567.8 | 9ab | c d e | f |
 232     | N | 1 |  RT   | | 011.1 | RB  | RA!=0 | M |
 233     | N | 1 |  RT   | | 110.0 | RB  | RA!=0 | M |
 234     | N | 1 |  RT   | | 110.1 | RB  | RA!=0 | M | fdiv
 235     | N | 1 |  RT   | | 011.1 | RB  | 0 0 0 | M | fabs.
 236     | N | 1 |  RT   | | 110.0 | RB  | 0 0 0 | M | fmr.
 237     | N | 1 |  RT   | | 110.1 | RB  | 0 0 0 | M |
 238
 239 10 bit mode:
 240
 241 * fsub. fneg. and fmr. default target is CR1
 242 * fmr. is **not available** in 10-bit mode
 243 * fdiv is **not available** in 10-bit mode
 244
 245 16 bit mode:
 246
 247 * fmr. copies RB to RT (and sets CR1)
 248
 249 ### Condition Register
 250
 251     | 16-bit mode   | | 10-bit mode            |
 252     | 0 1 2 3 | 4   | | 567.8 | 9 ab | cde | f |
 253     | 0 0 0 0 | BF2 | | 001.1 | 0 BF | BFA | M | mcrf
 254     | 0 0 0 1 | BA2 | | 001.1 | 0 BA | BB  | M | crnor
 255     | 0 1 0 0 | BA2 | | 001.1 | 0 BA | BB  | M | crandc
 256     | 0 1 1 0 | BA2 | | 001.1 | 0 BA | BB  | M | crxor
 257     | 0 1 1 1 | BA2 | | 001.1 | 0 BA | BB  | M | crnand
 258     | 1 0 0 0 | BA2 | | 001.1 | 0 BA | BB  | M | crand
 259     | 1 0 0 1 | BA2 | | 001.1 | 0 BA | BB  | M | creqv
 260     | 1 1 0 1 | BA2 | | 001.1 | 0 BA | BB  | M | crorc
 261     | 1 1 1 0 | BA2 | | 001.1 | 0 BA | BB  | M | cror
 262
 263 10 bit mode:
 264
 265 * mcrf BF is only 2 bits which means the destination is only CR0-CR3
 266 * CR operations: **not available** in 10-bit mode
 267
 268 16 bit mode:
 269
 270 * mcrf BF2 extends BF (in MSB) to 3 bits
 271 * CR operations: destination register is same as BA.
 272 * CR operations: only possible on CR0 and CR1
 273
 274 SV (Vector Mode):
 275
 276 * CR operations: greatly extended reach/range (useful for predicates)
 277
 278 ### System
 279
 280 cbank: Selection of Compressed-encoding "Bank".  Different "banks" give different
 281 meanings to opcodes.
 282 Example: CBank=0b001 is heavily optimised to A/Video
 283 Encode/Decode.
 284
 285     | 16-bit mode | | 10-bit mode               |
 286     | 0 1 | 2 3 4 | | 567.8 | 9 a b | c d e | f |
 287     |       Bank2 | | 010.0 | CBank | 0 0 0 | M | cbank
 288
 289 **not available** in 10-bit mode:
 290
 291     | 0 1 2 3 | 4  | | 567.8 | 9 ab | c d e  | f |
 292     | 1 1 1 1 | 0  | | 001.1 | 0 00 |  RT    | M | mtlr
 293     | 1 1 1 1 | 0  | | 001.1 | 0 01 |  RT    | M | mtctr
 294     | 1 1 1 1 | 0  | | 001.1 | 0 11 |  RT    | M | mtcr
 295     | 1 1 1 1 | 1  | | 001.1 | 0 00 |  RA    | M | mflr
 296     | 1 1 1 1 | 1  | | 001.1 | 0 01 |  RA    | M | mfctr
 297     | 1 1 1 1 | 1  | | 001.1 | 0 11 |  RA    | M | mfcr
 298
 299 ### Unallocated
 300
 301     | 0 1 2 3 | 4  | | 567.8 | 9 ab | c d e  | f |
 302     | 0 0 1 0 |    | | 001.1 | 0    |        | M |
 303     | 0 0 1 1 |    | | 001.1 | 0    |        | M |
 304     | 0 1 0 1 |    | | 001.1 | 0    |        | M |
 305     | 1 0 1 0 |    | | 001.1 | 0    |        | M |
 306     | 1 0 1 1 |    | | 001.1 | 0    |        | M |
 307     | 1 1 0 0 |    | | 001.1 | 0    |        | M |
 308     | 1 1 1 1 | 0  | | 001.1 | 0 10 |        | M |
 309     | 1 1 1 1 | 1  | | 001.1 | 0 10 |        | M |
 310