openpower/sv/16_bit_compressed.mdwn

   1 # 16 bit Compressed
   2
   3 See:
   4
   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=238>
   6 * <https://ftp.libre-soc.org/VLE_314-68105.pdf> VLE Encoding
   7
   8 This one is a conundrum.  OpenPOWER ISA was never designed with 16
   9 bit in mind.  VLE was added 10 years ago but only by way of marking
  10 an entire 64k page as "VLE".  With VLE not maintained it is not
  11 fully compatible with current PowerISA.
  12
  13 Here, in order to embed 16 bit into a predominantly 32 bit stream the
  14 overhead of using an entire 16 bits just to switch into Compressed mode
  15 is itself a significant overhead.  The situation is made worse by 5 bits
  16 being taken up by Major Opcode space, leaving only 11 bits to allocate
  17 to actual instructions.
  18
  19 In addition we would like to add SV-C32 which is a Vectorised version
  20 of 16 bit Compressed, and ideally have a variant that adds the 27-bit
  21 prefix format from SV-P64, as well.
  22
  23 Potential ways to reduce pressure on the 16 bit space are:
  24
  25 * To provide "paging".  This involves bank-switching to alternative optimised encodings for specific workloads
  26 * To enter "16 bit mode" for durations specified at the start
  27 * To reserve one bit of every 16 bit instruction to indicate that the 16 bit mode is to continue to be sustained
  28
  29 This latter would be useful in the Vector context to have an alternative
  30 meaning: as the bit which determines whether the instruction is 11-bit
  31 prefixed or 27-bit prefixed:
  32
  33     0 1 2 3 4 5 6 7 8 9 a b c d e f |
  34     |major op | 11 bit vector prefix|
  35     |16 bit opcode  alt vec. mode ^ |
  36     | extra vector prefix if alt set|
  37
  38 Using a major opcode to enter 16 bit mode, leaves 11 bits to find
  39 something to use them for:
  40
  41     0 1 2 3 4 5 6 7 8 9 a b c d e f |
  42     |major op | what to do here   1 |
  43     |16 bit    stay in 16bit mode 1 |
  44     |16 bit    stay in 16bit mode 1 |
  45     |16 bit       exit 16bit mode 0 |
  46
  47 One possibility is that the 11 bits are used for bank selection, with
  48 some room for additional context such as altering the registers used
  49 for the 16 bit operations (bank selection of which scalar regs)
  50
  51 Another is to use the 11 bits for only the utmost commonly used
  52 instructions.  That being the case then even one of those 11 bits would
  53 also need to be dedicated to saying if 16 bit mode is to be continued.
  54 10 bits remain for actual opcodes!
  55
  56 # Opcode Allocation Ideas
  57
  58 * one bit from the 16-bit mode is used to indicate that 32-bit mode
  59   is to be dropped into for only one single instruction
  60   <https://bugs.libre-soc.org/show_bug.cgi?id=238#c2>
  61
  62 ## Opcodes exploration (Attempt 1)
  63
  64 Switching between different encoding modes is controlled by M (alone)
  65 in 10-bit mode, and M and N in 16-bit mode.
  66
  67 * M in 10-bit mode if zero indicates that following instructions are
  68   standard OpenPOWER ISA 32-bit encoded (including, redundantly,
  69   further 10/16-bit instructions)
  70 * M in 10-bit mode if 1 indicates that following instructions are
  71   in 16-bit encoding mode
  72
  73 Once in 16-bit mode:
  74
  75 * 0b01 (M=1, N=0): stay in 16-bit mode
  76 * 0b00: leave 16-bit mode permanently (return to standard OpenPOWER ISA)
  77 * 0b10: leave 16-bit mode for one cycle (return to standard OpenPOWER ISA)
  78 * 0b11: free to be used for something completely different.
  79
  80 The current "top" idea for 0b11 is to use it for a new encoding format
  81 of predominantly "immediates-based" 16-bit instructions (branch-conditional,
  82 addi, mulli etc.)
  83
  84 The Compressed Major Opcode is in bits 5-7.
  85
  86 * M+N mode-switching is not available for C-Major 0b000 or 0b111
  87
  88 ### Immediate Opcodes
  89
  90 only available in 16-bit mode, and only available when M=1 and N=1
  91
  92     | 0 | 1  | 2 3 4 | | 567 | 89a | b c | d   | e | f |
  93     | 1 | o2 |  RT   | | 010 | RB  | offs      | 1 | addi.
  94     | 1 | o2 |  RT   | | 011 | RB  | offs      | 1 | addis.
  95     | 1 | o2     | 0 | | 100 | RB  | offs      | 1 | cmpdi
  96     | 1 | o2     | 1 | | 100 | RB  | offs      | 1 | cmpwi
  97     | 1 | o2 |  RT   | | 101 | RA  | offs      | 1 | ldi
  98     | 1 | o2 |  RT   | | 110 | RA  | offs      | 1 | sti
  99
 100 * Note that bc is included (below)
 101 * immediate is constructed from offs (LSBs) and o2 (MSB)
 102
 103 ### Branch
 104
 105 10 bit mode may be expanded by 16 bit mode later, adding capabilities
 106 that do not fit in the extreme limited space.
 107
 108     | 16-bit mode | | 10-bit mode                |
 109     | 0 | 1 | 234 | | 567 | 8 9 a | b | c d | e  | f |
 110     | N | BO3 BI3 | | 000 | 0  BI | BO      | LK | M | b, blr
 111     | N | offs2   | | 001 |    offs         | LK | M | b
 112     | 1 | offs2   | | 001 | BI    | BO1 oo  | LK | 1 | bc
 113
 114 16 bit mode:
 115
 116 * bc only available when N,M=0b11
 117 * offs2 extends offset in MSBs
 118 * BI3 extends BI in MSBs to allow selection of full CR
 119 * BO3 extends BO
 120 * bc offset constructed from oo as LSBs and offs2 as MSBs
 121 * bc BI allows selection of all bits from CR0 or CR1
 122 * bc CR check is always active (as if BO0=1) therefore BO1 inverts
 123
 124 10 bit mode:
 125
 126 * bc **not available** in 10-bit mode
 127 * BO[0] enables CR check, BO[1] inverts check
 128 * BI refers to CR0 only (4 bits of)
 129 * no Branch Conditional with immediate
 130 * no Absolute Address
 131 * CTR mode allowed with BO[2] for b only.
 132 * offs is to 2 byte (signed) aligned
 133 * all branches to 2 byte aligned
 134
 135 ### LD/ST
 136
 137     | 16-bit mode       | | 10-bit mode             |
 138     | 0   | 1   | 2 3 4 | | 567 | 8 9 a | b c d | e | f |
 139     | RB2 | RA2 |  RT   | | 001 | 1  RA | 1  RB | 0 | M | fld
 140     | RA2 | RT2 |  RB   | | 001 | 1  RA | 1  RT | 1 | M | fst
 141     |     |     |  RT   | | 111 |  RA   |  RB   | 0 | M | ld
 142     |     |     |  RB   | | 111 |  RA   |  RT   | 1 | M | st
 143
 144 * elwidth overrides can set different widths
 145
 146 16 bit mode:
 147
 148 * F=1 is FLD, FST
 149 * RA2 extends RA to 3 bits (MSB)
 150 * RT2 extends RT to 3 bits (MSB)
 151
 152 10 bit mode:
 153
 154 * RA and RB are only 2 bit (0-3)
 155 * for LD, RT is implicitly RB: "ld RT=RB, RA(RB)"
 156 * for ST, there is no offset: "st RT, RA(0)"
 157
 158 ### Arithmetic
 159
 160     | 16-bit mode   | | 10-bit mode             |
 161     | 0 | 1 | 2 3 4 | | 567 | 8 9 a | b c d | e | f |
 162     | N |   |  RT   | | 010 | RB    | RA!=0 | 0 | M | add
 163     | N |   | RT!=0 | | 011 | RB    | RA!=0 | 0 | M | sub.
 164     | N | 0 | 000   | | 011 | RB    | RA!=0 | 0 | M | cmpw
 165     | N | 1 | 000   | | 011 | RB    | RA!=0 | 0 | M | cmpl
 166     | N |   |  RT   | | 010 | RB    | RA    | 1 | M | mul
 167     | N |   |  RT   | | 011 | RB    | 0 0 0 | 0 | M | neg.
 168
 169 10 bit mode:
 170
 171 * sub. default CR target is CR0
 172 * for (RA|0) when RA=0 the input is a zero immediate,
 173   meaning that sub. becomes neg.
 174 * RT is implicitly RB: "add RT(=RB), RA, RB"
 175
 176 ### Logical
 177
 178     | 16-bit mode   | | 10-bit mode             |
 179     | 0 | 1 | 2 3 4 | | 567 | 8 9 a | b c d | e | f |
 180     | N | 0 |  RT   | | 100 | RB    | RA!=0 | 0 | M | and
 181     | N | 0 |  RT   | | 100 | RB    | RA!=0 | 1 | M | nand
 182     | N | 0 |  RT   | | 101 | RB    | RA!=0 | 0 | M | or
 183     | N | 0 |  RT   | | 101 | RB    | RA!=0 | 1 | M | nor
 184     | N | 0 |  RT   | | 100 | RB    | 0 0 0 | 0 | M | extsw
 185     | N | 0 |  RT   | | 100 | RB    | 0 0 0 | 1 | M | cntlz
 186     | N | 0 |  RT   | | 101 | RB    | 0 0 0 | 0 | M | popcnt
 187     | N | 0 |  RT   | | 101 | RB    | 0 0 0 | 1 | M | not
 188
 189 16-bit mode only:
 190
 191     | 0 | 1 | 2 3 4 | | 567 | 8 9 a | b c d | e | f |
 192     | N | 1 |  RT   | | 100 | RB    | RA!=0 | 0 | M |
 193     | N | 1 |  RT   | | 100 | RB    | RA!=0 | 1 | M |
 194     | N | 1 |  RT   | | 101 | RB    | RA!=0 | 0 | M |
 195     | N | 1 |  RT   | | 101 | RB    | RA!=0 | 1 | M |
 196     | N | 1 |  RT   | | 100 | RB    | 0 0 0 | 0 | M | extsb
 197     | N | 1 |  RT   | | 100 | RB    | 0 0 0 | 1 | M |
 198     | N | 1 |  RT   | | 101 | RB    | 0 0 0 | 0 | M |
 199     | N | 1 |  RT   | | 101 | RB    | 0 0 0 | 1 | M |
 200
 201 10 bit mode:
 202
 203 * for (RA|0) when RA=0 the input is a zero immediate,
 204   meaning that nor becomes not
 205 * cntlz, popcnt, exts **not available** in 10-bit mode
 206 * RT is implicitly RB: "and RT(=RB), RA, RB"
 207
 208 ### Floating Point
 209
 210 Note here that elwidth overrides (SV Prefix) can be used to select FP16/32/64
 211
 212     | 16-bit mode   | | 10-bit mode             |
 213     | 0 | 1 | 2 3 4 | | 567 | 8 9 a | b c d | e | f |
 214     | N |   |  RT   | | 011 | RB    | RA!=0 | 1 | M | fsub.
 215     | N | 0 |  RT   | | 110 | RB    | RA!=0 | 0 | M | fadd
 216     | N | 0 |  RT   | | 110 | RB    | RA!=0 | 1 | M | fmul
 217     | N | 0 |  RT   | | 011 | RB    | 0 0 0 | 1 | M | fneg.
 218     | N |   |  RT   | | 110 | RB    | 0 0 0 | 0 | M |
 219     | N |   |  RT   | | 110 | RB    | 0 0 0 | 1 | M |
 220
 221 16-bit mode only:
 222
 223     | 0 | 1 | 2 3 4 | | 567 | 8 9 a | b c d | e | f |
 224     | N | 1 |  RT   | | 011 | RB    | RA!=0 | 1 | M |
 225     | N | 1 |  RT   | | 110 | RB    | RA!=0 | 0 | M |
 226     | N | 1 |  RT   | | 110 | RB    | RA!=0 | 1 | M | fdiv
 227     | N | 1 |  RT   | | 011 | RB    | 0 0 0 | 1 | M | fabs.
 228     | N |   |  RT   | | 110 | RB    | 0 0 0 | 0 | M | fmr.
 229     | N |   |  RT   | | 110 | RB    | 0 0 0 | 1 | M |
 230
 231 10 bit mode:
 232
 233 * fsub. fneg. and fmr. default target is CR1
 234 * fmr. is **not available** in 10-bit mode
 235 * fdiv is **not available** in 10-bit mode
 236
 237 16 bit mode:
 238
 239 * fmr. copies RB to RT (and sets CR1)
 240
 241 ### Condition Register
 242
 243     | 16-bit mode   | | 10-bit mode           |
 244     | 0 1 2 3 | 4   | | 567 | 8 9 a | b c d e | f |
 245     | 0 0 0 0 | BF2 | | 000 | 1  BF | 0  BFA  | M | mcrf
 246     | 0 0 0 1 | BA2 | | 000 | 1  BA | 0  BB   | M | crnor
 247     | 0 1 0 0 | BA2 | | 000 | 1  BA | 0  BB   | M | crandc
 248     | 0 1 1 0 | BA2 | | 000 | 1  BA | 0  BB   | M | crxor
 249     | 0 1 1 1 | BA2 | | 000 | 1  BA | 0  BB   | M | crnand
 250     | 1 0 0 0 | BA2 | | 000 | 1  BA | 0  BB   | M | crand
 251     | 1 0 0 1 | BA2 | | 000 | 1  BA | 0  BB   | M | creqv
 252     | 1 1 0 1 | BA2 | | 000 | 1  BA | 0  BB   | M | crorc
 253     | 1 1 1 0 | BA2 | | 000 | 1  BA | 0  BB   | M | cror
 254
 255 10 bit mode:
 256
 257 * mcrf BF is only 2 bits which means the destination is only CR0-CR3
 258 * CR operations: **not available** in 10-bit mode
 259
 260 16 bit mode:
 261
 262 * mcrf BF2 extends BF (in MSB) to 3 bits
 263 * CR operations: destination register is same as BA.
 264 * CR operations: only possible on CR0 and CR1
 265
 266 SV (Vector Mode):
 267
 268 * CR operations: greatly extended reach/range (useful for predicates)
 269
 270 ### System
 271
 272 * cbank: Selection of Compressed-encoding "Bank".  Different "banks" give different
 273 meanings to opcodes.  Example: CBank=0b001 is heavily optimised to A/Video
 274 Encode/Decode.
 275
 276     | 16-bit mode | | 10-bit mode             |
 277     | 0 1 | 2 3 4 | | 567 | 8 9 a | b c d | e | f |
 278     |       Bank2 | | 010 | CBank | 0 0 0 | 0 | M | cbank
 279
 280 **not available** in 10-bit mode:
 281
 282     | 0 1 2 3 | 4  | | 567 | 8 9 a | b c d e  | f |
 283     | 1 1 1 1 | 0  | | 000 | 1  00 | 0  RT    | M | mtlr
 284     | 1 1 1 1 | 0  | | 000 | 1  01 | 0  RT    | M | mtctr
 285     | 1 1 1 1 | 0  | | 000 | 1  11 | 0  RT    | M | mtcr
 286     | 1 1 1 1 | 1  | | 000 | 1  00 | 0  RA    | M | mflr
 287     | 1 1 1 1 | 1  | | 000 | 1  01 | 0  RA    | M | mfctr
 288     | 1 1 1 1 | 1  | | 000 | 1  11 | 0  RA    | M | mfcr
 289
 290 ### Unallocated
 291
 292     | 0 1 2 3 | 4  | | 567 | 8 9 a | b c d e  | f |
 293     | 0 0 1 0 |    | | 000 | 1     | 0        | M |
 294     | 0 0 1 1 |    | | 000 | 1     | 0        | M |
 295     | 0 1 0 1 |    | | 000 | 1     | 0        | M |
 296     | 1 0 1 0 |    | | 000 | 1     | 0        | M |
 297     | 1 0 1 1 |    | | 000 | 1     | 0        | M |
 298     | 1 1 0 0 |    | | 000 | 1     | 0        | M |
 299     | 1 1 1 1 | 0  | | 000 | 1  10 | 0        | M |
 300     | 1 1 1 1 | 1  | | 000 | 1  10 | 0        | M |
 301