openpower/sv/16_bit_compressed.mdwn

   1 # 16 bit Compressed
   2
   3 See:
   4
   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=238>
   6 * <https://ftp.libre-soc.org/VLE_314-68105.pdf> VLE Encoding
   7
   8 This one is a conundrum.  OpenPOWER ISA was never designed with 16
   9 bit in mind.  VLE was added 10 years ago but only by way of marking
  10 an entire 64k page as "VLE".  With VLE not maintained it is not
  11 fully compatible with current PowerISA.
  12
  13 Here, in order to embed 16 bit into a predominantly 32 bit stream the
  14 overhead of using an entire 16 bits just to switch into Compressed mode
  15 is itself a significant overhead.  The situation is made worse by 5 bits
  16 being taken up by Major Opcode space, leaving only 11 bits to allocate
  17 to actual instructions.
  18
  19 In addition we would like to add SV-C32 which is a Vectorised version
  20 of 16 bit Compressed, and ideally have a variant that adds the 27-bit
  21 prefix format from SV-P64, as well.
  22
  23 Potential ways to reduce pressure on the 16 bit space are:
  24
  25 * To provide "paging".  This involves bank-switching to alternative optimised encodings for specific workloads
  26 * To enter "16 bit mode" for durations specified at the start
  27 * To reserve one bit of every 16 bit instruction to indicate that the 16 bit mode is to continue to be sustained
  28
  29 This latter would be useful in the Vector context to have an alternative
  30 meaning: as the bit which determines whether the instruction is 11-bit
  31 prefixed or 27-bit prefixed:
  32
  33     0 1 2 3 4 5 6 7 8 9 a b c d e f |
  34     |major op | 11 bit vector prefix|
  35     |16 bit opcode  alt vec. mode ^ |
  36     | extra vector prefix if alt set|
  37
  38 Using a major opcode to enter 16 bit mode, leaves 11 bits to find
  39 something to use them for:
  40
  41     0 1 2 3 4 5 6 7 8 9 a b c d e f |
  42     |major op | what to do here   1 |
  43     |16 bit    stay in 16bit mode 1 |
  44     |16 bit    stay in 16bit mode 1 |
  45     |16 bit       exit 16bit mode 0 |
  46
  47 One possibility is that the 11 bits are used for bank selection, with
  48 some room for additional context such as altering the registers used
  49 for the 16 bit operations (bank selection of which scalar regs)
  50
  51 Another is to use the 11 bits for only the utmost commonly used
  52 instructions.  That being the case then even one of those 11 bits would
  53 also need to be dedicated to saying if 16 bit mode is to be continued.
  54 10 bits remain for actual opcodes!
  55
  56 # Opcode Allocation Ideas
  57
  58 * one bit from the 16-bit mode is used to indicate that 32-bit mode
  59   is to be dropped into for only one single instruction
  60   <https://bugs.libre-soc.org/show_bug.cgi?id=238#c2>
  61
  62 ## Opcodes exploration (Attempt 1)
  63
  64 Switching between different encoding modes is controlled by M (alone)
  65 in 10-bit mode, and M and N in 16-bit mode.
  66
  67 * M in 10-bit mode if zero indicates that following instructions are
  68   standard OpenPOWER ISA 32-bit encoded (including, redundantly,
  69   further 10/16-bit instructions)
  70 * M in 10-bit mode if 1 indicates that following instructions are
  71   in 16-bit encoding mode
  72
  73 Once in 16-bit mode:
  74
  75 * 0b01 (M=1, N=0): stay in 16-bit mode
  76 * 0b00: leave 16-bit mode permanently (return to standard OpenPOWER ISA)
  77 * 0b10: leave 16-bit mode for one cycle (return to standard OpenPOWER ISA)
  78 * 0b11: free to be used for something completely different.
  79
  80 The current "top" idea for 0b11 is to use it for a new encoding format
  81 of predominantly "immediates-based" 16-bit instructions (branch-conditional,
  82 addi, mulli etc.)
  83
  84 The Compressed Major Opcode is in bits 5-7.
  85
  86 * M+N mode-switching is not available for C-Major 0b000 or 0b111
  87
  88 ### Immediate Opcodes
  89
  90 only available in 16-bit mode, and only available when M=1 and N=1
  91
  92     | 0 | 1  | 2 3 4 | | 567 | 89a  | b c | d   | e | f |
  93     | 1 | o2 |  RT   | | 010 | RB|0 | offs      | 1 | addi.
  94     | 1 | o2 |  RT   | | 011 | RB|0 | offs      | 1 | addis.
  95     | 1 | o2     | 0 | | 100 | RB   | offs      | 1 | cmpdi
  96     | 1 | o2     | 1 | | 100 | RB   | offs      | 1 | cmpwi
  97     | 1 | o2     | 0 | | 101 | RA   | offs      | 1 | ldi
  98     | 1 | o2     | 1 | | 101 | RA   | offs      | 1 | lwi
  99     | 1 | o2     | 0 | | 110 | RA   | offs      | 1 | flwi
 100     | 1 | o2     | 1 | | 110 | RA   | offs      | 1 | fldi
 101
 102 * Note that bc is included (below)
 103 * immediate is constructed from offs (LSBs) and o2 (MSB)
 104 * for loads, offset is aligned.  8byte: o2||offs||0b000 4byte: 0b00
 105 * RB|0 if RB is zero, addi. becomes "li"
 106
 107 ### Branch
 108
 109 10 bit mode may be expanded by 16 bit mode later, adding capabilities
 110 that do not fit in the extreme limited space.
 111
 112     | 16-bit mode | | 10-bit mode              |
 113     | 0 | 1 | 234 | | 567 | 8 9a | b | cd | e  | f |
 114     | N | BO3 BI3 | | 000 | 0 BI | BO     | LK | M | bclr, bclrl
 115     | N | offs2   | | 001 |   offs        | LK | M | b, bl
 116     | 1 | offs2   | | 001 | BI   | BO1 oo | LK | 1 | bc, bcl
 117
 118 16 bit mode:
 119
 120 * bc only available when N,M=0b11
 121 * offs2 extends offset in MSBs
 122 * BI3 extends BI in MSBs to allow selection of full CR
 123 * BO3 extends BO
 124 * bc offset constructed from oo as LSBs and offs2 as MSBs
 125 * bc BI allows selection of all bits from CR0 or CR1
 126 * bc CR check is always active (as if BO0=1) therefore BO1 inverts
 127
 128 10 bit mode:
 129
 130 * bc **not available** in 10-bit mode
 131 * BO[0] enables CR check, BO[1] inverts check
 132 * BI refers to CR0 only (4 bits of)
 133 * no Branch Conditional with immediate
 134 * no Absolute Address
 135 * CTR mode allowed with BO[2] for b only.
 136 * offs is to 2 byte (signed) aligned
 137 * all branches to 2 byte aligned
 138
 139 ### LD/ST
 140
 141     | 16-bit mode       | | 10-bit mode             |
 142     | 0   | 1   | 2 3 4 | | 567 | 8 9 a | b c d | e | f |
 143     | RB2 | RA2 |  RT   | | 001 | 1  RA | 1  RB | 0 | M | fld
 144     | RA2 | RT2 |  RB   | | 001 | 1  RA | 1  RT | 1 | M | fst
 145     |     |     |  RT   | | 111 |  RA   |  RB   | 0 | M | ld
 146     |     |     |  RB   | | 111 |  RA   |  RT   | 1 | M | st
 147
 148 * elwidth overrides can set different widths
 149
 150 16 bit mode:
 151
 152 * F=1 is FLD, FST
 153 * RA2 extends RA to 3 bits (MSB)
 154 * RT2 extends RT to 3 bits (MSB)
 155
 156 10 bit mode:
 157
 158 * RA and RB are only 2 bit (0-3)
 159 * for LD, RT is implicitly RB: "ld RT=RB, RA(RB)"
 160 * for ST, there is no offset: "st RT, RA(0)"
 161
 162 ### Arithmetic
 163
 164     | 16-bit mode   | | 10-bit mode             |
 165     | 0 | 1 | 2 3 4 | | 567 | 89a | b c d | e | f |
 166     | N |   |  RT   | | 010 | RB  | RA!=0 | 0 | M | add
 167     | N |   | RT!=0 | | 011 | RB  | RA!=0 | 0 | M | sub.
 168     | N | 0 | 000   | | 011 | RB  | RA!=0 | 0 | M | cmpw
 169     | N | 1 | 000   | | 011 | RB  | RA!=0 | 0 | M | cmpl
 170     | N |   |  RT   | | 010 | RB  | RA    | 1 | M | mul
 171     | N |   |  RT   | | 011 | RB  | 000   | 0 | M | neg.
 172
 173 10 bit mode:
 174
 175 * sub. default CR target is CR0
 176 * for (RA|0) when RA=0 the input is a zero immediate,
 177   meaning that sub. becomes neg.
 178 * RT is implicitly RB: "add RT(=RB), RA, RB"
 179
 180 ### Logical
 181
 182     | 16-bit mode   | | 10-bit mode             |
 183     | 0 | 1 | 2 3 4 | | 567 | 8 9 a | b c d | e | f |
 184     | N | 0 |  RT   | | 100 | RB    | RA!=0 | 0 | M | and
 185     | N | 0 |  RT   | | 100 | RB    | RA!=0 | 1 | M | nand
 186     | N | 0 |  RT   | | 101 | RB    | RA!=0 | 0 | M | or
 187     | N | 0 |  RT   | | 101 | RB    | RA!=0 | 1 | M | nor
 188     | N | 0 |  RT   | | 100 | RB    | 0 0 0 | 0 | M | extsw
 189     | N | 0 |  RT   | | 100 | RB    | 0 0 0 | 1 | M | cntlz
 190     | N | 0 |  RT   | | 101 | RB    | 0 0 0 | 0 | M | popcnt
 191     | N | 0 |  RT   | | 101 | RB    | 0 0 0 | 1 | M | not
 192
 193 16-bit mode only:
 194
 195     | 0 | 1 | 2 3 4 | | 567 | 8 9 a | b c d | e | f |
 196     | N | 1 |  RT   | | 100 | RB    | RA!=0 | 0 | M |
 197     | N | 1 |  RT   | | 100 | RB    | RA!=0 | 1 | M |
 198     | N | 1 |  RT   | | 101 | RB    | RA!=0 | 0 | M | xor
 199     | N | 1 |  RT   | | 101 | RB    | RA!=0 | 1 | M | eqv (xnor)
 200     | N | 1 |  RT   | | 100 | RB    | 0 0 0 | 0 | M | extsb
 201     | N | 1 |  RT   | | 100 | RB    | 0 0 0 | 1 | M | cnttz
 202     | N | 1 |  RT   | | 101 | RB    | 0 0 0 | 0 | M |
 203     | N | 1 |  RT   | | 101 | RB    | 0 0 0 | 1 | M | extsh
 204
 205 10 bit mode:
 206
 207 * for (RA|0) when RA=0 the input is a zero immediate,
 208   meaning that nor becomes not
 209 * cntlz, popcnt, exts **not available** in 10-bit mode
 210 * RT is implicitly RB: "and RT(=RB), RA, RB"
 211
 212 ### Floating Point
 213
 214 Note here that elwidth overrides (SV Prefix) can be used to select FP16/32/64
 215
 216     | 16-bit mode   | | 10-bit mode             |
 217     | 0 | 1 | 2 3 4 | | 567 | 8 9 a | b c d | e | f |
 218     | N |   |  RT   | | 011 | RB    | RA!=0 | 1 | M | fsub.
 219     | N | 0 |  RT   | | 110 | RB    | RA!=0 | 0 | M | fadd
 220     | N | 0 |  RT   | | 110 | RB    | RA!=0 | 1 | M | fmul
 221     | N | 0 |  RT   | | 011 | RB    | 0 0 0 | 1 | M | fneg.
 222     | N | 0 |  RT   | | 110 | RB    | 0 0 0 | 0 | M |
 223     | N | 0 |  RT   | | 110 | RB    | 0 0 0 | 1 | M |
 224
 225 16-bit mode only:
 226
 227     | 0 | 1 | 2 3 4 | | 567 | 8 9 a | b c d | e | f |
 228     | N | 1 |  RT   | | 011 | RB    | RA!=0 | 1 | M |
 229     | N | 1 |  RT   | | 110 | RB    | RA!=0 | 0 | M |
 230     | N | 1 |  RT   | | 110 | RB    | RA!=0 | 1 | M | fdiv
 231     | N | 1 |  RT   | | 011 | RB    | 0 0 0 | 1 | M | fabs.
 232     | N | 1 |  RT   | | 110 | RB    | 0 0 0 | 0 | M | fmr.
 233     | N | 1 |  RT   | | 110 | RB    | 0 0 0 | 1 | M |
 234
 235 10 bit mode:
 236
 237 * fsub. fneg. and fmr. default target is CR1
 238 * fmr. is **not available** in 10-bit mode
 239 * fdiv is **not available** in 10-bit mode
 240
 241 16 bit mode:
 242
 243 * fmr. copies RB to RT (and sets CR1)
 244
 245 ### Condition Register
 246
 247     | 16-bit mode   | | 10-bit mode           |
 248     | 0 1 2 3 | 4   | | 567 | 8 9 a | b c d e | f |
 249     | 0 0 0 0 | BF2 | | 000 | 1  BF | 0  BFA  | M | mcrf
 250     | 0 0 0 1 | BA2 | | 000 | 1  BA | 0  BB   | M | crnor
 251     | 0 1 0 0 | BA2 | | 000 | 1  BA | 0  BB   | M | crandc
 252     | 0 1 1 0 | BA2 | | 000 | 1  BA | 0  BB   | M | crxor
 253     | 0 1 1 1 | BA2 | | 000 | 1  BA | 0  BB   | M | crnand
 254     | 1 0 0 0 | BA2 | | 000 | 1  BA | 0  BB   | M | crand
 255     | 1 0 0 1 | BA2 | | 000 | 1  BA | 0  BB   | M | creqv
 256     | 1 1 0 1 | BA2 | | 000 | 1  BA | 0  BB   | M | crorc
 257     | 1 1 1 0 | BA2 | | 000 | 1  BA | 0  BB   | M | cror
 258
 259 10 bit mode:
 260
 261 * mcrf BF is only 2 bits which means the destination is only CR0-CR3
 262 * CR operations: **not available** in 10-bit mode
 263
 264 16 bit mode:
 265
 266 * mcrf BF2 extends BF (in MSB) to 3 bits
 267 * CR operations: destination register is same as BA.
 268 * CR operations: only possible on CR0 and CR1
 269
 270 SV (Vector Mode):
 271
 272 * CR operations: greatly extended reach/range (useful for predicates)
 273
 274 ### System
 275
 276 * cbank: Selection of Compressed-encoding "Bank".  Different "banks" give different
 277 meanings to opcodes.  Example: CBank=0b001 is heavily optimised to A/Video
 278 Encode/Decode.
 279
 280     | 16-bit mode | | 10-bit mode             |
 281     | 0 1 | 2 3 4 | | 567 | 8 9 a | b c d | e | f |
 282     |       Bank2 | | 010 | CBank | 0 0 0 | 0 | M | cbank
 283
 284 **not available** in 10-bit mode:
 285
 286     | 0 1 2 3 | 4  | | 567 | 8 9 a | b c d e  | f |
 287     | 1 1 1 1 | 0  | | 000 | 1  00 | 0  RT    | M | mtlr
 288     | 1 1 1 1 | 0  | | 000 | 1  01 | 0  RT    | M | mtctr
 289     | 1 1 1 1 | 0  | | 000 | 1  11 | 0  RT    | M | mtcr
 290     | 1 1 1 1 | 1  | | 000 | 1  00 | 0  RA    | M | mflr
 291     | 1 1 1 1 | 1  | | 000 | 1  01 | 0  RA    | M | mfctr
 292     | 1 1 1 1 | 1  | | 000 | 1  11 | 0  RA    | M | mfcr
 293
 294 ### Unallocated
 295
 296     | 0 1 2 3 | 4  | | 567 | 8 9 a | b c d e  | f |
 297     | 0 0 1 0 |    | | 000 | 1     | 0        | M |
 298     | 0 0 1 1 |    | | 000 | 1     | 0        | M |
 299     | 0 1 0 1 |    | | 000 | 1     | 0        | M |
 300     | 1 0 1 0 |    | | 000 | 1     | 0        | M |
 301     | 1 0 1 1 |    | | 000 | 1     | 0        | M |
 302     | 1 1 0 0 |    | | 000 | 1     | 0        | M |
 303     | 1 1 1 1 | 0  | | 000 | 1  10 | 0        | M |
 304     | 1 1 1 1 | 1  | | 000 | 1  10 | 0        | M |
 305