openpower/sv/16_bit_compressed.mdwn

   1 # 16 bit Compressed
   2
   3 See:
   4
   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=238>
   6 * <https://ftp.libre-soc.org/VLE_314-68105.pdf> VLE Encoding
   7
   8 This one is a conundrum.  OpenPOWER ISA was never designed with 16
   9 bit in mind.  VLE was added 10 years ago but only by way of marking
  10 an entire 64k page as "VLE".  With VLE not maintained it is not
  11 fully compatible with current PowerISA.
  12
  13 Here, in order to embed 16 bit into a predominantly 32 bit stream the
  14 overhead of using an entire 16 bits just to switch into Compressed mode
  15 is itself a significant overhead.  The situation is made worse by 5 bits
  16 being taken up by Major Opcode space, leaving only 11 bits to allocate
  17 to actual instructions.
  18
  19 In addition we would like to add SV-C32 which is a Vectorised version
  20 of 16 bit Compressed, and ideally have a variant that adds the 27-bit
  21 prefix format from SV-P64, as well.
  22
  23 Potential ways to reduce pressure on the 16 bit space are:
  24
  25 * To provide "paging".  This involves bank-switching to alternative optimised encodings for specific workloads
  26 * To enter "16 bit mode" for durations specified at the start
  27 * To reserve one bit of every 16 bit instruction to indicate that the 16 bit mode is to continue to be sustained
  28
  29 This latter would be useful in the Vector context to have an alternative
  30 meaning: as the bit which determines whether the instruction is 11-bit
  31 prefixed or 27-bit prefixed:
  32
  33     0 1 2 3 4 5 6 7 8 9 a b c d e f |
  34     |major op | 11 bit vector prefix|
  35     |16 bit opcode  alt vec. mode ^ |
  36     | extra vector prefix if alt set|
  37
  38 Using a major opcode to enter 16 bit mode, leaves 11 bits to find
  39 something to use them for:
  40
  41     0 1 2 3 4 5 6 7 8 9 a b c d e f |
  42     |major op | what to do here   1 |
  43     |16 bit    stay in 16bit mode 1 |
  44     |16 bit    stay in 16bit mode 1 |
  45     |16 bit       exit 16bit mode 0 |
  46
  47 One possibility is that the 11 bits are used for bank selection, with
  48 some room for additional context such as altering the registers used
  49 for the 16 bit operations (bank selection of which scalar regs)
  50
  51 Another is to use the 11 bits for only the utmost commonly used
  52 instructions.  That being the case then even one of those 11 bits would
  53 also need to be dedicated to saying if 16 bit mode is to be continued.
  54 10 bits remain for actual opcodes!
  55
  56 # Opcode Allocation Ideas
  57
  58 * one bit from the 16-bit mode is used to indicate that 32-bit mode
  59   is to be dropped into for only one single instruction
  60   <https://bugs.libre-soc.org/show_bug.cgi?id=238#c2>
  61
  62 ## Opcodes exploration (Attempt 1)
  63
  64 Switching between different encoding modes is controlled by M (alone)
  65 in 10-bit mode, and M and N in 16-bit mode.
  66
  67 * M in 10-bit mode if zero indicates that following instructions are
  68   standard OpenPOWER ISA 32-bit encoded (including, redundantly,
  69   further 10/16-bit instructions)
  70 * M in 10-bit mode if 1 indicates that following instructions are
  71   in 16-bit encoding mode
  72
  73 Once in 16-bit mode:
  74
  75 * 0b01 (M=1, N=0): stay in 16-bit mode
  76 * 0b00: leave 16-bit mode permanently (return to standard OpenPOWER ISA)
  77 * 0b10: leave 16-bit mode for one cycle (return to standard OpenPOWER ISA)
  78 * 0b11: free to be used for something completely different.
  79
  80 The current "top" idea for 0b11 is to use it for a new encoding format
  81 of predominantly "immediates-based" 16-bit instructions (branch-conditional,
  82 addi, mulli etc.)
  83
  84 The Compressed Major Opcode is in bits 5-7.
  85
  86 * M+N mode-switching is not available for C-Major 0b000 or 0b111
  87
  88 ### Immediate Opcodes
  89
  90 only available in 16-bit mode, and only available when M=1 and N=1
  91
  92     | 0 | 1  | 2 3 4 | | 567 | 8 9 a | b c d | e | f |
  93     | 1 | offs2      | | 001 | o  BI | o BO | LK | 1 | bc
  94     | 1 | o2 |  RT   | | 010 | RB    | offs      | 1 | addis
  95     | 1 | o2 |  RT   | | 011 | RB    | offs      | 1 | mulis
  96     | 1 | o2 |       | | 100 |       | offs      | 1 |
  97     | 1 | o2 |  RT   | | 101 | RA    | offs      | 1 | ldi
  98     | 1 | o2 |  RT   | | 110 | RA    | offs      | 1 | sti
  99
 100 ### Branch
 101
 102 10 bit mode may be expanded by 16 bit mode later, adding capabilities
 103 that do not fit in the extreme limited space.
 104
 105     | 16-bit mode | | 10-bit mode              |
 106     | 0 | 1 | 2 3 4 | | 567 | 8 9 a | b c d | e  | f |
 107     | BO2   | BI3   | | 000 | 0  BI | 0  BO | LK | M | bclr
 108     | BO2   | BI3   | | 000 | 0  BI | 1  BO | LK | M | bctr
 109     | N | offs2     | | 001 |    offs       | LK | M | b
 110
 111 16 bit mode:
 112
 113 * offs2 extends offset in MSBs
 114 * BI3 extends BI in MSBs to allow selection of full CR
 115 * BO2 extends BO
 116
 117 10 bit mode:
 118
 119 * BO[0] enables CR check, BO[1] inverts check
 120 * BI refers to CR0 only (4 bits of)
 121 * no Branch Conditional with immediate
 122 * no Absolute Address
 123 * no CTR mode (and no bctr)
 124 * offs is to 2 byte (signed) aligned
 125 * all branches to 2 byte aligned
 126
 127 ### LD/ST
 128
 129     | 16-bit mode       | | 10-bit mode             |
 130     | 0   | 1   | 2 3 4 | | 567 | 8 9 a | b c d | e | f |
 131     | RB2 | RA2 |  RT   | | 001 | 1  RA | 1  RB | 0 | M | fld
 132     | RA2 | RT2 |  RB   | | 001 | 1  RA | 1  RT | 1 | M | fst
 133     |     |     |  RT   | | 111 |  RA   |  RB   | 0 | M | ld
 134     |     |     |  RB   | | 111 |  RA   |  RT   | 1 | M | st
 135
 136 * elwidth overrides can set different widths
 137
 138 16 bit mode:
 139
 140 * F=1 is FLD, FST
 141 * RA2 extends RA to 3 bits (MSB)
 142 * RT2 extends RT to 3 bits (MSB)
 143
 144 10 bit mode:
 145
 146 * RA and RB are only 2 bit (0-3)
 147 * for LD, RT is implicitly RB: "ld RT=RB, RA(RB)"
 148 * for ST, there is no offset: "st RT, RA(0)"
 149
 150 ### Arithmetic
 151
 152     | 16-bit mode   | | 10-bit mode             |
 153     | 0 | 1 | 2 3 4 | | 567 | 8 9 a | b c d | e | f |
 154     | N |   |  RT   | | 010 | RB    | RA!=0 | 0 | M | add
 155     | N |   |  RT   | | 011 | RB    | RA!=0 | 0 | M | sub.
 156     | N |   |  RT   | | 010 | RB    | RA    | 1 | M | mul
 157     | N |   |  RT   | | 011 | RB    | 0 0 0 | 0 | M | neg.
 158
 159 10 bit mode:
 160
 161 * sub. default CR target is CR0
 162 * for (RA|0) when RA=0 the input is a zero immediate,
 163   meaning that sub. becomes neg.
 164 * RT is implicitly RB: "add RT(=RB), RA, RB"
 165
 166 ### Logical
 167
 168     | 16-bit mode   | | 10-bit mode             |
 169     | 0 | 1 | 2 3 4 | | 567 | 8 9 a | b c d | e | f |
 170     | N |   |  RT   | | 100 | RB    | RA!=0 | 0 | M | and
 171     | N |   |  RT   | | 100 | RB    | RA!=0 | 1 | M | nand
 172     | N |   |  RT   | | 101 | RB    | RA!=0 | 0 | M | or
 173     | N |   |  RT   | | 101 | RB    | RA!=0 | 1 | M | nor
 174     | N |   |  RT   | | 100 | RB    | 0 0 0 | 0 | M | exts
 175     | N |   |  RT   | | 100 | RB    | 0 0 0 | 1 | M | cntlz
 176     | N |   |  RT   | | 101 | RB    | 0 0 0 | 0 | M | popcnt
 177     | N |   |  RT   | | 101 | RB    | 0 0 0 | 1 | M | not
 178
 179 10 bit mode:
 180
 181 * for (RA|0) when RA=0 the input is a zero immediate,
 182   meaning that nor becomes not
 183 * cntlz, popcnt, exts **not available** in 10-bit mode
 184 * RT is implicitly RB: "and RT(=RB), RA, RB"
 185
 186 ### Floating Point
 187
 188 Note here that elwidth overrides (SV Prefix) can be used to select FP16/32/64
 189
 190     | 16-bit mode   | | 10-bit mode             |
 191     | 0 | 1 | 2 3 4 | | 567 | 8 9 a | b c d | e | f |
 192     | N |   |  RT   | | 011 | RB    | RA!=0 | 1 | M | fsub.
 193     | N | 0 |  RT   | | 110 | RB    | RA!=0 | 0 | M | fadd
 194     | N | 0 |  RT   | | 110 | RB    | RA!=0 | 1 | M | fmul
 195     | N | 0 |  RT   | | 011 | RB    | 0 0 0 | 1 | M | fneg.
 196     | N |   |  RT   | | 110 | RB    | 0 0 0 | 0 | M |
 197     | N |   |  RT   | | 110 | RB    | 0 0 0 | 1 | M |
 198
 199 16-bit mode only:
 200
 201     | 0 | 1 | 2 3 4 | | 567 | 8 9 a | b c d | e | f |
 202     | N | 1 |  RT   | | 011 | RB    | RA!=0 | 1 | M |
 203     | N | 1 |  RT   | | 110 | RB    | RA!=0 | 0 | M |
 204     | N | 1 |  RT   | | 110 | RB    | RA!=0 | 1 | M | fdiv
 205     | N | 1 |  RT   | | 011 | RB    | 0 0 0 | 1 | M | fabs.
 206     | N |   |  RT   | | 110 | RB    | 0 0 0 | 0 | M | fmr.
 207     | N |   |  RT   | | 110 | RB    | 0 0 0 | 1 | M |
 208
 209 10 bit mode:
 210
 211 * fsub. fneg. and fmr. default target is CR1
 212 * fmr. is **not available** in 10-bit mode
 213 * fdiv is **not available** in 10-bit mode
 214
 215 16 bit mode:
 216
 217 * fmr. copies RB to RT (and sets CR1)
 218
 219 ### Condition Register
 220
 221     | 16-bit mode   | | 10-bit mode           |
 222     | 0 1 2 3 | 4   | | 567 | 8 9 a | b c d e | f |
 223     | 0 0 0 0 | BF2 | | 000 | 1  BF | 0  BFA  | M | mcrf
 224     | 0 0 0 1 | BA2 | | 000 | 1  BA | 0  BB   | M | crnor
 225     | 0 1 0 0 | BA2 | | 000 | 1  BA | 0  BB   | M | crandc
 226     | 0 1 1 0 | BA2 | | 000 | 1  BA | 0  BB   | M | crxor
 227     | 0 1 1 1 | BA2 | | 000 | 1  BA | 0  BB   | M | crnand
 228     | 1 0 0 0 | BA2 | | 000 | 1  BA | 0  BB   | M | crand
 229     | 1 0 0 1 | BA2 | | 000 | 1  BA | 0  BB   | M | creqv
 230     | 1 1 0 1 | BA2 | | 000 | 1  BA | 0  BB   | M | crorc
 231     | 1 1 1 0 | BA2 | | 000 | 1  BA | 0  BB   | M | cror
 232
 233 10 bit mode:
 234
 235 * mcrf BF is only 2 bits which means the destination is only CR0-CR3
 236 * CR operations: **not available** in 10-bit mode
 237
 238 16 bit mode:
 239
 240 * mcrf BF2 extends BF (in MSB) to 3 bits
 241 * CR operations: destination register is same as BA.
 242 * CR operations: only possible on CR0 and CR1
 243
 244 SV (Vector Mode):
 245
 246 * CR operations: greatly extended reach/range (useful for predicates)
 247
 248 ### System
 249
 250 * cbank: Selection of Compressed-encoding "Bank".  Different "banks" give different
 251 meanings to opcodes.  Example: CBank=0b001 is heavily optimised to A/Video
 252 Encode/Decode.
 253
 254     | 16-bit mode | | 10-bit mode             |
 255     | 0 1 | 2 3 4 | | 567 | 8 9 a | b c d | e | f |
 256     |       Bank2 | | 010 | CBank | 0 0 0 | 0 | M | cbank
 257
 258 **not available** in 10-bit mode:
 259
 260     | 0 1 2 3 | 4  | | 567 | 8 9 a | b c d e  | f |
 261     | 1 1 1 1 | 0  | | 000 | 1  00 | 0  RT    | M | mtlr
 262     | 1 1 1 1 | 0  | | 000 | 1  01 | 0  RT    | M | mtctr
 263     | 1 1 1 1 | 0  | | 000 | 1  11 | 0  RT    | M | mtcr
 264     | 1 1 1 1 | 1  | | 000 | 1  00 | 0  RA    | M | mflr
 265     | 1 1 1 1 | 1  | | 000 | 1  01 | 0  RA    | M | mfctr
 266     | 1 1 1 1 | 1  | | 000 | 1  11 | 0  RA    | M | mfcr
 267
 268 ### Unallocated
 269
 270     | 0 1 2 3 | 4  | | 567 | 8 9 a | b c d e  | f |
 271     | 0 0 1 0 |    | | 000 | 1     | 0        | M |
 272     | 0 0 1 1 |    | | 000 | 1     | 0        | M |
 273     | 0 1 0 1 |    | | 000 | 1     | 0        | M |
 274     | 1 0 1 0 |    | | 000 | 1     | 0        | M |
 275     | 1 0 1 1 |    | | 000 | 1     | 0        | M |
 276     | 1 1 0 0 |    | | 000 | 1     | 0        | M |
 277     | 1 1 1 1 | 0  | | 000 | 1  10 | 0        | M |
 278     | 1 1 1 1 | 1  | | 000 | 1  10 | 0        | M |
 279