openpower/sv/16_bit_compressed.mdwn

   1 # 16 bit Compressed
   2
   3 See:
   4
   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=238>
   6 * <https://ftp.libre-soc.org/VLE_314-68105.pdf> VLE Encoding
   7
   8 This one is a conundrum.  OpenPOWER ISA was never designed with 16
   9 bit in mind.  VLE was added 10 years ago but only by way of marking
  10 an entire 64k page as "VLE".  With VLE not maintained it is not
  11 fully compatible with current PowerISA.
  12
  13 Here, in order to embed 16 bit into a predominantly 32 bit stream the
  14 overhead of using an entire 16 bits just to switch into Compressed mode
  15 is itself a significant overhead.  The situation is made worse by 5 bits
  16 being taken up by Major Opcode space, leaving only 11 bits to allocate
  17 to actual instructions.
  18
  19 In addition we would like to add SV-C32 which is a Vectorised version
  20 of 16 bit Compressed, and ideally have a variant that adds the 27-bit
  21 prefix format from SV-P64, as well.
  22
  23 Potential ways to reduce pressure on the 16 bit space are:
  24
  25 * To provide "paging".  This involves bank-switching to alternative optimised encodings for specific workloads
  26 * To enter "16 bit mode" for durations specified at the start
  27 * To reserve one bit of every 16 bit instruction to indicate that the 16 bit mode is to continue to be sustained
  28
  29 This latter would be useful in the Vector context to have an alternative
  30 meaning: as the bit which determines whether the instruction is 11-bit
  31 prefixed or 27-bit prefixed:
  32
  33     0 1 2 3 4 5 6 7 8 9 a b c d e f |
  34     |major op | 11 bit vector prefix|
  35     |16 bit opcode  alt vec. mode ^ |
  36     | extra vector prefix if alt set|
  37
  38 Using a major opcode to enter 16 bit mode, leaves 11 bits to find
  39 something to use them for:
  40
  41     0 1 2 3 4 5 6 7 8 9 a b c d e f |
  42     |major op | what to do here   1 |
  43     |16 bit    stay in 16bit mode 1 |
  44     |16 bit    stay in 16bit mode 1 |
  45     |16 bit       exit 16bit mode 0 |
  46
  47 One possibility is that the 11 bits are used for bank selection, with
  48 some room for additional context such as altering the registers used
  49 for the 16 bit operations (bank selection of which scalar regs)
  50
  51 Another is to use the 11 bits for only the utmost commonly used
  52 instructions.  That being the case then even one of those 11 bits would
  53 also need to be dedicated to saying if 16 bit mode is to be continued.
  54 10 bits remain for actual opcodes!
  55
  56 # Opcode Allocation Ideas
  57
  58 ## Opcodes exploration (Attempt 1)
  59
  60 ### Branch
  61
  62 10 bit mode may be expanded by 16 bit mode later, adding capabilities
  63 that do not fit in the extreme limited space.
  64
  65     | 0 1 | 2 3 4 | | 5 6 7 | 8 9 | a b | c d | e  | f |
  66     |   offs2     | | 0 0 0 |     offs        | LK | 1 | b
  67     | BO2 | BI3   | | 0 0 1 | 00  | BI  | BO  | LK | 1 | bclr
  68     | BO2 | BI3   | | 0 0 1 | 01  | BI  | BO  | LK | 1 | bctar
  69
  70 16 bit mode:
  71
  72 * offs2 extends offset in MSBs
  73 * BI3 extends BI in MSBs to allow selection of full CR
  74 * BO2 extends BO
  75
  76 10 bit mode:
  77
  78 * BO[0] enables CR check, BO[1] inverts check
  79 * BI refers to CR0 only (4 bits of)
  80 * no Branch Conditional with immediate
  81 * no Absolute Address
  82 * no CTR mode (and no bctr)
  83 * offs is to 2 byte (signed) aligned
  84 * all branches to 2 byte aligned
  85
  86 ### LD/ST
  87
  88     | 0   | 1   | 2 3 4 | | 5 6 7 | 8 9 | a b | c d | e | f |
  89     | RB2 | RA2 |  RT   | | 0 0 1 | 11  | RA  | RB  | 0 | 1 | fld
  90     | RA2 | RT2 |  RB   | | 0 0 1 | 11  | RA  | RT  | 1 | 1 | fst
  91     |     |     |  RT   | | 1 1 1 | RAB2| RA  | RB  | 0 | 1 | ld
  92     |     |     |  RB   | | 1 1 1 | RAT2| RA  | RT  | 1 | 1 | st
  93
  94 * elwidth overrides can set different widths
  95
  96 16 bit mode:
  97
  98 * F=1 is FLD, FST
  99 * RA2 extends RA to 3 bits (MSB)
 100 * RT2 extends RT to 3 bits (MSB)
 101
 102 10 bit mode:
 103
 104 * RA and RB are only 2 bit (0-3)
 105 * for LD, RT is implicitly RB: ld RT=RB, RA(RB)
 106 * for ST, there is no offset: st RT, RA(0)
 107
 108 ### Arithmetic
 109
 110     | 0 1 | 2 3 4 | | 5 6 7 | 8 9 a | b c d | e | f |
 111     |     |       | | 0 1 0 | RB    | RA    | 0 | 1 | add
 112     |     |       | | 0 1 0 | RB    | RA    | 1 | 1 | mul
 113     |     |       | | 0 1 1 | RB    | (RA|0)| 0 | 1 | sub.
 114
 115 10 bit mode:
 116
 117 * sub. default CR target is CR0
 118 * for (RA|0) when RA=0 the input is a zero immediate,
 119   meaning that sub. becomes neg.
 120
 121 ### Logical
 122
 123     | 0 1 | 2 3 4 | | 5 6 7 | 8 9 a | b c d | e | f |
 124     |     |       | | 1 0 0 | RB    | RA    | 0 | 1 | and
 125     |     |       | | 1 0 0 | RB    | RA    | 1 | 1 | nand
 126     |     |       | | 1 0 1 | RB    | RA    | 0 | 1 | or
 127     |     |       | | 1 0 1 | RB    | (RA|0)| 1 | 1 | nor
 128
 129 10 bit mode:
 130
 131 * for (RA|0) when RA=0 the input is a zero immediate,
 132   meaning that nor becomes not
 133
 134 ### Floating Point
 135
 136     | 0 1 | 2 3 4 | | 5 6 7 | 8 9 a | b c d | e | f |
 137     |     |  RT   | | 0 1 1 | RB    | (RA|0)| 1 | 1 | fsub.
 138     |     |  RT   | | 1 1 0 | RB    | RA!=0 | 0 | 1 | fadd
 139     |     |  RT   | | 1 1 0 | RB    | 0 0 0 | 0 | 1 | fabs
 140     |     |  RT   | | 1 1 0 | RB    | RA    | 1 | 1 | fmul
 141
 142 10 bit mode:
 143
 144 * fcmp default target is CR1
 145 * for (RA|0) when RA=0 the input is a zero immediate,
 146   meaning that fsub becomes fneg, and fcmp becomes fcmp-against-zero
 147
 148 ### Condition Register
 149
 150     | 0 1 2 3 | 4   | | 5 6 7 | 8 9 | a b | c d e  | f |
 151     | 0 0 0 0 | BF2 | | 0 0 1 | 10  | BF  | BFA    | 1 | mcrf
 152     | 0 0 0 1 | BA2 | | 0 0 1 | 10  | BA  | BB     | 1 | crnor
 153     | 0 1 0 0 | BA2 | | 0 0 1 | 10  | BA  | BB     | 1 | crandc
 154     | 0 1 1 0 | BA2 | | 0 0 1 | 10  | BA  | BB     | 1 | crxor
 155     | 0 1 1 1 | BA2 | | 0 0 1 | 10  | BA  | BB     | 1 | crnand
 156     | 1 0 0 0 | BA2 | | 0 0 1 | 10  | BA  | BB     | 1 | crand
 157     | 1 0 0 1 | BA2 | | 0 0 1 | 10  | BA  | BB     | 1 | creqv
 158     | 1 1 0 1 | BA2 | | 0 0 1 | 10  | BA  | BB     | 1 | crorc
 159     | 1 1 1 0 | BA2 | | 0 0 1 | 10  | BA  | BB     | 1 | cror
 160
 161 10 bit mode:
 162
 163 * mcrf BF is only 2 bits which means the destination is only CR0-CR3
 164
 165 16 bit mode:
 166
 167 * mcrf BF2 extends BF (in MSB) to 3 bits
 168 * CR operations: destination register is same as BA.
 169 * CR operations: only possible on CR0 and CR1
 170
 171 SV (Vector Mode):
 172
 173 * CR operations: greatly extended reach/range (useful for predicates)
 174