openpower/sv/av_opcodes.mdwn

   1 [[!tag standards]]
   2
   3 # Scalar OpenPOWER Audio and Video Opcodes
   4
   5 the fundamental principle of SV is a hardware for-loop. therefore the first (and in nearly 100% of cases only) place to put Vector operations is first and foremost in the *scalar* ISA.  However only by analysing those scalar opcodes *in* a SV Vectorisation context does it become clear why they are needed and how they may be designed.
   6
   7 This page therefore has accompanying discussion at <https://bugs.libre-soc.org/show_bug.cgi?id=230> for evolution of suitable opcodes.
   8
   9 Links
  10
  11 * [[vpu]]
  12 * [[sv/int_fp_mv]]
  13 * TODO review https://en.m.wikipedia.org/wiki/Multimedia_Acceleration_eXtensions
  14
  15 # Summary
  16
  17 In-advance, the summary of base scalar operations that need to be added is:
  18
  19 | instruction  | pseudocode               |
  20 | ------------ | ------------------------      |
  21 | average-add. | result = (src1 + src2 + 1) >> 1 |
  22 | abs-diff     | result = abs (src1-src2) |
  23 | signed min   | result = (src1 < src2) ? src1 : src2 use bitmanip |
  24 | signed max   | result = (src1 > src2) ? src1 : src2  use bitmanip |
  25 | bitwise sel  | (a ? b : c) - use bitmanip ternary |
  26 | int/fp move  | GPR(RT) = FPR(FRA) and FPR(FRT) = GPR(RA) |
  27
  28 All other capabilities (saturate in particular) are achieved with [[sv/svp64]] modes and swizzle.  Note that minmax and ternary are added in bitmanip.
  29
  30 # Audio
  31
  32 The fundamental principle for these instructions is:
  33
  34 * identify the scalar primitive
  35 * assume that longer runs of scalars will have Simple-V vectorisatin applied
  36 * assume that "swizzle" may be applied at the (vec2 - SUBVL=2) Vector level,
  37  (even if that involves a mv.swizxle which may be macro-op fused)
  38   in order to perform the necessary HI/LO selection normally hard-coded
  39   into SIMD ISAs.
  40
  41 Thus for example, where OpenPOWER VSX has vpkswss, this would be achieved in SV with simply:
  42
  43 * addition of a scalar ext/clamp instruction
  44 * 1st op, swizzle-selection vec2 "select X only" from source to dest:
  45   dest.X = extclamp(src.X)
  46 * 2nd op, swizzle-select vec2 "select Y only" from source to dest
  47   dest.Y = extclamp(src.Y)
  48
  49 Macro-op fusion may be used to detect that these two interleave cleanly, overlapping the vec2.X with vec2.Y to produce a single vec2.XY operation.
  50
  51 ## Scalar element operations
  52
  53 * clamping / saturation for signed and unsigned.  best done similar to FP rounding modes, i.e. with an SPR.
  54 * average-add.  result = (src1 + src2 + 1) >> 1
  55 * abs-diff: result = (src1 > src2) ? (src1-src2) : (src2-src1)
  56 * signed min/max
  57
  58 # Video
  59
  60 TODO
  61
  62 * DCT <https://users.cs.cf.ac.uk/Dave.Marshall/Multimedia/node231.html>
  63 * <https://www.nayuki.io/page/fast-discrete-cosine-transform-algorithms>
  64
  65 # VSX SIMD
  66
  67 Useful parts of VSX, and how they might map.
  68
  69 ## vpks[\*][\*]s (vec_pack*)
  70
  71 signed and unsigned, these are N-to-M (N=64/32/16, M=32/16/8) chop/clamp/sign/zero-extend operations. May be implemented by a clamped move to a smaller elwidth.
  72
  73 The other direction, vec_unpack widening ops, may need some way to tell whether to sign-extend or zero-extend.
  74
  75 *scalar extsw/b/h gives one set, mv gives another.  src elwidth override and dest elwidth override provide the pack/unpack*
  76
  77 ## vavgs\* (vec_avg)
  78
  79 signed and unsigned, 8/16/32: these are all of the form:
  80
  81     result = truncate((a + b + 1) >> 1))
  82
  83 *These do not exist in scalar ISA and would need to be added.  Essentially it is a type of post-processing involving the CA bit so could be included in the existing scalar pipeline ALU*
  84
  85 ## vabsdu\* (vec_abs)
  86
  87 unsigned 8/16/32: these are all of the form:
  88
  89     result = (src1 > src2) ? truncate(src1-src2) :
  90                              truncate(src2-src1)
  91
  92 *These do not exist in the scalar ISA and would need to be added*
  93
  94 ## vmaxs\* / vmaxu\* (and min)
  95
  96 signed and unsigned, 8/16/32: these are all of the form:
  97
  98     result = (src1 > src2) ? src1 : src2 # max
  99     result = (src1 < src2) ? src1 : src2 # min
 100
 101 *These do not exist in the scalar INTEGER ISA and would need to be added*.
 102 There are additionally no scalar FP min/max, either. These also
 103 need to be added.
 104
 105 Also it makes sense for both the integer and FP variants
 106 to have Rc=1 modes, where those modes are based on the
 107 respective cmp (or fsel / isel) behaviour. In other words,
 108 the Rc=1 setting is based on the *comparison* of the
 109 two inputs, rather than on which of the two results was
 110 returned by the min/max opcode.
 111
 112     result = (src1 > src2) ? src1 : src2 # max
 113     CR0 = CR_computr(src2-src1) # not based on result
 114
 115 ## vmerge operations
 116
 117 Their main point was to work around the odd/even multiplies. SV swizzles and mv.x should handle all cases.
 118
 119 these take two src vectors of various widths and splice them together.  the best technique to cover these is a simple straightforward predicated pair of mv operations, inverting the predicate in the second case, or, alternately, to use a pair of vec2 (SUBVL=2) swizzled operations.
 120
 121 in the swizzle case the first instruction would be destvec2.X = srcvec2.X and the second would swizzle-select Y: destvec2.Y = srcvec2.Y.  macro-op fusion in both the predicated variant and the swizzle variant would interleave the two into the same SIMD backend ALUs (or macro-op fusion identifies the patterns)
 122
 123 with twin predication the elwidth can be overridden on both src and dest such that either straight scalar mv or extsw/b/h can be used to provide the combinations of coverage needed, with only 2 actual instructions (plus vector prefixing)
 124
 125 See [[sv/mv.vec]] and [[sv/mv.swizzle]]
 126
 127 ## Float estimates
 128
 129     vec_expte - float 2^x
 130     vec_loge - float log2(x)
 131     vec_re - float 1/x
 132     vec_rsqrte - float 1/sqrt(x)
 133
 134 The spec says the max relative inaccuracy is 1/4096.
 135
 136 *In conjunction with the FPSPR "accuracy" bit These could be done by assigning meaning to the "sat mode" SVP64 bits in a FP context. 0b00 is IEEE754 FP, 0b01 is 2^12 accuracy for FP32. These can be applied to standard scalar FP ops*
 137
 138 The other alternative is to use the "single precision" FP operations on a 32-bit elwidth override.  As explained in [[sv/fcvt]] this halves the precision,
 139 operating at FP16 accuracy but storing in a FP32 format.
 140
 141 ## vec_madd(s) - FMA, multiply-add, optionally saturated
 142
 143     a * b + c
 144
 145 *Standard scalar madd*
 146
 147 ## vec_msum(s) - horizontal gather multiply-add, optionally saturated
 148
 149 This should be separated to a horizontal multiply and a horizontal add. How a horizontal operation would work in SV is TBD, how wide is it, etc.
 150
 151     a.x + a.y + a.z ...
 152     a.x * a.y * a.z ...
 153
 154 *This would realistically need to be done with a loop doing a mapreduce sequence.  I looked very early on at doing this type of operation and concluded it would be better done with a series of halvings each time, as separate instructions:  VL=16 then VL=8 then 4 then 2 and finally one scalar.  i.e. not an actual part of SV al all. An OoO multi-issue engine would be more than capable of dealing with the Dependencies.*
 155
 156 That has the issue that's it's a massive PITA to code, plus it's slow. Plus there's the "access to non-4-offset regs stalls". Even if there's no ready operation, it should be made easier and faster than a manual mapreduce loop.
 157
 158 --
 159
 160 As a mid-solution, 4-element gathers were discussed. 4 elements would also make them useful for pixel packing, not just the general vector gather. This is because OR and ADD are the same operation when bits don't overlap.
 161
 162     gather-add: d = a.x + a.y + a.z + a.w
 163     gather-mul: d = a.x * a.y * a.z * a.w
 164
 165 But can the SV loop increment the src reg # by 4? Hmm.
 166
 167 The idea then leads to the opposite operation, a 1-to-4 bit scatter instruction. Like gather, it could be implemented with a normal loop, but it's faster for certain uses.
 168
 169     bit-scatter dest, src, bits
 170
 171     bit-scatter rd, rs, 8 # assuming source and dest are 32-bit wide
 172     rd = (rs >> 0 * 8) & (2^8 - 1)
 173     rd+1 = (rs >> 1 * 8) & (2^8 - 1)
 174     rd+2 = (rs >> 2 * 8) & (2^8 - 1)
 175     rd+3 = (rs >> 3 * 8) & (2^8 - 1)
 176
 177 So at the start you have a RGBA packed pixel in one 32-bit register, at the end you have each channel separated into its own register, in the low bits, and ANDed so only the relevant bits are there.
 178
 179 ## vec_mul*
 180
 181 There should be both a same-width multiply and a widening multiply. Signed and unsigned versions. Optionally saturated.
 182
 183     u8 * u8 = u8
 184     u8 * u8 = u16
 185
 186 For 8,16,32,64, resulting in 8,16,32,64,128.
 187
 188 *All of these can be done with SV elwidth overrides, as long as the dest is no greater than 128.  SV specifically does not do 128 bit arithmetic. Instead, vec2.X mul-lo followed by vec2.Y mul-hi can be macro-op fused to get at the full 128 bit internal result.  Specifying e.g. src elwidth=8 and dest elwidth=16 will give a widening multiply*
 189
 190 ## vec_rl - rotate left
 191
 192     (a << x) | (a >> (WIDTH - x))
 193
 194 *Standard scalar rlwinm*
 195
 196 ## vec_sel - bitwise select
 197
 198     (a ? b : c)
 199
 200 *This does not exist in the scalar ISA and would need to be added*
 201
 202 Interesting operation: Tim.Forsyth's video on Larrabee they added a logical ternary lookup table op, which can cover this and more.  similar to crops 2-2 bit lookup.
 203
 204 * <http://0x80.pl/articles/avx512-ternary-functions.html>
 205 * <https://github.com/WojciechMula/ternary-logic/blob/master/py/show-function.py>
 206 * [[sv/bitmanip]]
 207
 208
 209 ## vec_splat - scatter
 210
 211 Implemented using swizzle/predicate.
 212
 213 ## vec_perm - permute
 214
 215 Implemented using swizzle, mv.x.
 216
 217 ## vec_*c[tl]z, vec_popcnt - count leading/trailing zeroes, set bits
 218
 219 Bit counts.
 220
 221     ctz - count trailing zeroes
 222     clz - count leading zeroes
 223     popcnt - count set bits
 224
 225 *These all exist in the scalar ISA*