openpower/sv/av_opcodes.mdwn

   1 [[!tag standards]]
   2
   3 # Scalar OpenPOWER Audio and Video Opcodes
   4
   5 the fundamental principle of SV is a hardware for-loop. therefore the first (and in nearly 100% of cases only) place to put Vector operations is first and foremost in the *scalar* ISA.  However only by analysing those scalar opcodes *in* a SV Vectorisation context does it become clear why they are needed and how they may be designed.
   6
   7 This page therefore has accompanying discussion at <https://bugs.libre-soc.org/show_bug.cgi?id=230> for evolution of suitable opcodes.
   8
   9 Links
  10
  11 * <https://bugs.libre-soc.org/show_bug.cgi?id=863> add pseudocode etc.
  12 * <https://bugs.libre-soc.org/show_bug.cgi?id=234> hardware implementation
  13 * [[vpu]]
  14 * [[sv/int_fp_mv]]
  15 * [[openpower/isa/av]] pseudocode
  16 * TODO review HP 1994-6 PA-RISC MAX <https://en.m.wikipedia.org/wiki/Multimedia_Acceleration_eXtensions>
  17 * <https://en.m.wikipedia.org/wiki/Sum_of_absolute_differences>
  18 * List of MMX instructions <https://cs.fit.edu/~mmahoney/cse3101/mmx.html>
  19
  20 # Summary
  21
  22 In-advance, the summary of base scalar operations that need to be added is:
  23
  24 | instruction   | pseudocode               |
  25 | ------------  | ------------------------      |
  26 | average-add.  | result = (src1 + src2 + 1) >> 1 |
  27 | abs-diff      | result = abs (src1-src2) |
  28 | abs-accumulate| result += abs (src1-src2) |
  29 | (un)signed min| result = (src1 < src2) ? src1 : src2 use bitmanip |
  30 | (un)signed max| result = (src1 > src2) ? src1 : src2  use bitmanip |
  31 | bitwise sel   | (a ? b : c) - use [[sv/bitmanip]] ternary |
  32 | int/fp move   | covered by [[sv/int_fp_mv]] |
  33
  34 Implemented at the [[openpower/isa/av]] pseudocode page.
  35
  36 All other capabilities (saturate in particular) are achieved with [[sv/svp64]] modes and swizzle.  Note that minmax and ternary are added in bitmanip.
  37
  38 # Audio
  39
  40 The fundamental principle for these instructions is:
  41
  42 * identify the scalar primitive
  43 * assume that longer runs of scalars will have Simple-V vectorisatin applied
  44 * assume that "swizzle" may be applied at the (vec2 - SUBVL=2) Vector level,
  45  (even if that involves a mv.swizxle which may be macro-op fused)
  46   in order to perform the necessary HI/LO selection normally hard-coded
  47   into SIMD ISAs.
  48
  49 Thus for example, where OpenPOWER VSX has vpkswss, this would be achieved in SV with simply:
  50
  51 * addition of a scalar ext/clamp instruction
  52 * 1st op, swizzle-selection vec2 "select X only" from source to dest:
  53   dest.X = extclamp(src.X)
  54 * 2nd op, swizzle-select vec2 "select Y only" from source to dest
  55   dest.Y = extclamp(src.Y)
  56
  57 Macro-op fusion may be used to detect that these two interleave cleanly, overlapping the vec2.X with vec2.Y to produce a single vec2.XY operation.
  58
  59 ## Scalar element operations
  60
  61 * clamping / saturation for signed and unsigned.  best done similar to FP rounding modes, i.e. with an SPR.
  62 * average-add.  result = (src1 + src2 + 1) >> 1
  63 * abs-diff: result = (src1 > src2) ? (src1-src2) : (src2-src1)
  64 * signed min/max
  65
  66 # Video
  67
  68 TODO
  69
  70 * DCT <https://users.cs.cf.ac.uk/Dave.Marshall/Multimedia/node231.html>
  71 * <https://www.nayuki.io/page/fast-discrete-cosine-transform-algorithms>
  72 * Absolute-diff Accumulation, used in Motion Estimation
  73
  74 # VSX SIMD
  75
  76 Useful parts of VSX, and how they might map.
  77
  78 ## vpks[\*][\*]s (vec_pack*)
  79
  80 signed and unsigned, these are N-to-M (N=64/32/16, M=32/16/8) chop/clamp/sign/zero-extend operations. May be implemented by a clamped move to a smaller elwidth.
  81
  82 The other direction, vec_unpack widening ops, may need some way to tell whether to sign-extend or zero-extend.
  83
  84 *scalar extsw/b/h gives one set, mv gives another.  src elwidth override and dest elwidth override provide the pack/unpack*.
  85
  86 implemented by [[sv/mv.vec]] RM Pack/Unpack mode as long as these instructions
  87 have that RM Mode.
  88
  89 ## vavgs\* (vec_avg)
  90
  91 signed and unsigned, 8/16/32: these are all of the form:
  92
  93     result = truncate((a + b + 1) >> 1))
  94
  95 *These do not exist in scalar ISA and would need to be added.  Essentially it is a type of post-processing involving the CA bit so could be included in the existing scalar pipeline ALU*
  96
  97 ## vabsdu\* (vec_abs)
  98
  99 unsigned 8/16/32: these are all of the form:
 100
 101     result = (src1 > src2) ? truncate(src1-src2) :
 102                              truncate(src2-src1)
 103
 104 *These do not exist in the scalar ISA and would need to be added*
 105
 106 ## abs-accumulate
 107
 108 signed and unsigned variants needed:
 109
 110     result += (src1 > src2) ? truncate(src1-src2) :
 111                               truncate(src2-src1)
 112
 113 *These do not exist in the scalar ISA and would need to be added*
 114
 115 ## vmaxs\* / vmaxu\* (and min)
 116
 117 signed and unsigned, 8/16/32: these are all of the form:
 118
 119     result = (src1 > src2) ? src1 : src2 # max
 120     result = (src1 < src2) ? src1 : src2 # min
 121
 122 *These do not exist in the scalar INTEGER ISA and would need to be added*.
 123 There are additionally no scalar FP min/max, either. These also
 124 need to be added.
 125
 126 Also it makes sense for both the integer and FP variants
 127 to have Rc=1 modes, where those modes are based on the
 128 respective cmp (or fsel / isel) behaviour. In other words,
 129 the Rc=1 setting is based on the *comparison* of the
 130 two inputs, rather than on which of the two results was
 131 returned by the min/max opcode.
 132
 133     result = (src1 > src2) ? src1 : src2 # max
 134     CR0 = CR_computr(src2-src1) # not based on result
 135
 136 ## vmerge operations
 137
 138 Their main point was to work around the odd/even multiplies. SV swizzles and mv.x should handle all cases.
 139
 140 these take two src vectors of various widths and splice them together.  the best technique to cover these is a simple straightforward predicated pair of mv operations, inverting the predicate in the second case, or, alternately, to use a pair of vec2 (SUBVL=2) swizzled operations.
 141
 142 in the swizzle case the first instruction would be destvec2.X = srcvec2.X and the second would swizzle-select Y: destvec2.Y = srcvec2.Y.  macro-op fusion in both the predicated variant and the swizzle variant would interleave the two into the same SIMD backend ALUs (or macro-op fusion identifies the patterns)
 143
 144 with twin predication the elwidth can be overridden on both src and dest such that either straight scalar mv or extsw/b/h can be used to provide the combinations of coverage needed, with only 2 actual instructions (plus vector prefixing)
 145
 146 See [[sv/mv.vec]] and [[sv/mv.swizzle]]
 147
 148 ## Float estimates
 149
 150     vec_expte - float 2^x
 151     vec_loge - float log2(x)
 152     vec_re - float 1/x
 153     vec_rsqrte - float 1/sqrt(x)
 154
 155 The spec says the max relative inaccuracy is 1/4096.
 156
 157 *In conjunction with the FPSPR "accuracy" bit These could be done by assigning meaning to the "sat mode" SVP64 bits in a FP context. 0b00 is IEEE754 FP, 0b01 is 2^12 accuracy for FP32. These can be applied to standard scalar FP ops*
 158
 159 The other alternative is to use the "single precision" FP operations on a 32-bit elwidth override.  As explained in [[sv/fcvt]] this halves the precision,
 160 operating at FP16 accuracy but storing in a FP32 format.
 161
 162 ## vec_madd(s) - FMA, multiply-add, optionally saturated
 163
 164     a * b + c
 165
 166 *Standard scalar madd*
 167
 168 ## vec_msum(s) - horizontal gather multiply-add, optionally saturated
 169
 170 This should be separated to a horizontal multiply and a horizontal add. How a horizontal operation would work in SV is TBD, how wide is it, etc.
 171
 172     a.x + a.y + a.z ...
 173     a.x * a.y * a.z ...
 174
 175 *This would realistically need to be done with a loop doing a mapreduce sequence.  I looked very early on at doing this type of operation and concluded it would be better done with a series of halvings each time, as separate instructions:  VL=16 then VL=8 then 4 then 2 and finally one scalar.  i.e. not an actual part of SV al all. An OoO multi-issue engine would be more than capable of dealing with the Dependencies.*
 176
 177 That has the issue that's it's a massive PITA to code, plus it's slow. Plus there's the "access to non-4-offset regs stalls". Even if there's no ready operation, it should be made easier and faster than a manual mapreduce loop.
 178
 179 --
 180
 181 As a mid-solution, 4-element gathers were discussed. 4 elements would also make them useful for pixel packing, not just the general vector gather. This is because OR and ADD are the same operation when bits don't overlap.
 182
 183     gather-add: d = a.x + a.y + a.z + a.w
 184     gather-mul: d = a.x * a.y * a.z * a.w
 185
 186 But can the SV loop increment the src reg # by 4? Hmm.
 187
 188 The idea then leads to the opposite operation, a 1-to-4 bit scatter instruction. Like gather, it could be implemented with a normal loop, but it's faster for certain uses.
 189
 190     bit-scatter dest, src, bits
 191
 192     bit-scatter rd, rs, 8 # assuming source and dest are 32-bit wide
 193     rd = (rs >> 0 * 8) & (2^8 - 1)
 194     rd+1 = (rs >> 1 * 8) & (2^8 - 1)
 195     rd+2 = (rs >> 2 * 8) & (2^8 - 1)
 196     rd+3 = (rs >> 3 * 8) & (2^8 - 1)
 197
 198 So at the start you have a RGBA packed pixel in one 32-bit register, at the end you have each channel separated into its own register, in the low bits, and ANDed so only the relevant bits are there.
 199
 200 ## vec_mul*
 201
 202 There should be both a same-width multiply and a widening multiply. Signed and unsigned versions. Optionally saturated.
 203
 204     u8 * u8 = u8
 205     u8 * u8 = u16
 206
 207 For 8,16,32,64, resulting in 8,16,32,64,128.
 208
 209 *All of these can be done with SV elwidth overrides, as long as the dest is no greater than 128.  SV specifically does not do 128 bit arithmetic. Instead, vec2.X mul-lo followed by vec2.Y mul-hi can be macro-op fused to get at the full 128 bit internal result.  Specifying e.g. src elwidth=8 and dest elwidth=16 will give a widening multiply*
 210
 211 (Now added `madded` which is twin-half 64x64->HI64/LO64 in [[sv/biginteger]])
 212
 213 ## vec_rl - rotate left
 214
 215     (a << x) | (a >> (WIDTH - x))
 216
 217 *Standard scalar rlwinm*
 218
 219 ## vec_sel - bitwise select
 220
 221     (a ? b : c)
 222
 223 *This does not exist in the scalar ISA and would need to be added*
 224
 225 Interesting operation: Tim.Forsyth's video on Larrabee they added a logical ternary lookup table op, which can cover this and more.  similar to crops 2-2 bit lookup.
 226
 227 * <http://0x80.pl/articles/avx512-ternary-functions.html>
 228 * <https://github.com/WojciechMula/ternary-logic/blob/master/py/show-function.py>
 229 * [[sv/bitmanip]]
 230
 231
 232 ## vec_splat - scatter
 233
 234 Implemented using swizzle/predicate.
 235
 236 ## vec_perm - permute
 237
 238 Implemented using swizzle, mv.x.
 239
 240 ## vec_*c[tl]z, vec_popcnt - count leading/trailing zeroes, set bits
 241
 242 Bit counts.
 243
 244     ctz - count trailing zeroes
 245     clz - count leading zeroes
 246     popcnt - count set bits
 247
 248 *These all exist in the scalar ISA*