openpower/sv/av_opcodes.mdwn

   1 [[!tag standards]]
   2
   3 # Scalar OpenPOWER Audio and Video Opcodes
   4
   5 the fundamental principle of SV is a hardware for-loop. therefore the first (and in nearly 100% of cases only) place to put Vector operations is first and foremost in the *scalar* ISA.  However only by analysing those scalar opcodes *in* a SV Vectorisation context does it become clear why they are needed and how they may be designed.
   6
   7 This page therefore has acompanying discussion at <https://bugs.libre-soc.org/show_bug.cgi?id=230> for evolution of suitable opcodes.
   8
   9 Links
  10
  11 * [[vpu]]
  12
  13 # Summary
  14
  15 In-advance, the summary of base scalar operations that need to be added is:
  16
  17 | instruction  | pseudocode               |
  18 | ------------ | ------------------------      |
  19 | average-add. | result = (src1 + src2 + 1) >> 1 |
  20 | abs-diff     | result = abs (src1-src2) |
  21 | signed min   | result = (src1 < src2) ? src1 : src2  |
  22 | signed max   | result = (src1 > src2) ? src1 : src2  |
  23 | bitwise sel  | (a ? b : c) - use bitmanip ternary |
  24
  25 All other capabilities are achieved with [[sv/svp64]] modes and swizzle.
  26
  27 # Audio
  28
  29 The fundamental principle for these instructions is:
  30
  31 * identify the scalar primitive
  32 * assume that longer runs of scalars will have Simple-V vectorisatin applied
  33 * assume that "swizzle" may be applied at the (vec2 - SUBVL=2) Vector level,
  34  (even if that involves a mv.swizxle which may be macro-op fused)
  35   in order to perform the necessary HI/LO selection normally hard-coded
  36   into SIMD ISAs.
  37
  38 Thus for example, where OpenPOWER VSX has vpkswss, this would be achieved in SV with simply:
  39
  40 * addition of a scalar ext/clamp instruction
  41 * 1st op, swizzle-selection vec2 "select X only" from source to dest:
  42   dest.X = extclamp(src.X)
  43 * 2nd op, swizzle-select vec2 "select Y only" from source to dest
  44   dest.Y = extclamp(src.Y)
  45
  46 Macro-op fusion may be used to detect that these two interleave cleanly, overlapping the vec2.X with vec2.Y to produce a single vec2.XY operation.
  47
  48 ## Scalar element operations
  49
  50 * clamping / saturation for signed and unsigned.  best done similar to FP rounding modes, i.e. with an SPR.
  51 * average-add.  result = (src1 + src2 + 1) >> 1
  52 * abs-diff: result = (src1 > src2) ? (src1-src2) : (src2-src1)
  53 * signed min/max
  54
  55 # Video
  56
  57 TODO
  58
  59 * DCT <https://users.cs.cf.ac.uk/Dave.Marshall/Multimedia/node231.html>
  60 * <https://www.nayuki.io/page/fast-discrete-cosine-transform-algorithms>
  61
  62 # VSX SIMD
  63
  64 Useful parts of VSX, and how they might map.
  65
  66 ## vpks[\*][\*]s (vec_pack*)
  67
  68 signed and unsigned, these are N-to-M (N=64/32/16, M=32/16/8) chop/clamp/sign/zero-extend operations. May be implemented by a clamped move to a smaller elwidth.
  69
  70 The other direction, vec_unpack widening ops, may need some way to tell whether to sign-extend or zero-extend.
  71
  72 *scalar extsw/b/h gives one set, mv gives another.  src elwidth override and dest rlwidth override provide the pack/unpack*
  73
  74 ## vavgs\* (vec_avg)
  75
  76 signed and unsigned, 8/16/32: these are all of the form:
  77
  78     result = truncate((a + b + 1) >> 1))
  79
  80 *These do not exist in scalar ISA and would need to be added.  Essentially it is a type of post-processing involving the CA bit so could be included in the existing scalar pipeline ALU*
  81
  82 ## vabsdu\* (vec_abs)
  83
  84 unsigned 8/16/32: these are all of the form:
  85
  86     result = (src1 > src2) ? truncate(src1-src2) :
  87                              truncate(src2-src1)
  88
  89 *These do not exist in the scalar ISA and would need to be added*
  90
  91 ## vmaxs\* / vmaxu\* (and min)
  92
  93 signed and unsigned, 8/16/32: these are all of the form:
  94
  95     result = (src1 > src2) ? src1 : src2 # max
  96     result = (src1 < src2) ? src1 : src2 # min
  97
  98 *These do not exist in the scalar INTEGER ISA and would need to be added*
  99
 100 ## vmerge operations
 101
 102 Their main point was to work around the odd/even multiplies. SV swizzles and mv.x should handle all cases.
 103
 104 these take two src vectors of various widths and splice them together.  the best technique to cover these is a simple straightforward predicated pair of mv operations, inverting the predicate in the second case, or, alternately, to use a pair of vec2 (SUBVL=2) swizzled operations.
 105
 106 in the swizzle case the first instruction would be destvec2.X = srcvec2.X and the second would swizzle-select Y: destvec2.Y = srcvec2.Y.  macro-op fusion in both the predicated variant and the swizzle variant would interleave the two into the same SIMD backend ALUs (or macro-op fusion identifies the patterns)
 107
 108 with twin predication the elwidth can be overridden on both src and dest such that either straight scalar mv or extsw/b/h can be used to provide the combinations of coverage needed, with only 2 actual instructions (plus vector prefixing)
 109
 110 See [[sv/mv.vec]] and [[sv/mv.swizzle]]
 111
 112 ## Float estimates
 113
 114     vec_expte - float 2^x
 115     vec_loge - float log2(x)
 116     vec_re - float 1/x
 117     vec_rsqrte - float 1/sqrt(x)
 118
 119 The spec says the max relative inaccuracy is 1/4096.
 120
 121 *In conjunction with the FPSPR "accuracy" bit These could be done by assigning meaning to the "sat mode" SVP64 bits in a FP context. 0b00 is IEEE754 FP, 0b01 is 2^12 accuracy for FP32. These can be applied to standard scalar FP ops*
 122
 123 The other alternative is to use the "single precision" FP operations on a 32-bit elwidth override.  As explained in [[sv/fcvt]] this halves the precision,
 124 operating at FP16 accuracy but storing in a FP32 format.
 125
 126 ## vec_madd(s) - FMA, multiply-add, optionally saturated
 127
 128     a * b + c
 129
 130 *Standard scalar madd*
 131
 132 ## vec_msum(s) - horizontal gather multiply-add, optionally saturated
 133
 134 This should be separated to a horizontal multiply and a horizontal add. How a horizontal operation would work in SV is TBD, how wide is it, etc.
 135
 136     a.x + a.y + a.z ...
 137     a.x * a.y * a.z ...
 138
 139 *This would realistically need to be done with a loop doing a mapreduce sequence.  I looked very early on at doing this type of operation and concluded it would be better done with a series of halvings each time, as separate instructions:  VL=16 then VL=8 then 4 then 2 and finally one scalar.  i.e. not an actual part of SV al all. An OoO multi-issue engine would be more than capable of dealing with the Dependencies.*
 140
 141 That has the issue that's it's a massive PITA to code, plus it's slow. Plus there's the "access to non-4-offset regs stalls". Even if there's no ready operation, it should be made easier and faster than a manual mapreduce loop.
 142
 143 --
 144
 145 As a mid-solution, 4-element gathers were discussed. 4 elements would also make them useful for pixel packing, not just the general vector gather. This is because OR and ADD are the same operation when bits don't overlap.
 146
 147     gather-add: d = a.x + a.y + a.z + a.w
 148     gather-mul: d = a.x * a.y * a.z * a.w
 149
 150 But can the SV loop increment the src reg # by 4? Hmm.
 151
 152 The idea then leads to the opposite operation, a 1-to-4 bit scatter instruction. Like gather, it could be implemented with a normal loop, but it's faster for certain uses.
 153
 154     bit-scatter dest, src, bits
 155
 156     bit-scatter rd, rs, 8 # assuming source and dest are 32-bit wide
 157     rd = (rs >> 0 * 8) & (2^8 - 1)
 158     rd+1 = (rs >> 1 * 8) & (2^8 - 1)
 159     rd+2 = (rs >> 2 * 8) & (2^8 - 1)
 160     rd+3 = (rs >> 3 * 8) & (2^8 - 1)
 161
 162 So at the start you have a RGBA packed pixel in one 32-bit register, at the end you have each channel separated into its own register, in the low bits, and ANDed so only the relevant bits are there.
 163
 164 ## vec_mul*
 165
 166 There should be both a same-width multiply and a widening multiply. Signed and unsigned versions. Optionally saturated.
 167
 168     u8 * u8 = u8
 169     u8 * u8 = u16
 170
 171 For 8,16,32,64, resulting in 8,16,32,64,128.
 172
 173 *All of these can be done with SV elwidth overrides, as long as the dest is no greater than 128.  SV specifically does not do 128 bit arithmetic. Instead, vec2.X mul-lo followed by vec2.Y mul-hi can be macro-op fused to get at the full 128 bit internal result.  Specifying e.g. src elwidth=8 and dest elwidth=16 will give a widening multiply*
 174
 175 ## vec_rl - rotate left
 176
 177     (a << x) | (a >> (WIDTH - x))
 178
 179 *Standard scalar rlwinm*
 180
 181 ## vec_sel - bitwise select
 182
 183     (a ? b : c)
 184
 185 *This does not exist in the scalar ISA and would need to be added*
 186
 187 Interesting operation: Tim.Forsyth's video on Larrabee they added a logical ternary lookup table op, which can cover this and more.  similar to crops 2-2 bit lookup.
 188
 189 * <http://0x80.pl/articles/avx512-ternary-functions.html>
 190 * <https://github.com/WojciechMula/ternary-logic/blob/master/py/show-function.py>
 191 * [[sv/bitmanip]]
 192
 193
 194 ## vec_splat - scatter
 195
 196 Implemented using swizzle/predicate.
 197
 198 ## vec_perm - permute
 199
 200 Implemented using swizzle, mv.x.
 201
 202 ## vec_*c[tl]z, vec_popcnt - count leading/trailing zeroes, set bits
 203
 204 Bit counts.
 205
 206     ctz - count trailing zeroes
 207     clz - count leading zeroes
 208     popcnt - count set bits
 209
 210 *These all exist in the scalar ISA*