openpower/sv/av_opcodes.mdwn

   1 [[!tag standards]]
   2
   3 # Scalar OpenPOWER Audio and Video Opcodes
   4
   5 the fundamental principle of SV is a hardware for-loop. therefore the first (and in nearly 100% of cases only) place to put Vector operations is first and foremost in the *scalar* ISA.  However only by analysing those scalar opcodes *in* a SV Vectorisation context does it become clear why they are needed and how they may be designed.
   6
   7 This page therefore has acompanying discussion at <https://bugs.libre-soc.org/show_bug.cgi?id=230> for evolution of suitable opcodes.
   8
   9 Links
  10
  11 * [[vpu]]
  12
  13 # Audio
  14
  15 The fundamental principle for these instructions is:
  16
  17 * identify the scalar primitive
  18 * assume that longer runs of scalars will have Simple-V vectorisatin applied
  19 * assume that "swizzle" may be applied at the (vec2 - SUBVL=2) Vector level,
  20  (even if that involves a mv.swizxle which may be macro-op fused)
  21   in order to perform the necessary HI/LO selection normally hard-coded
  22   into SIMD ISAs.
  23
  24 Thus for example, where OpenPOWER VSX has vpkswss, this would be achieved in SV with simply:
  25
  26 * addition of a scalar ext/clamp instruction
  27 * 1st op, swizzle-selection vec2 "select X only" from source to dest:
  28   dest.X = extclamp(src.X)
  29 * 2nd op, swizzle-select vec2 "select Y only" from source to dest
  30   dest.Y = extclamp(src.Y)
  31
  32 Macro-op fusion may be used to detect that these two interleave cleanly, overlapping the vec2.X with vec2.Y to produce a single vec2.XY operation.
  33
  34 ## Scalar element operations
  35
  36 * clamping / saturation for signed and unsigned.  best done similar to FP rounding modes, i.e. with an SPR.
  37 * average-add.  result = (src1 + src2 + 1) >> 1
  38 * abs-diff: result = (src1 > src2) ? (src1-src2) : (src2-src1)
  39 * signed min/max
  40
  41 # Video
  42
  43 TODO
  44
  45 * DCT <https://users.cs.cf.ac.uk/Dave.Marshall/Multimedia/node231.html>
  46 * <https://www.nayuki.io/page/fast-discrete-cosine-transform-algorithms>
  47
  48 # VSX SIMD
  49
  50 Useful parts of VSX, and how they might map.
  51
  52 ## vpks[\*][\*]s (vec_pack*)
  53
  54 signed and unsigned, these are N-to-M (N=64/32/16, M=32/16/8) chop/clamp/sign/zero-extend operations. May be implemented by a clamped move to a smaller elwidth.
  55
  56 The other direction, vec_unpack widening ops, may need some way to tell whether to sign-extend or zero-extend.
  57
  58 *scalar extsw/b/h gives one set, mv gives another.  src elwidth override and dest rlwidth override provide the pack/unpack*
  59
  60 ## vavgs\* (vec_avg)
  61
  62 signed and unsigned, 8/16/32: these are all of the form:
  63
  64     result = truncate((a + b + 1) >> 1))
  65
  66 *These do not exist in scalar ISA and would need to be added.  Essentially it is a type of post-processing involving the CA bit so could be included in the existing scalar pipeline ALU*
  67
  68 ## vabsdu\* (vec_abs)
  69
  70 unsigned 8/16/32: these are all of the form:
  71
  72     result = (src1 > src2) ? truncate(src1-src2) :
  73                              truncate(src2-src1)
  74
  75 *These do not exist in the scalar ISA and would need to be added*
  76
  77 ## vmaxs\* / vmaxu\* (and min)
  78
  79 signed and unsigned, 8/16/32: these are all of the form:
  80
  81     result = (src1 > src2) ? src1 : src2 # max
  82     result = (src1 < src2) ? src1 : src2 # min
  83
  84 *These do not exist in the scalar INTEGER ISA and would need to be added*
  85
  86 ## vmerge operations
  87
  88 Their main point was to work around the odd/even multiplies. SV swizzles and mv.x should handle all cases.
  89
  90 these take two src vectors of various widths and splice them together.  the best technique to cover these is a simple straightforward predicated pair of mv operations, inverting the predicate in the second case, or, alternately, to use a pair of vec2 (SUBVL=2) swizzled operations.
  91
  92 in the swizzle case the first instruction would be destvec2.X = srcvec2.X and the second would swizzle-select Y: destvec2.Y = srcvec2.Y.  macro-op fusion in both the predicated variant and the swizzle variant would interleave the two into the same SIMD backend ALUs (or macro-op fusion identifies the patterns)
  93
  94 with twin predication the elwidth can be overridden on both src and dest such that either straight scalar mv or extsw/b/h can be used to provide the combinations of coverage needed, with only 2 actual instructions (plus vector prefixing)
  95
  96 See [[sv/mv.vec]] and [[sv/mv.swizzle]]
  97
  98 ## Float estimates
  99
 100     vec_expte - float 2^x
 101     vec_loge - float log2(x)
 102     vec_re - float 1/x
 103     vec_rsqrte - float 1/sqrt(x)
 104
 105 The spec says the max relative inaccuracy is 1/4096.
 106
 107 *In conjunction with the FPSPR "accuracy" bit These could be done by assigning meaning to the "sat mode" SVP64 bits in a FP context. 0b00 is IEEE754 FP, 0b01 is 2^12 accuracy for FP32. These can be applied to standard scalar FP ops*
 108
 109 The other alternative is to use the "single precision" FP operations on a 32-bit elwidth override.  As explained in [[sv/]] this halves the precision.
 110
 111 ## vec_madd(s) - FMA, multiply-add, optionally saturated
 112
 113     a * b + c
 114
 115 *Standard scalar madd*
 116
 117 ## vec_msum(s) - horizontal gather multiply-add, optionally saturated
 118
 119 This should be separated to a horizontal multiply and a horizontal add. How a horizontal operation would work in SV is TBD, how wide is it, etc.
 120
 121     a.x + a.y + a.z ...
 122     a.x * a.y * a.z ...
 123
 124 *This would realistically need to be done with a loop doing a mapreduce sequence.  I looked very early on at doing this type of operation and concluded it would be better done with a series of halvings each time, as separate instructions:  VL=16 then VL=8 then 4 then 2 and finally one scalar.  i.e. not an actual part of SV al all. An OoO multi-issue engine would be more than capable of dealing with the Dependencies.*
 125
 126 That has the issue that's it's a massive PITA to code, plus it's slow. Plus there's the "access to non-4-offset regs stalls". Even if there's no ready operation, it should be made easier and faster than a manual mapreduce loop.
 127
 128 --
 129
 130 As a mid-solution, 4-element gathers were discussed. 4 elements would also make them useful for pixel packing, not just the general vector gather. This is because OR and ADD are the same operation when bits don't overlap.
 131
 132     gather-add: d = a.x + a.y + a.z + a.w
 133     gather-mul: d = a.x * a.y * a.z * a.w
 134
 135 But can the SV loop increment the src reg # by 4? Hmm.
 136
 137 The idea then leads to the opposite operation, a 1-to-4 bit scatter instruction. Like gather, it could be implemented with a normal loop, but it's faster for certain uses.
 138
 139     bit-scatter dest, src, bits
 140
 141     bit-scatter rd, rs, 8 # assuming source and dest are 32-bit wide
 142     rd = (rs >> 0 * 8) & (2^8 - 1)
 143     rd+1 = (rs >> 1 * 8) & (2^8 - 1)
 144     rd+2 = (rs >> 2 * 8) & (2^8 - 1)
 145     rd+3 = (rs >> 3 * 8) & (2^8 - 1)
 146
 147 So at the start you have a RGBA packed pixel in one 32-bit register, at the end you have each channel separated into its own register, in the low bits, and ANDed so only the relevant bits are there.
 148
 149 ## vec_mul*
 150
 151 There should be both a same-width multiply and a widening multiply. Signed and unsigned versions. Optionally saturated.
 152
 153     u8 * u8 = u8
 154     u8 * u8 = u16
 155
 156 For 8,16,32,64, resulting in 8,16,32,64,128.
 157
 158 *All of these can be done with SV elwidth overrides, as long as the dest is no greater than 128.  SV specifically does not do 128 bit arithmetic. Instead, vec2.X mul-lo followed by vec2.Y mul-hi can be macro-op fused to get at the full 128 bit internal result.  Specifying e.g. src elwidth=8 and dest elwidth=16 will give a widening multiply*
 159
 160 ## vec_rl - rotate left
 161
 162     (a << x) | (a >> (WIDTH - x))
 163
 164 *Standard scalar rlwinm*
 165
 166 ## vec_sel - bitwise select
 167
 168     (a ? b : c)
 169
 170 *This does not exist in the scalar ISA and would need to be added*
 171
 172 Interesting operation: Tim.Forsyth's video on Larrabee they added a logical ternary lookup table op, which can cover this and more.  similar to crops 2-2 bit lookup.
 173
 174 * <http://0x80.pl/articles/avx512-ternary-functions.html>
 175 * <https://github.com/WojciechMula/ternary-logic/blob/master/py/show-function.py>
 176 * [[sv/bitmanip]]
 177
 178
 179 ## vec_splat - scatter
 180
 181 Implemented using swizzle/predicate.
 182
 183 ## vec_perm - permute
 184
 185 Implemented using swizzle, mv.x.
 186
 187 ## vec_*c[tl]z, vec_popcnt - count leading/trailing zeroes, set bits
 188
 189 Bit counts.
 190
 191     ctz - count trailing zeroes
 192     clz - count leading zeroes
 193     popcnt - count set bits
 194
 195 *These all exist in the scalar ISA*