openpower/sv/av_opcodes.mdwn

   1 [[!tag standards]]
   2
   3 # Scalar OpenPOWER Audio and Video Opcodes
   4
   5 the fundamental principle of SV is a hardware for-loop. therefore the first (and in nearly 100% of cases only) place to put Vector operations is first and foremost in the *scalar* ISA.  However only by analysing those scalar opcodes *in* a SV Vectorisation context does it become clear why they are needed and how they may be designed.
   6
   7 This page therefore has accompanying discussion at <https://bugs.libre-soc.org/show_bug.cgi?id=230> for evolution of suitable opcodes.
   8
   9 Links
  10
  11 * [[vpu]]
  12 * [[sv/int_fp_mv]]
  13 * TODO review <https://en.m.wikipedia.org/wiki/Multimedia_Acceleration_eXtensions>
  14 * <https://en.m.wikipedia.org/wiki/Sum_of_absolute_differences>
  15
  16 # Summary
  17
  18 In-advance, the summary of base scalar operations that need to be added is:
  19
  20 | instruction  | pseudocode               |
  21 | ------------ | ------------------------      |
  22 | average-add. | result = (src1 + src2 + 1) >> 1 |
  23 | abs-diff     | result = abs (src1-src2) |
  24 | abs-accumulate| result += abs (src1, src2) |
  25 | signed min   | result = (src1 < src2) ? src1 : src2 use bitmanip |
  26 | signed max   | result = (src1 > src2) ? src1 : src2  use bitmanip |
  27 | bitwise sel  | (a ? b : c) - use bitmanip ternary |
  28 | int/fp move  | GPR(RT) = FPR(FRA) and FPR(FRT) = GPR(RA) |
  29
  30 All other capabilities (saturate in particular) are achieved with [[sv/svp64]] modes and swizzle.  Note that minmax and ternary are added in bitmanip.
  31
  32 # Audio
  33
  34 The fundamental principle for these instructions is:
  35
  36 * identify the scalar primitive
  37 * assume that longer runs of scalars will have Simple-V vectorisatin applied
  38 * assume that "swizzle" may be applied at the (vec2 - SUBVL=2) Vector level,
  39  (even if that involves a mv.swizxle which may be macro-op fused)
  40   in order to perform the necessary HI/LO selection normally hard-coded
  41   into SIMD ISAs.
  42
  43 Thus for example, where OpenPOWER VSX has vpkswss, this would be achieved in SV with simply:
  44
  45 * addition of a scalar ext/clamp instruction
  46 * 1st op, swizzle-selection vec2 "select X only" from source to dest:
  47   dest.X = extclamp(src.X)
  48 * 2nd op, swizzle-select vec2 "select Y only" from source to dest
  49   dest.Y = extclamp(src.Y)
  50
  51 Macro-op fusion may be used to detect that these two interleave cleanly, overlapping the vec2.X with vec2.Y to produce a single vec2.XY operation.
  52
  53 ## Scalar element operations
  54
  55 * clamping / saturation for signed and unsigned.  best done similar to FP rounding modes, i.e. with an SPR.
  56 * average-add.  result = (src1 + src2 + 1) >> 1
  57 * abs-diff: result = (src1 > src2) ? (src1-src2) : (src2-src1)
  58 * signed min/max
  59
  60 # Video
  61
  62 TODO
  63
  64 * DCT <https://users.cs.cf.ac.uk/Dave.Marshall/Multimedia/node231.html>
  65 * <https://www.nayuki.io/page/fast-discrete-cosine-transform-algorithms>
  66 * Absolute-diff Accumulation, used in Motion Estimation
  67
  68 # VSX SIMD
  69
  70 Useful parts of VSX, and how they might map.
  71
  72 ## vpks[\*][\*]s (vec_pack*)
  73
  74 signed and unsigned, these are N-to-M (N=64/32/16, M=32/16/8) chop/clamp/sign/zero-extend operations. May be implemented by a clamped move to a smaller elwidth.
  75
  76 The other direction, vec_unpack widening ops, may need some way to tell whether to sign-extend or zero-extend.
  77
  78 *scalar extsw/b/h gives one set, mv gives another.  src elwidth override and dest elwidth override provide the pack/unpack*
  79
  80 ## vavgs\* (vec_avg)
  81
  82 signed and unsigned, 8/16/32: these are all of the form:
  83
  84     result = truncate((a + b + 1) >> 1))
  85
  86 *These do not exist in scalar ISA and would need to be added.  Essentially it is a type of post-processing involving the CA bit so could be included in the existing scalar pipeline ALU*
  87
  88 ## vabsdu\* (vec_abs)
  89
  90 unsigned 8/16/32: these are all of the form:
  91
  92     result = (src1 > src2) ? truncate(src1-src2) :
  93                              truncate(src2-src1)
  94
  95 *These do not exist in the scalar ISA and would need to be added*
  96
  97 ## abs-accumulate
  98
  99 signed and unsigned variants needed:
 100
 101     result += (src1 > src2) ? truncate(src1-src2) :
 102                               truncate(src2-src1)
 103
 104 *These do not exist in the scalar ISA and would need to be added*
 105
 106 ## vmaxs\* / vmaxu\* (and min)
 107
 108 signed and unsigned, 8/16/32: these are all of the form:
 109
 110     result = (src1 > src2) ? src1 : src2 # max
 111     result = (src1 < src2) ? src1 : src2 # min
 112
 113 *These do not exist in the scalar INTEGER ISA and would need to be added*.
 114 There are additionally no scalar FP min/max, either. These also
 115 need to be added.
 116
 117 Also it makes sense for both the integer and FP variants
 118 to have Rc=1 modes, where those modes are based on the
 119 respective cmp (or fsel / isel) behaviour. In other words,
 120 the Rc=1 setting is based on the *comparison* of the
 121 two inputs, rather than on which of the two results was
 122 returned by the min/max opcode.
 123
 124     result = (src1 > src2) ? src1 : src2 # max
 125     CR0 = CR_computr(src2-src1) # not based on result
 126
 127 ## vmerge operations
 128
 129 Their main point was to work around the odd/even multiplies. SV swizzles and mv.x should handle all cases.
 130
 131 these take two src vectors of various widths and splice them together.  the best technique to cover these is a simple straightforward predicated pair of mv operations, inverting the predicate in the second case, or, alternately, to use a pair of vec2 (SUBVL=2) swizzled operations.
 132
 133 in the swizzle case the first instruction would be destvec2.X = srcvec2.X and the second would swizzle-select Y: destvec2.Y = srcvec2.Y.  macro-op fusion in both the predicated variant and the swizzle variant would interleave the two into the same SIMD backend ALUs (or macro-op fusion identifies the patterns)
 134
 135 with twin predication the elwidth can be overridden on both src and dest such that either straight scalar mv or extsw/b/h can be used to provide the combinations of coverage needed, with only 2 actual instructions (plus vector prefixing)
 136
 137 See [[sv/mv.vec]] and [[sv/mv.swizzle]]
 138
 139 ## Float estimates
 140
 141     vec_expte - float 2^x
 142     vec_loge - float log2(x)
 143     vec_re - float 1/x
 144     vec_rsqrte - float 1/sqrt(x)
 145
 146 The spec says the max relative inaccuracy is 1/4096.
 147
 148 *In conjunction with the FPSPR "accuracy" bit These could be done by assigning meaning to the "sat mode" SVP64 bits in a FP context. 0b00 is IEEE754 FP, 0b01 is 2^12 accuracy for FP32. These can be applied to standard scalar FP ops*
 149
 150 The other alternative is to use the "single precision" FP operations on a 32-bit elwidth override.  As explained in [[sv/fcvt]] this halves the precision,
 151 operating at FP16 accuracy but storing in a FP32 format.
 152
 153 ## vec_madd(s) - FMA, multiply-add, optionally saturated
 154
 155     a * b + c
 156
 157 *Standard scalar madd*
 158
 159 ## vec_msum(s) - horizontal gather multiply-add, optionally saturated
 160
 161 This should be separated to a horizontal multiply and a horizontal add. How a horizontal operation would work in SV is TBD, how wide is it, etc.
 162
 163     a.x + a.y + a.z ...
 164     a.x * a.y * a.z ...
 165
 166 *This would realistically need to be done with a loop doing a mapreduce sequence.  I looked very early on at doing this type of operation and concluded it would be better done with a series of halvings each time, as separate instructions:  VL=16 then VL=8 then 4 then 2 and finally one scalar.  i.e. not an actual part of SV al all. An OoO multi-issue engine would be more than capable of dealing with the Dependencies.*
 167
 168 That has the issue that's it's a massive PITA to code, plus it's slow. Plus there's the "access to non-4-offset regs stalls". Even if there's no ready operation, it should be made easier and faster than a manual mapreduce loop.
 169
 170 --
 171
 172 As a mid-solution, 4-element gathers were discussed. 4 elements would also make them useful for pixel packing, not just the general vector gather. This is because OR and ADD are the same operation when bits don't overlap.
 173
 174     gather-add: d = a.x + a.y + a.z + a.w
 175     gather-mul: d = a.x * a.y * a.z * a.w
 176
 177 But can the SV loop increment the src reg # by 4? Hmm.
 178
 179 The idea then leads to the opposite operation, a 1-to-4 bit scatter instruction. Like gather, it could be implemented with a normal loop, but it's faster for certain uses.
 180
 181     bit-scatter dest, src, bits
 182
 183     bit-scatter rd, rs, 8 # assuming source and dest are 32-bit wide
 184     rd = (rs >> 0 * 8) & (2^8 - 1)
 185     rd+1 = (rs >> 1 * 8) & (2^8 - 1)
 186     rd+2 = (rs >> 2 * 8) & (2^8 - 1)
 187     rd+3 = (rs >> 3 * 8) & (2^8 - 1)
 188
 189 So at the start you have a RGBA packed pixel in one 32-bit register, at the end you have each channel separated into its own register, in the low bits, and ANDed so only the relevant bits are there.
 190
 191 ## vec_mul*
 192
 193 There should be both a same-width multiply and a widening multiply. Signed and unsigned versions. Optionally saturated.
 194
 195     u8 * u8 = u8
 196     u8 * u8 = u16
 197
 198 For 8,16,32,64, resulting in 8,16,32,64,128.
 199
 200 *All of these can be done with SV elwidth overrides, as long as the dest is no greater than 128.  SV specifically does not do 128 bit arithmetic. Instead, vec2.X mul-lo followed by vec2.Y mul-hi can be macro-op fused to get at the full 128 bit internal result.  Specifying e.g. src elwidth=8 and dest elwidth=16 will give a widening multiply*
 201
 202 (Now added `madded` which is twin-half 64x64->HI64/LO64 in [[sv/biginteger]])
 203
 204 ## vec_rl - rotate left
 205
 206     (a << x) | (a >> (WIDTH - x))
 207
 208 *Standard scalar rlwinm*
 209
 210 ## vec_sel - bitwise select
 211
 212     (a ? b : c)
 213
 214 *This does not exist in the scalar ISA and would need to be added*
 215
 216 Interesting operation: Tim.Forsyth's video on Larrabee they added a logical ternary lookup table op, which can cover this and more.  similar to crops 2-2 bit lookup.
 217
 218 * <http://0x80.pl/articles/avx512-ternary-functions.html>
 219 * <https://github.com/WojciechMula/ternary-logic/blob/master/py/show-function.py>
 220 * [[sv/bitmanip]]
 221
 222
 223 ## vec_splat - scatter
 224
 225 Implemented using swizzle/predicate.
 226
 227 ## vec_perm - permute
 228
 229 Implemented using swizzle, mv.x.
 230
 231 ## vec_*c[tl]z, vec_popcnt - count leading/trailing zeroes, set bits
 232
 233 Bit counts.
 234
 235     ctz - count trailing zeroes
 236     clz - count leading zeroes
 237     popcnt - count set bits
 238
 239 *These all exist in the scalar ISA*