openpower/sv/biginteger.mdwn

   1 [[!tag standards]]
   2
   3 # Big Integer Arithmetic
   4
   5 **DRAFT STATUS** 19apr2021
   6
   7 (see [[discussion]] page for notes)
   8
   9 BigNum arithmetic is extremely common especially in cryptography,
  10 where for example RSA relies on arithmetic of 2048 or 4096 bits
  11 in length.  The primary operations are add, multiply and divide
  12 (and modulo) with specialisations of subtract and signed multiply.
  13
  14 A reminder that a particular focus of SVP64 is that it is built on
  15 top of Scalar operations, where those scalar operations are useful in
  16 their own right without SVP64. Thus the operations here are proposed
  17 first as Scalar Extensions to the Power ISA.
  18
  19 A secondary focus is that if Vectorised, implementors may choose
  20 to deploy macro-op fusion targetting back-end 256-bit or greater
  21 Dynamic SIMD ALUs for maximum performance and effectiveness.
  22
  23 # Analysis
  24
  25 Covered in [[biginteger/analysis]] the summary is that standard `adde`
  26 is sufficient for SVP64 Vectorisation of big-integer addition (and subfe
  27 for subtraction) but that big-integer multiply and divide require an
  28 extra 3-in 2-out instruction, similar to Intel's `mulx`, to be efficient.
  29 The same instruction (`madded`) is used for both because 'madded''s primary
  30 purpose is to perform a fused 64-bit scalar multiply with a large vector,
  31 where that result is Big-Added for Big-Multiply, but Big-Subtracted for
  32 Big-Divide.
  33
  34 Macro-op Fusion and back-end massively-wide SIMD ALUs may be deployed in a
  35 fashion that is hidden from the user, behind a consistent, stable ISA API.
  36
  37 # Instructions
  38
  39 **DRAFT**
  40
  41 `madded` is VA-Form:
  42
  43 |0.....5|6..10|11..15|16..20|21..25|26..31|
  44 |-------|-----|------|------|------|------|
  45 | EXT04 | RT  |  RA  |  RB  |   RC |  XO  |
  46
  47 For the Opcode map (XO Field)
  48 see Power ISA v3.1, Book III, Appendix D, Table 13 (sheet 7 of 8), p1357.
  49 Proposed is the addition of `msubed` (**DRAFT, NOT APPROVED**) which is
  50 in `110110`.  A corresponding `madded` is proposed for `110010`
  51
  52 | 110000 | 110001  | 110010 | 110011 | 110100 | 110101 | 110110 | 110111 |
  53 | ------ | ------- | ------ | ------ | ------ | ------ | ------ | ------ |
  54 | maddhd | maddhdu | madded | maddld | rsvd   | rsvd   | rsvd   | rsvd   |
  55
  56 For SVP64 EXTRA register extension, the `RM-1P-3S-1D` format is
  57 used with the additional bit set for determining RS.
  58
  59 | Field Name | Field bits | Description                            |
  60 |------------|------------|----------------------------------------|
  61 | Rdest\_EXTRA2 | `10:11` | extends RT (R\*\_EXTRA2 Encoding)   |
  62 | Rsrc1\_EXTRA2 | `12:13` | extends RA (R\*\_EXTRA2 Encoding)   |
  63 | Rsrc2\_EXTRA2 | `14:15` | extends RB (R\*\_EXTRA2 Encoding)   |
  64 | Rsrc3\_EXTRA2 | `16:17` | extends RC (R\*\_EXTRA2 Encoding)   |
  65 | EXTRA2_MODE   | `18`    | used by `msubed` and `madded` for RS   |
  66
  67 When `EXTRA2_MODE` is set to zero, the implicit RS register takes
  68 its Vector/Scalar setting from Rdest_EXTRA2, and takes
  69 the register number from RT, but all numbering
  70 is offset by VL. *Note that element-width overrides influence this
  71 offset* (see SVP64 [[svp64/appendix]] for full details).
  72
  73 When `EXTRA2_MODE` is set to one, the implicit RS register is identical
  74 to RC extended to SVP64 numbering, including whether RC is set Scalar or
  75 Vector.
  76
  77 ## madded
  78
  79 The pseudocode for `madded RT, RA, RB, RC` is:
  80
  81     prod[0:127] = (RA) * (RB)
  82     sum[0:127] = EXTZ(RC) + prod
  83     RT <- sum[64:127]
  84     RS <- sum[0:63] # RS is either RC or RT+VL
  85
  86 Again RC is zero-extended (not shifted), the 128-bit product added
  87 to it; the lower half of the result stored in RT and the upper half
  88 in RS.
  89
  90 The differences here to `maddhdu` are that `maddhdu` stores the upper
  91 half in RT, where `madded` stores the upper half in RS. There is no
  92 equivalent to `maddld` because `maddld` performs sign-extension on RC.
  93