7 * ternlogi <https://bugs.libre-soc.org/show_bug.cgi?id=745>
8 * grev <https://bugs.libre-soc.org/show_bug.cgi?id=755>
9 * GF2^M <https://bugs.libre-soc.org/show_bug.cgi?id=782>
10 * binutils <https://bugs.libre-soc.org/show_bug.cgi?id=836>
11 * shift-and-add <https://bugs.libre-soc.org/show_bug.cgi?id=968>
17 pseudocode: [[openpower/isa/bitmanip]]
19 this extension amalgamates bitmanipulation primitives from many sources,
20 including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX.
21 Also included are DSP/Multimedia operations suitable for Audio/Video.
22 Vectorization and SIMD are removed: these are straight scalar (element)
23 operations making them suitable for embedded applications. Vectorization
24 Context is provided by [[openpower/sv]].
26 When combined with SV, scalar variants of bitmanip operations found in
27 VSX are added so that the Packed SIMD aspects of VSX may be retired as
28 "legacy" in the far future (10 to 20 years). Also, VSX is hundreds of
29 opcodes, requires 128 bit pathways, and is wholly unsuited to low power
30 or embedded scenarios.
32 ternlogv is experimental and is the only operation that may be considered
33 a "Packed SIMD". It is added as a variant of the already well-justified
34 ternlog operation (done in AVX512 as an immediate only) "because it
35 looks fun". As it is based on the LUT4 concept it will allow accelerated
36 emulation of FPGAs. Other vendors of ISAs are buying FPGA companies to
37 achieve similar objectives.
39 general-purpose Galois Field 2^M operations are added so as to avoid
40 huge custom opcode proliferation across many areas of Computer Science.
41 however for convenience and also to avoid setup costs, some of the more
42 common operations (clmul, crc32) are also added. The expectation is
43 that these operations would all be covered by the same pipeline.
45 note that there are brownfield spaces below that could incorporate
46 some of the set-before-first and other scalar operations listed in
48 [[sv/vector_ops]], [[sv/int_fp_mv]] and the [[sv/av_opcodes]] as well as
49 [[sv/setvl]], [[sv/svstep]], [[sv/remap]]
53 * <https://en.wikiversity.org/wiki/Reed%E2%80%93Solomon_codes_for_coders>
54 * <https://maths-people.anu.edu.au/~brent/pd/rpb232tr.pdf>
55 * <https://gist.github.com/animetosho/d3ca95da2131b5813e16b5bb1b137ca0>
56 * <https://github.com/HJLebbink/asm-dude/wiki/GF2P8AFFINEINVQB>
58 [[!inline pages="openpower/sv/draft_opcode_tables" quick="yes" raw="yes" ]]
60 # binary and ternary bitops
62 Similar to FPGA LUTs: for two (binary) or three (ternary) inputs take
63 bits from each input, concatenate them and perform a lookup into a
64 table using an 8-8-bit immediate (for the ternary instructions), or in
65 another register (4-bit for the binary instructions). The binary lookup
66 instructions have CR Field lookup variants due to CR Fields being 4 bit.
69 [vpternlogd/vpternlogq](https://www.felixcloutier.com/x86/vpternlogd:vpternlogq)
74 | 0.5|6.10|11.15|16.20| 21..28|29.30|31|
75 | -- | -- | --- | --- | ----- | --- |--|
76 | NN | RT | RA | RB | im0-7 | 00 |Rc|
79 idx = c << 2 | b << 1 | a
80 return imm[idx] # idx by LSB0 order
83 RT[i] = lut3(imm, RB[i], RA[i], RT[i])
87 Binary lookup is a dynamic LUT2 version of ternlogi. Firstly, the
88 lookup table is 4 bits wide not 8 bits, and secondly the lookup
89 table comes from a register not an immediate.
91 | 0.5|6.10|11.15|16.20| 21..25|26..31 | Form |
92 | -- | -- | --- | --- | ----- |--------|---------|
93 | NN | RT | RA | RB | RC |nh 00001| VA-Form |
94 | NN | RT | RA | RB | /BFA/ |0 01001| VA-Form |
96 For binlut, the 4-bit LUT may be selected from either the high nibble
97 or the low nibble of the first byte of RC:
101 return imm[idx] # idx by LSB0 order
103 imm = (RC>>(nh*4))&0b1111
105 RT[i] = lut2(imm, RB[i], RA[i])
107 For bincrlut, `BFA` selects the 4-bit CR Field as the LUT2:
110 RT[i] = lut2(CRs{BFA}, RB[i], RA[i])
112 When Vectorized with SVP64, as usual both source and destination may be
115 *Programmer's note: a dynamic ternary lookup may be synthesised from
116 a pair of `binlut` instructions followed by a `ternlogi` to select which
117 to merge. Use `nh` to select which nibble to use as the lookup table
118 from the RC source register (`nh=1` nibble high), i.e. keeping
119 an 8-bit LUT3 in RC, the first `binlut` instruction may set nh=0 and
124 another mode selection would be CRs not Ints.
128 | 0.5|6.8 |9.10|11.13|14.15|16.18|19.25|26.30| 31|
129 |----|----|----|-----|-----|-----|-----|-----|---|
130 | NN | BF | msk|BFA | msk | BFB | TLI | XO |TLI|
133 a,b,c = CRs[BF][i], CRs[BFA][i], CRs[BFB][i])
134 if msk[i] CRs[BF][i] = lut3(imm, a, b, c)
136 This instruction is remarkably similar to the existing crops, `crand` etc.
137 which have been noted to be a 4-bit (binary) LUT. In effect `crternlogi`
138 is the ternary LUT version of crops, having an 8-bit LUT. However it
139 is an overwrite instruction in order to save on register file ports,
140 due to the mask requiring the contents of the BF to be both read and
143 Programmer's note: This instruction is useful when combined with Matrix REMAP
144 in "Inner Product" Mode, creating Warshall Transitive Closure that has many
145 applications in Computer Science.
149 With ternary (LUT3) dynamic instructions being very costly,
150 and CR Fields being only 4 bit, a binary (LUT2) variant is better
154 | 0.5|6.8 |9.10|11.13|14.15|16.18|19.25|26.30| 31|
155 |----|----|----|-----|-----|-----|-----|-----|---|
156 | NN | BF | msk|BFA | msk | BFB | // | XO | //|
159 a,b = CRs[BF][i], CRs[BF][i])
160 if msk[i] CRs[BF][i] = lut2(CRs[BFB], a, b)
162 When SVP64 Vectorized any of the 4 operands may be Scalar or
163 Vector, including `BFB` meaning that multiple different dynamic
164 lookups may be performed with a single instruction. Note that
165 this instruction is deliberately an overwrite in order to reduce
166 the number of register file ports required: like `crternlogi`
167 the contents of `BF` **must** be read due to the mask only
168 writing back to non-masked-out bits of `BF`.
170 *Programmer's note: just as with binlut and ternlogi, a pair
171 of crbinlog instructions followed by a merging crternlogi may
172 be deployed to synthesise dynamic ternary (LUT3) CR Field
179 required for the [[sv/av_opcodes]]
181 signed and unsigned min/max for integer.
183 signed/unsigned min/max gives more flexibility.
185 \[un]signed min/max instructions are specifically needed for vector reduce min/max operations which are pretty common.
189 * PO=19, XO=----000011 `minmax RT, RA, RB, MMM`
190 * PO=19, XO=----000011 `minmax. RT, RA, RB, MMM`
192 see [[openpower/sv/rfc/ls013]] for `MMM` definition and pseudo-code.
194 implements all of (and more):
197 uint_xlen_t mins(uint_xlen_t rs1, uint_xlen_t rs2)
198 { return (int_xlen_t)rs1 < (int_xlen_t)rs2 ? rs1 : rs2;
200 uint_xlen_t maxs(uint_xlen_t rs1, uint_xlen_t rs2)
201 { return (int_xlen_t)rs1 > (int_xlen_t)rs2 ? rs1 : rs2;
203 uint_xlen_t minu(uint_xlen_t rs1, uint_xlen_t rs2)
204 { return rs1 < rs2 ? rs1 : rs2;
206 uint_xlen_t maxu(uint_xlen_t rs1, uint_xlen_t rs2)
207 { return rs1 > rs2 ? rs1 : rs2;
213 required for the [[sv/av_opcodes]], these exist in Packed SIMD (VSX)
217 uint_xlen_t intavg(uint_xlen_t rs1, uint_xlen_t rs2) {
218 return (rs1 + rs2 + 1) >> 1:
224 required for the [[sv/av_opcodes]], these exist in Packed SIMD (VSX)
228 uint_xlen_t absdu(uint_xlen_t rs1, uint_xlen_t rs2) {
229 return (src1 > src2) ? (src1-src2) : (src2-src1)
235 required for the [[sv/av_opcodes]], these are needed for motion estimation.
236 both are overwrite on RS.
239 uint_xlen_t uintabsacc(uint_xlen_t rs, uint_xlen_t ra, uint_xlen_t rb) {
240 return rs + (src1 > src2) ? (src1-src2) : (src2-src1)
242 uint_xlen_t intabsacc(uint_xlen_t rs, int_xlen_t ra, int_xlen_t rb) {
243 return rs + (src1 > src2) ? (src1-src2) : (src2-src1)
247 For SVP64, the twin Elwidths allows e.g. a 16 bit accumulator for 8 bit
248 differences. Form is `RM-1P-3S1D` where RS-as-source has a separate
249 SVP64 designation from RS-as-dest. This gives a limited range of
250 non-overwrite capability.
252 # shift-and-add <a name="shift-add"> </a>
254 Power ISA is missing LD/ST with shift, which is present in both ARM and x86.
255 Too complex to add more LD/ST, a compromise is to add shift-and-add.
256 Replaces a pair of explicit instructions in hot-loops.
260 |0 |6 |11 |15 |16 |21 |23 |31 |
261 | PO | RT | RA | RB |sm | XO |Rc |
268 RT <- (n[m:XLEN-1] || [0]*m) + (RA)
270 Pseudo-code (shaddw):
272 shift <- sm + 1 # Shift is between 1-4
273 n <- EXTS((RB)[XLEN/2:XLEN-1]) # Only use lower XLEN/2-bits of RB
274 RT <- (n << shift) + (RA) # Shift n, add RA
276 Pseudo-code (shadduw):
278 n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
280 RT <- (n[m:XLEN-1] || [0]*m) + (RA)
283 uint_xlen_t shadd(uint_xlen_t RA, uint_xlen_t RB, uint8_t sm) {
285 return (RB << (sm+1)) + RA;
288 uint_xlen_t shaddw(uint_xlen_t RA, uint_xlen_t RB, uint8_t sm) {
289 uint_xlen_t n = (int_xlen_t)(RB << XLEN / 2) >> XLEN / 2;
291 return (n << (sm+1)) + RA;
294 uint_xlen_t shadduw(uint_xlen_t RA, uint_xlen_t RB, uint8_t sm) {
295 uint_xlen_t n = RB & 0xFFFFFFFF;
297 return (n << (sm+1)) + RA;
303 based on RV bitmanip singlebit set, instruction format similar to shift
304 [[isa/fixedshift]]. bmext is actually covered already (shift-with-mask
305 rldicl but only immediate version). however bitmask-invert is not,
306 and set/clr are not covered, although they can use the same Shift ALU.
308 bmext (RB) version is not the same as rldicl because bmext is a right
309 shift by RC, where rldicl is a left rotate. for the immediate version
310 this does not matter, so a bmexti is not required. bmrev however there
311 is no direct equivalent and consequently a bmrevi is required.
313 bmset (register for mask amount) is particularly useful for creating
314 predicate masks where the length is a dynamic runtime quantity.
315 bmset(RA=0, RB=0, RC=mask) will produce a run of ones of length "mask"
316 in a single instruction without needing to initialise or depend on any
319 | 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name |
320 | -- | -- | --- | --- | --- | ------- |--| ----- |
321 | NN | RS | RA | RB | RC | mode 010 |Rc| bm\* |
323 Immediate-variant is an overwrite form:
325 | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name |
326 | -- | -- | --- | --- | -- | ----- | -------- |--| ---- |
327 | NN | RS | RB | sh | SH | itype | 1000 110 |Rc| bm\*i |
333 mask_a = ((1 << x) - 1) & ((1 << 64) - 1)
334 mask_b = ((1 << y) - 1) & ((1 << 64) - 1)
339 mask_a = ((1 << x) - 1) & ((1 << 64) - 1)
340 mask_b = (~((1 << y) - 1)) & ((1 << 64) - 1)
341 return mask_a ^ mask_b
344 uint_xlen_t bmset(RS, RB, sh)
346 int shamt = RB & (XLEN - 1);
348 return RS | (mask << shamt);
351 uint_xlen_t bmclr(RS, RB, sh)
353 int shamt = RB & (XLEN - 1);
355 return RS & ~(mask << shamt);
358 uint_xlen_t bminv(RS, RB, sh)
360 int shamt = RB & (XLEN - 1);
362 return RS ^ (mask << shamt);
365 uint_xlen_t bmext(RS, RB, sh)
367 int shamt = RB & (XLEN - 1);
369 return mask & (RS >> shamt);
373 bitmask extract with reverse. can be done by bit-order-inverting all
374 of RB and getting bits of RB from the opposite end.
376 when RA is zero, no shift occurs. this makes bmextrev useful for
377 simply reversing all bits of a register.
381 rev[0:msb] = rb[msb:0];
384 uint_xlen_t bmrevi(RA, RB, sh)
387 if (RA != 0) shamt = (GPR(RA) & (XLEN - 1));
388 shamt = (XLEN-1)-shamt; # shift other end
389 brb = bitreverse(GPR(RB)) # swap LSB-MSB
391 return mask & (brb >> shamt);
394 uint_xlen_t bmrev(RA, RB, RC) {
395 return bmrevi(RA, RB, GPR(RC) & 0b111111);
399 | 0.5|6.10|11.15|16.20|21.26| 27..30 |31| name | Form |
400 | -- | -- | --- | --- | --- | ------- |--| ------ | -------- |
401 | NN | RT | RA | RB | sh | 1111 |Rc| bmrevi | MDS-Form |
403 | 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name | Form |
404 | -- | -- | --- | --- | --- | ------- |--| ------ | -------- |
405 | NN | RT | RA | RB | RC | 11110 |Rc| bmrev | VA2-Form |
407 # grevlut <a name="grevlut"> </a>
409 generalised reverse combined with a pair of LUT2s and allowing
410 a constant `0b0101...0101` when RA=0, and an option to invert
411 (including when RA=0, giving a constant 0b1010...1010 as the
412 initial value) provides a wide range of instructions
413 and a means to set hundreds of regular 64 bit patterns with one
414 single 32 bit instruction.
416 the two LUT2s are applied left-half (when not swapping)
417 and right-half (when swapping) so as to allow a wider
420 <img src="/openpower/sv/grevlut2x2.jpg" width=700 />
422 * A value of `0b11001010` for the immediate provides
423 the functionality of a standard "grev".
424 * `0b11101110` provides gorc
426 grevlut should be arranged so as to produce the constants
427 needed to put into bext (bitextract) so as in turn to
428 be able to emulate x86 pmovmask instructions
429 <https://www.felixcloutier.com/x86/pmovmskb>.
430 This only requires 2 instructions (grevlut, bext).
432 Note that if the mask is required to be placed
433 directly into CR Fields (for use as CR Predicate
434 masks rather than a integer mask) then sv.cmpi or sv.ori
435 may be used instead, bearing in mind that sv.ori
436 is a 64-bit instruction, and `VL` must have been
437 set to the required length:
439 sv.ori./elwid=8 r10.v, r10.v, 0
441 The following settings provide the required mask constants:
443 | RA=0 | RB | imm | iv | result |
444 | ------- | ------- | ---------- | -- | ---------- |
445 | 0x555.. | 0b10 | 0b01101100 | 0 | 0x111111... |
446 | 0x555.. | 0b110 | 0b01101100 | 0 | 0x010101... |
447 | 0x555.. | 0b1110 | 0b01101100 | 0 | 0x00010001... |
448 | 0x555.. | 0b10 | 0b11000110 | 1 | 0x88888... |
449 | 0x555.. | 0b110 | 0b11000110 | 1 | 0x808080... |
450 | 0x555.. | 0b1110 | 0b11000110 | 1 | 0x80008000... |
452 Better diagram showing the correct ordering of shamt (RB). A LUT2
453 is applied to all locations marked in red using the first 4
454 bits of the immediate, and a separate LUT2 applied to all
455 locations in green using the upper 4 bits of the immediate.
457 <img src="/openpower/sv/grevlut.png" width=700 />
459 demo code [[openpower/sv/grevlut.py]]
464 return (imm>>idx) & 1
466 def dorow(imm8, step_i, chunk_size):
469 if (j&chunk_size) == 0:
470 imm = (imm8 & 0b1111)
474 b = (step_i>>(j ^ chunk_size))&1
475 res = lut2(imm, a, b)
476 #print(j, bin(imm), a, b, res)
478 #print (" ", chunk_size, bin(step_o))
481 def grevlut64(RA, RB, imm, iv):
483 if RA is None: # RA=0
484 x = 0x5555555555555555
492 x = dorow(imm, x, step)
493 return x & ((1<<64)-1)
496 A variant may specify different LUT-pairs per row,
497 using one byte of RB for each. If it is desired that
498 a particular row-crossover shall not be applied it is
499 a simple matter to set the appropriate LUT-pair in RB
500 to effect an identity transform for that row (`0b11001010`).
503 uint64_t grevlutr(uint64_t RA, uint64_t RB, bool iv, bool is32b)
505 uint64_t x = 0x5555_5555_5555_5555;
506 if (RA != 0) x = GPR(RA);
508 for i in 0 to (6-is32b)
510 imm = (RB>>(i*8))&0xff
511 x = dorow(imm, x, step, is32b)
517 | 0.5|6.10|11.15|16.20 |21..28 | 29.30|31| name | Form |
518 | -- | -- | --- | --- | ----- | -----|--| ------ | ----- |
519 | NN | RT | RA | s0-4 | im0-7 | 1 iv |s5| grevlogi | |
520 | NN | RT | RA | RB | im0-7 | 01 |0 | grevlog | |
522 An equivalent to `grevlogw` may be synthesised by setting the
523 appropriate bits in RB to set the top half of RT to zero.
524 Thus an explicit grevlogw instruction is not necessary.
528 based on RV bitmanip.
530 RA contains a vector of indices to select parts of RB to be
531 copied to RT. The immediate-variant allows up to an 8 bit
532 pattern (repeated) to be targetted at different parts of RT.
534 xperm shares some similarity with one of the uses of bmator
535 in that xperm indices are binary addressing where bitmator
536 may be considered to be unary addressing.
539 uint_xlen_t xpermi(uint8_t imm8, uint_xlen_t RB, int sz_log2)
542 uint_xlen_t sz = 1LL << sz_log2;
543 uint_xlen_t mask = (1LL << sz) - 1;
544 uint_xlen_t RA = imm8 | imm8<<8 | ... | imm8<<56;
545 for (int i = 0; i < XLEN; i += sz) {
546 uint_xlen_t pos = ((RA >> i) & mask) << sz_log2;
548 r |= ((RB >> pos) & mask) << i;
552 uint_xlen_t xperm(uint_xlen_t RA, uint_xlen_t RB, int sz_log2)
555 uint_xlen_t sz = 1LL << sz_log2;
556 uint_xlen_t mask = (1LL << sz) - 1;
557 for (int i = 0; i < XLEN; i += sz) {
558 uint_xlen_t pos = ((RA >> i) & mask) << sz_log2;
560 r |= ((RB >> pos) & mask) << i;
564 uint_xlen_t xperm_n (uint_xlen_t RA, uint_xlen_t RB)
565 { return xperm(RA, RB, 2); }
566 uint_xlen_t xperm_b (uint_xlen_t RA, uint_xlen_t RB)
567 { return xperm(RA, RB, 3); }
568 uint_xlen_t xperm_h (uint_xlen_t RA, uint_xlen_t RB)
569 { return xperm(RA, RB, 4); }
570 uint_xlen_t xperm_w (uint_xlen_t RA, uint_xlen_t RB)
571 { return xperm(RA, RB, 5); }
576 bmatflip and bmatxor is found in the Cray XMT, and in x86 is known
577 as GF2P8AFFINEQB. uses:
579 * <https://gist.github.com/animetosho/d3ca95da2131b5813e16b5bb1b137ca0>
580 * SM4, Reed Solomon, RAID6
581 <https://stackoverflow.com/questions/59124720/what-are-the-avx-512-galois-field-related-instructions-for>
582 * Vector bit-reverse <https://reviews.llvm.org/D91515?id=305411>
583 * Affine Inverse <https://github.com/HJLebbink/asm-dude/wiki/GF2P8AFFINEINVQB>
585 | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name | Form |
586 | -- | -- | --- | --- | -- | ----- | -------- |--| ---- | ------- |
587 | NN | RS | RA |im04 | im5| 1 1 | im67 00 110 |Rc| bmatxori | TODO |
591 uint64_t bmatflip(uint64_t RA)
600 uint64_t bmatxori(uint64_t RS, uint64_t RA, uint8_t imm) {
602 uint64_t RAt = bmatflip(RA);
603 uint8_t u[8]; // rows of RS
604 uint8_t v[8]; // cols of RA
605 for (int i = 0; i < 8; i++) {
610 for (int i = 0; i < 64; i++) {
611 bit = (imm >> (i%8)) & 1;
612 bit ^= pcnt(u[i / 8] & v[i % 8]) & 1;
618 uint64_t bmatxor(uint64_t RA, uint64_t RB) {
619 return bmatxori(RA, RB, 0xff)
622 uint64_t bmator(uint64_t RA, uint64_t RB) {
624 uint64_t RBt = bmatflip(RB);
625 uint8_t u[8]; // rows of RA
626 uint8_t v[8]; // cols of RB
627 for (int i = 0; i < 8; i++) {
632 for (int i = 0; i < 64; i++) {
633 if ((u[i / 8] & v[i % 8]) != 0)
639 uint64_t bmatand(uint64_t RA, uint64_t RB) {
641 uint64_t RBt = bmatflip(RB);
642 uint8_t u[8]; // rows of RA
643 uint8_t v[8]; // cols of RB
644 for (int i = 0; i < 8; i++) {
649 for (int i = 0; i < 64; i++) {
650 if ((u[i / 8] & v[i % 8]) == 0xff)
657 # Introduction to Carry-less and GF arithmetic
659 * obligatory xkcd <https://xkcd.com/2595/>
661 There are three completely separate types of Galois-Field-based arithmetic
662 that we implement which are not well explained even in introductory
663 literature. A slightly oversimplified explanation is followed by more
664 accurate descriptions:
666 * `GF(2)` carry-less binary arithmetic. this is not actually a Galois Field,
667 but is accidentally referred to as GF(2) - see below as to why.
668 * `GF(p)` modulo arithmetic with a Prime number, these are "proper"
670 * `GF(2^N)` carry-less binary arithmetic with two limits: modulo a power-of-2
671 (2^N) and a second "reducing" polynomial (similar to a prime number), these
672 are said to be GF(2^N) arithmetic.
674 further detailed and more precise explanations are provided below
676 * **Polynomials with coefficients in `GF(2)`**
677 (aka. Carry-less arithmetic -- the `cl*` instructions).
678 This isn't actually a Galois Field, but its coefficients are. This is
679 basically binary integer addition, subtraction, and multiplication like
680 usual, except that carries aren't propagated at all, effectively turning
681 both addition and subtraction into the bitwise xor operation. Division and
682 remainder are defined to match how addition and multiplication works.
683 * **Galois Fields with a prime size**
684 (aka. `GF(p)` or Prime Galois Fields -- the `gfp*` instructions).
685 This is basically just the integers mod `p`.
686 * **Galois Fields with a power-of-a-prime size**
687 (aka. `GF(p^n)` or `GF(q)` where `q == p^n` for prime `p` and
689 We only implement these for `p == 2`, called Binary Galois Fields
690 (`GF(2^n)` -- the `gfb*` instructions).
691 For any prime `p`, `GF(p^n)` is implemented as polynomials with
692 coefficients in `GF(p)` and degree `< n`, where the polynomials are the
693 remainders of dividing by a specificly chosen polynomial in `GF(p)` called
694 the Reducing Polynomial (we will denote that by `red_poly`). The Reducing
695 Polynomial must be an irreducable polynomial (like primes, but for
696 polynomials), as well as have degree `n`. All `GF(p^n)` for the same `p`
697 and `n` are isomorphic to each other -- the choice of `red_poly` doesn't
698 affect `GF(p^n)`'s mathematical shape, all that changes is the specific
699 polynomials used to implement `GF(p^n)`.
701 Many implementations and much of the literature do not make a clear
702 distinction between these three categories, which makes it confusing
703 to understand what their purpose and value is.
705 * carry-less multiply is extremely common and is used for the ubiquitous
706 CRC32 algorithm. [TODO add many others, helps justify to ISA WG]
707 * GF(2^N) forms the basis of Rijndael (the current AES standard) and
708 has significant uses throughout cryptography
709 * GF(p) is the basis again of a significant quantity of algorithms
710 (TODO, list them, jacob knows what they are), even though the
711 modulo is limited to be below 64-bit (size of a scalar int)
713 # Instructions for Carry-less Operations
715 aka. Polynomials with coefficients in `GF(2)`
717 Carry-less addition/subtraction is simply XOR, so a `cladd`
718 instruction is not provided since the `xor[i]` instruction can be used instead.
720 These are operations on polynomials with coefficients in `GF(2)`, with the
721 polynomial's coefficients packed into integers with the following algorithm:
724 [[!inline pagenames="gf_reference/pack_poly.py" raw="yes"]]
727 ## Carry-less Multiply Instructions
730 see <https://en.wikipedia.org/wiki/CLMUL_instruction_set> and
731 <https://www.felixcloutier.com/x86/pclmulqdq> and
732 <https://en.m.wikipedia.org/wiki/Carry-less_product>
734 They are worth adding as their own non-overwrite operations
735 (in the same pipeline).
737 ### `clmul` Carry-less Multiply
740 [[!inline pagenames="gf_reference/clmul.py" raw="yes"]]
743 ### `clmulh` Carry-less Multiply High
746 [[!inline pagenames="gf_reference/clmulh.py" raw="yes"]]
749 ### `clmulr` Carry-less Multiply (Reversed)
751 Useful for CRCs. Equivalent to bit-reversing the result of `clmul` on
755 [[!inline pagenames="gf_reference/clmulr.py" raw="yes"]]
758 ## `clmadd` Carry-less Multiply-Add
761 clmadd RT, RA, RB, RC
765 (RT) = clmul((RA), (RB)) ^ (RC)
768 ## `cltmadd` Twin Carry-less Multiply-Add (for FFTs)
770 Used in combination with SV FFT REMAP to perform a full Discrete Fourier
771 Transform of Polynomials over GF(2) in-place. Possible by having 3-in 2-out,
772 to avoid the need for a temp register. RS is written to as well as RT.
774 Note: Polynomials over GF(2) are a Ring rather than a Field, so, because the
775 definition of the Inverse Discrete Fourier Transform involves calculating a
776 multiplicative inverse, which may not exist in every Ring, therefore the
777 Inverse Discrete Fourier Transform may not exist. (AFAICT the number of inputs
778 to the IDFT must be odd for the IDFT to be defined for Polynomials over GF(2).
779 TODO: check with someone who knows for sure if that's correct.)
782 cltmadd RT, RA, RB, RC
785 TODO: add link to explanation for where `RS` comes from.
790 # read all inputs before writing to any outputs in case
791 # an input overlaps with an output register.
792 (RT) = clmul(a, (RB)) ^ c
796 ## `cldivrem` Carry-less Division and Remainder
798 `cldivrem` isn't an actual instruction, but is just used in the pseudo-code
799 for other instructions.
802 [[!inline pagenames="gf_reference/cldivrem.py" raw="yes"]]
805 ## `cldiv` Carry-less Division
814 q, r = cldivrem(n, d, width=XLEN)
818 ## `clrem` Carry-less Remainder
827 q, r = cldivrem(n, d, width=XLEN)
831 # Instructions for Binary Galois Fields `GF(2^m)`
835 * <https://courses.csail.mit.edu/6.857/2016/files/ffield.py>
836 * <https://engineering.purdue.edu/kak/compsec/NewLectures/Lecture7.pdf>
837 * <https://foss.heptapod.net/math/libgf2/-/blob/branch/default/src/libgf2/gf2.py>
839 Binary Galois Field addition/subtraction is simply XOR, so a `gfbadd`
840 instruction is not provided since the `xor[i]` instruction can be used instead.
842 ## `GFBREDPOLY` SPR -- Reducing Polynomial
844 In order to save registers and to make operations orthogonal with standard
845 arithmetic, the reducing polynomial is stored in a dedicated SPR `GFBREDPOLY`.
846 This also allows hardware to pre-compute useful parameters (such as the
847 degree, or look-up tables) based on the reducing polynomial, and store them
848 alongside the SPR in hidden registers, only recomputing them whenever the SPR
849 is written to, rather than having to recompute those values for every
852 Because Galois Fields require the reducing polynomial to be an irreducible
853 polynomial, that guarantees that any polynomial of `degree > 1` must have
854 the LSB set, since otherwise it would be divisible by the polynomial `x`,
855 making it reducible, making whatever we're working on no longer a Field.
856 Therefore, we can reuse the LSB to indicate `degree == XLEN`.
859 [[!inline pagenames="gf_reference/decode_reducing_polynomial.py" raw="yes"]]
862 ## `gfbredpoly` -- Set the Reducing Polynomial SPR `GFBREDPOLY`
864 unless this is an immediate op, `mtspr` is completely sufficient.
867 [[!inline pagenames="gf_reference/gfbredpoly.py" raw="yes"]]
870 ## `gfbmul` -- Binary Galois Field `GF(2^m)` Multiplication
877 [[!inline pagenames="gf_reference/gfbmul.py" raw="yes"]]
880 ## `gfbmadd` -- Binary Galois Field `GF(2^m)` Multiply-Add
883 gfbmadd RT, RA, RB, RC
887 [[!inline pagenames="gf_reference/gfbmadd.py" raw="yes"]]
890 ## `gfbtmadd` -- Binary Galois Field `GF(2^m)` Twin Multiply-Add (for FFT)
892 Used in combination with SV FFT REMAP to perform a full `GF(2^m)` Discrete
893 Fourier Transform in-place. Possible by having 3-in 2-out, to avoid the need
894 for a temp register. RS is written to as well as RT.
897 gfbtmadd RT, RA, RB, RC
900 TODO: add link to explanation for where `RS` comes from.
905 # read all inputs before writing to any outputs in case
906 # an input overlaps with an output register.
907 (RT) = gfbmadd(a, (RB), c)
908 # use gfbmadd again since it reduces the result
909 (RS) = gfbmadd(a, 1, c) # "a * 1 + c"
912 ## `gfbinv` -- Binary Galois Field `GF(2^m)` Inverse
919 [[!inline pagenames="gf_reference/gfbinv.py" raw="yes"]]
922 # Instructions for Prime Galois Fields `GF(p)`
924 ## `GFPRIME` SPR -- Prime Modulus For `gfp*` Instructions
926 ## `gfpadd` Prime Galois Field `GF(p)` Addition
933 [[!inline pagenames="gf_reference/gfpadd.py" raw="yes"]]
936 the addition happens on infinite-precision integers
938 ## `gfpsub` Prime Galois Field `GF(p)` Subtraction
945 [[!inline pagenames="gf_reference/gfpsub.py" raw="yes"]]
948 the subtraction happens on infinite-precision integers
950 ## `gfpmul` Prime Galois Field `GF(p)` Multiplication
957 [[!inline pagenames="gf_reference/gfpmul.py" raw="yes"]]
960 the multiplication happens on infinite-precision integers
962 ## `gfpinv` Prime Galois Field `GF(p)` Invert
968 Some potential hardware implementations are found in:
969 <https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.90.5233&rep=rep1&type=pdf>
972 [[!inline pagenames="gf_reference/gfpinv.py" raw="yes"]]
975 ## `gfpmadd` Prime Galois Field `GF(p)` Multiply-Add
978 gfpmadd RT, RA, RB, RC
982 [[!inline pagenames="gf_reference/gfpmadd.py" raw="yes"]]
985 the multiplication and addition happens on infinite-precision integers
987 ## `gfpmsub` Prime Galois Field `GF(p)` Multiply-Subtract
990 gfpmsub RT, RA, RB, RC
994 [[!inline pagenames="gf_reference/gfpmsub.py" raw="yes"]]
997 the multiplication and subtraction happens on infinite-precision integers
999 ## `gfpmsubr` Prime Galois Field `GF(p)` Multiply-Subtract-Reversed
1002 gfpmsubr RT, RA, RB, RC
1006 [[!inline pagenames="gf_reference/gfpmsubr.py" raw="yes"]]
1009 the multiplication and subtraction happens on infinite-precision integers
1011 ## `gfpmaddsubr` Prime Galois Field `GF(p)` Multiply-Add and Multiply-Sub-Reversed (for FFT)
1013 Used in combination with SV FFT REMAP to perform
1014 a full Number-Theoretic-Transform in-place. Possible by having 3-in 2-out,
1015 to avoid the need for a temp register. RS is written
1019 gfpmaddsubr RT, RA, RB, RC
1022 TODO: add link to explanation for where `RS` comes from.
1028 # read all inputs before writing to any outputs in case
1029 # an input overlaps with an output register.
1030 (RT) = gfpmadd(factor1, factor2, term)
1031 (RS) = gfpmsubr(factor1, factor2, term)
1034 # Already in POWER ISA or subsumed
1036 Lists operations either included as part of
1037 other bitmanip operations, or are already in
1042 based on RV bitmanip, covered by ternlog bitops
1045 uint_xlen_t cmix(uint_xlen_t RA, uint_xlen_t RB, uint_xlen_t RC) {
1046 return (RA & RB) | (RC & ~RB);
1050 ## count leading/trailing zeros with mask
1056 do i = 0 to 63 if((RB)i=1) then do
1057 if((RS)i=1) then break end end count ← count + 1
1063 pdepd VRT,VRA,VRB, identical to RV bitmamip bdep, found already in v3.1 p106
1066 if VSR[VRB+32].dword[i].bit[63-m]=1 then do
1067 result = VSR[VRA+32].dword[i].bit[63-k]
1068 VSR[VRT+32].dword[i].bit[63-m] = result
1074 uint_xlen_t bdep(uint_xlen_t RA, uint_xlen_t RB)
1077 for (int i = 0, j = 0; i < XLEN; i++)
1078 if ((RB >> i) & 1) {
1080 r |= uint_xlen_t(1) << i;
1090 other way round: identical to RV bext: pextd, found in v3.1 p196
1093 uint_xlen_t bext(uint_xlen_t RA, uint_xlen_t RB)
1096 for (int i = 0, j = 0; i < XLEN; i++)
1097 if ((RB >> i) & 1) {
1099 r |= uint_xlen_t(1) << j;
1108 found in v3.1 p106 so not to be added here
1118 if((RB)63-i==1) then do
1119 result63-ptr1 = (RS)63-i
1125 ## bit to byte permute
1127 similar to matrix permute in RV bitmanip, which has XOR and OR variants,
1128 these perform a transpose (bmatflip).
1129 TODO this looks VSX is there a scalar variant
1134 b = VSR[VRB+32].dword[i].byte[k].bit[j]
1135 VSR[VRT+32].dword[i].byte[j].bit[k] = b
1139 superceded by grevlut
1141 based on RV bitmanip, this is also known as a butterfly network. however
1142 where a butterfly network allows setting of every crossbar setting in
1143 every row and every column, generalised-reverse (grev) only allows
1144 a per-row decision: every entry in the same row must either switch or
1147 <img src="https://upload.wikimedia.org/wikipedia/commons/thumb/8/8c/Butterfly_Network.jpg/474px-Butterfly_Network.jpg" />
1150 uint64_t grev64(uint64_t RA, uint64_t RB)
1153 int shamt = RB & 63;
1154 if (shamt & 1) x = ((x & 0x5555555555555555LL) << 1) |
1155 ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
1156 if (shamt & 2) x = ((x & 0x3333333333333333LL) << 2) |
1157 ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
1158 if (shamt & 4) x = ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
1159 ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
1160 if (shamt & 8) x = ((x & 0x00FF00FF00FF00FFLL) << 8) |
1161 ((x & 0xFF00FF00FF00FF00LL) >> 8);
1162 if (shamt & 16) x = ((x & 0x0000FFFF0000FFFFLL) << 16) |
1163 ((x & 0xFFFF0000FFFF0000LL) >> 16);
1164 if (shamt & 32) x = ((x & 0x00000000FFFFFFFFLL) << 32) |
1165 ((x & 0xFFFFFFFF00000000LL) >> 32);
1173 based on RV bitmanip, gorc is superceded by grevlut
1176 uint32_t gorc32(uint32_t RA, uint32_t RB)
1179 int shamt = RB & 31;
1180 if (shamt & 1) x |= ((x & 0x55555555) << 1) | ((x & 0xAAAAAAAA) >> 1);
1181 if (shamt & 2) x |= ((x & 0x33333333) << 2) | ((x & 0xCCCCCCCC) >> 2);
1182 if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4) | ((x & 0xF0F0F0F0) >> 4);
1183 if (shamt & 8) x |= ((x & 0x00FF00FF) << 8) | ((x & 0xFF00FF00) >> 8);
1184 if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16);
1187 uint64_t gorc64(uint64_t RA, uint64_t RB)
1190 int shamt = RB & 63;
1191 if (shamt & 1) x |= ((x & 0x5555555555555555LL) << 1) |
1192 ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
1193 if (shamt & 2) x |= ((x & 0x3333333333333333LL) << 2) |
1194 ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
1195 if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
1196 ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
1197 if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL) << 8) |
1198 ((x & 0xFF00FF00FF00FF00LL) >> 8);
1199 if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL) << 16) |
1200 ((x & 0xFFFF0000FFFF0000LL) >> 16);
1201 if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL) << 32) |
1202 ((x & 0xFFFFFFFF00000000LL) >> 32);
1211 see [[bitmanip/appendix]]