openpower/sv/bitmanip.mdwn

   1 [[!tag standards]]
   2
   3 # TODO
   4
   5 * remove Rc=1 from ternlog due to conflicts in encoding as well
   6   as saving space
   7
   8 # bitmanipulation
   9
  10 **DRAFT STATUS**
  11
  12 this extension amalgamates bitmanipulation primitives from many sources, including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX.  Vectorisation and SIMD are removed: these are straight scalar (element) operations making them suitable for embedded applications.
  13 Vectorisation Context is provided by [[openpower/sv]].
  14
  15 When combined with SV, scalar variants of bitmanip operations found in VSX are added so that VSX may be retired as "legacy" in the far future (10 to 20 years).  Also, VSX is hundreds of opcodes, requires 128 bit pathways, and is wholly unsuited to low power or embedded scenarios.
  16
  17 ternlogv is experimental and is the only operation that may be considered a "Packed SIMD".  It is added as a variant of the already well-justified ternlog operation (done in AVX512 as an immediate only) "because it looks fun". As it is based on the LUT4 concept it will allow accelerated emulation of FPGAs.  Other vendors of ISAs are buying FPGA companies to achieve similar objectives.
  18
  19 general-purpose Galois Field operations are added so as to avoid huge custom opcode proliferation across many areas of Computer Science.  however for convenience and also to avoid setup costs, some of the more common operations (clmul, crc32) are also added.  The expectation is that these operations would all be covered by the same pipeline.
  20
  21 note that there are brownfield spaces below that could incorporate some of the set-before-first and other scalar operations listed in [[sv/vector_ops]], and
  22 the [[sv/av_opcodes]] as well as [[sv/setvl]]
  23
  24 Useful resource:
  25
  26 * <https://en.wikiversity.org/wiki/Reed%E2%80%93Solomon_codes_for_coders>
  27 * <https://maths-people.anu.edu.au/~brent/pd/rpb232tr.pdf>
  28
  29 # summary
  30
  31 minor opcode allocation
  32
  33     |  28.30 |31| name      |
  34     | ------ |--| --------- |
  35     |   00   |0 | ternlogi  |
  36     |  000   |1 | ternlog   |
  37     |  100   |  | reserved  |
  38     |  010   |Rc| bitmask   |
  39     |  011   |Rc| gf*       |
  40     |  101   |1 | ternlogv  |
  41     |  101   |0 | ternlogcr |
  42     |  110   |Rc| 1/2-op    |
  43     |  111   |Rc| 3-op      |
  44
  45 1-op and variants
  46
  47 | dest | src1 | subop | op       |
  48 | ---- | ---- | ----- | -------- |
  49 | RT   | RA   | ..    | bmatflip |
  50
  51 2-op and variants
  52
  53 | dest | src1 | src2 | subop | op       |
  54 | ---- | ---- | ---- | ----- | -------- |
  55 | RT   | RA   | RB   | or    | bmatflip |
  56 | RT   | RA   | RB   | xor   | bmatflip |
  57 | RT   | RA   | RB   |       | grev  |
  58 | RT   | RA   | RB   |       | clmul*  |
  59 | RT   | RA   | RB   |       | gorc |
  60 | RT   | RA   | RB   | shuf  | shuffle |
  61 | RT   | RA   | RB   | unshuf| shuffle |
  62 | RT   | RA   | RB   | width | xperm  |
  63 | RT   | RA   | RB   | type | minmax |
  64 | RT   | RA   | RB   |      | av abs avgadd  |
  65 | RT   | RA   | RB   | type | vmask ops |
  66 | RT   | RA   | RB   |  |  |
  67
  68 3 ops
  69
  70 * bitmask set/extract
  71 * ternlog bitops
  72 * GF
  73
  74 | 0.5|6.10|11.15|16.20|21..25 | 26....30 |31| name |
  75 | -- | -- | --- | --- | ----- | -------- |--| ------ |
  76 | NN | RT | RA  | RB  | RC    | mode 001 |Rc| ternlog |
  77 | NN | RT | RA  | RB  | im0-4 | im5-7 00 |Rc| ternlogi |
  78 | NN | RS | RA  | RB  | RC    | 00  011  |Rc| gfmul |
  79 | NN | RS | RA  | RB  | RC    | 01  011  |Rc| gfadd |
  80 | NN | RT | RA  | RB  | deg   | 10  011  |Rc| gfinv |
  81 | NN | RS | RA  | RB  | deg   | 11  011  |Rc| gfmuli |
  82 | NN | RS | RA  | RB  | deg   | 11  111  |Rc| gfaddi |
  83
  84 | 0.5|6.10|11.15| 16.23 |24.27 | 28.30 |31| name |
  85 | -- | -- | --- | ----- | ---- | ----- |--| ------ |
  86 | NN | RT | RA  | imm   | mask | 101   |1 | ternlogv |
  87
  88 | 0.5|6.8 | 9.11|12.14|15|16.23|24.27 | 28.30|31| name |
  89 | -- | -- | --- | --- |- |-----|----- | -----|--| -------|
  90 | NN | BA | BB  | BC  |0 |imm  | mask | 101  |0 | ternlogcr |
  91
  92 ops (note that av avg and abs as well as vec scalar mask
  93 are included here)
  94
  95 | 0.5|6.10|11.15|16.20| 21.22 | 23 | 24....30 |31| name |
  96 | -- | -- | --- | --- | ----- | -- | -------- |--| ---- |
  97 | NN | RA | RB  |     |       | 0  | 0000 110 |Rc| rsvd   |
  98 | NN | RA | RB  | RC  | itype | 1  | 0000 110 |Rc| xperm |
  99 | NN | RA | RB  | RC  | itype | 0  | 0100 110 |Rc| minmax |
 100 | NN | RA | RB  | RC  |   00  | 1  | 0100 110 |Rc| av avgadd |
 101 | NN | RA | RB  | RC  |   01  | 1  | 0100 110 |Rc| av abs |
 102 | NN | RA | RB  |     |   10  | 1  | 0100 110 |Rc| rsvd |
 103 | NN | RA | RB  |     |   11  | 1  | 0100 110 |Rc| rsvd |
 104 | NN | RA | RB  | sh  | itype | SH | 1000 110 |Rc| bmopsi |
 105 | NN | RA | RB  |     |       |    | 1100 110 |Rc| rsvd |
 106 | NN | RA | RB  |     |       | 1  | 0001 110 |Rc| rsvd |
 107 | NN | RA | RB  | RC  |   00  | 0  | 0001 110 |Rc| vec sbfm |
 108 | NN | RA | RB  | RC  |   01  | 0  | 0001 110 |Rc| vec sofm |
 109 | NN | RA | RB  | RC  |   10  | 0  | 0001 110 |Rc| vec sifm |
 110 | NN | RA | RB  | RC  |   11  | 0  | 0001 110 |Rc| vec cprop |
 111 | NN | RA | RB  |     |       | 0  | 0101 110 |Rc| rsvd |
 112 | NN | RA | RB  | RC  | 00    | 0  | 0010 110 |Rc| gorc |
 113 | NN | RA | RB  | sh  | 00    | SH | 1010 110 |Rc| gorci |
 114 | NN | RA | RB  | RC  | 00    | 0  | 0110 110 |Rc| gorcw |
 115 | NN | RA | RB  | sh  | 00    | 0  | 1110 110 |Rc| gorcwi |
 116 | NN | RA | RB  | RC  | 00    | 1  | 1110 110 |Rc| bmator  |
 117 | NN | RA | RB  | RC  | 01    | 0  | 0010 110 |Rc| grev |
 118 | NN | RA | RB  | RC  | 01    | 1  | 0010 110 |Rc| clmul |
 119 | NN | RA | RB  | sh  | 01    | SH | 1010 110 |Rc| grevi |
 120 | NN | RA | RB  | RC  | 01    | 0  | 0110 110 |Rc| grevw |
 121 | NN | RA | RB  | sh  | 01    | 0  | 1110 110 |Rc| grevwi |
 122 | NN | RA | RB  | RC  | 01    | 1  | 1110 110 |Rc| bmatxor   |
 123 | NN | RA | RB  | RC  | 10    | 0  | 0010 110 |Rc| shfl |
 124 | NN | RA | RB  | sh  | 10    | SH | 1010 110 |Rc| shfli |
 125 | NN | RA | RB  | RC  | 10    | 0  | 0110 110 |Rc| shflw |
 126 | NN | RA | RB  | RC  | 10    |    | 1110 110 |Rc| rsvd   |
 127 | NN | RA | RB  | RC  | 11    | 0  | 1110 110 |Rc| clmulr  |
 128 | NN | RA | RB  | RC  | 11    | 1  | 1110 110 |Rc| clmulh  |
 129 | NN |    |     |     |       |    | --11 110 |Rc| setvl  |
 130
 131 # count leading/trailing zeros with mask
 132
 133 in v3.1 p105
 134
 135 ```
 136 count = 0
 137 do i = 0 to 63 if((RB)i=1) then do
 138 if((RS)i=1) then break end end count ← count + 1
 139 RA ← EXTZ64(count)
 140 ```
 141
 142 # bit to byte permute
 143
 144 similar to matrix permute in RV bitmanip, which has XOR and OR variants
 145
 146     do j = 0 to 7
 147       do k = 0 to 7
 148          b = VSR[VRB+32].dword[i].byte[k].bit[j]
 149          VSR[VRT+32].dword[i].byte[j].bit[k] = b
 150
 151 #  bit deposit
 152
 153 vpdepd VRT,VRA,VRB, identical to RV bitmamip bdep, found already in v3.1 p106
 154
 155     do while(m < 64)
 156        if VSR[VRB+32].dword[i].bit[63-m]=1 then do
 157           result = VSR[VRA+32].dword[i].bit[63-k]
 158           VSR[VRT+32].dword[i].bit[63-m] = result
 159           k = k + 1
 160        m = m + 1
 161
 162 ```
 163
 164 uint_xlen_t bdep(uint_xlen_t RA, uint_xlen_t RB)
 165 {
 166     uint_xlen_t r = 0;
 167     for (int i = 0, j = 0; i < XLEN; i++)
 168         if ((RB >> i) & 1) {
 169             if ((RA >> j) & 1)
 170                 r |= uint_xlen_t(1) << i;
 171             j++;
 172         }
 173     return r;
 174 }
 175
 176 ```
 177
 178 # bit extract
 179
 180 other way round: identical to RV bext, found in v3.1 p196
 181
 182 ```
 183 uint_xlen_t bext(uint_xlen_t RA, uint_xlen_t RB)
 184 {
 185     uint_xlen_t r = 0;
 186     for (int i = 0, j = 0; i < XLEN; i++)
 187         if ((RB >> i) & 1) {
 188             if ((RA >> i) & 1)
 189                 r |= uint_xlen_t(1) << j;
 190             j++;
 191         }
 192     return r;
 193 }
 194 ```
 195
 196 # centrifuge
 197
 198 found in v3.1 p106 so not to be added here
 199
 200 ```
 201 ptr0 = 0
 202 ptr1 = 0
 203 do i = 0 to 63
 204     if((RB)i=0) then do
 205        resultptr0 = (RS)i
 206     end
 207     ptr0 = ptr0 + 1
 208     if((RB)63-i==1) then do
 209         result63-ptr1 = (RS)63-i
 210     end
 211     ptr1 = ptr1 + 1
 212 RA = result
 213 ```
 214
 215 # int min/max
 216
 217 signed and unsigned min/max for integer.  this is sort-of partly synthesiseable in [[sv/svp64]] with pred-result as long as the dest reg is one of the sources, but not both signed and unsigned.  when the dest is also one of the srces and the mv fails due to the CR bittest failing this will only overwrite the dest where the src is greater (or less).
 218
 219 signed/unsigned min/max gives more flexibility.
 220
 221 ```
 222 uint_xlen_t min(uint_xlen_t rs1, uint_xlen_t rs2)
 223 { return (int_xlen_t)rs1 < (int_xlen_t)rs2 ? rs1 : rs2;
 224 }
 225 uint_xlen_t max(uint_xlen_t rs1, uint_xlen_t rs2)
 226 { return (int_xlen_t)rs1 > (int_xlen_t)rs2 ? rs1 : rs2;
 227 }
 228 uint_xlen_t minu(uint_xlen_t rs1, uint_xlen_t rs2)
 229 { return rs1 < rs2 ? rs1 : rs2;
 230 }
 231 uint_xlen_t maxu(uint_xlen_t rs1, uint_xlen_t rs2)
 232 { return rs1 > rs2 ? rs1 : rs2;
 233 }
 234 ```
 235
 236
 237 # ternlog bitops
 238
 239 Similar to FPGA LUTs: for every bit perform a lookup into a table using an 8bit immediate, or in another register.
 240
 241 Like the x86 AVX512F [vpternlogd/vpternlogq](https://www.felixcloutier.com/x86/vpternlogd:vpternlogq) instructions.
 242
 243 | 0.5|6.10|11.15|16.20| 21..25| 26..30   |31|
 244 | -- | -- | --- | --- | ----- | -------- |--|
 245 | NN | RT | RA  | RB  | im0-4 | im5-7 00 |Rc|
 246
 247     for i in range(64):
 248         idx = RT[i] << 2 | RA[i] << 1 | RB[i]
 249         RT[i] = (imm & (1<<idx)) != 0
 250
 251 bits 21..22 may be used to specify a mode, such as treating the whole integer zero/nonzero and putting 1/0 in the result, rather than bitwise test.
 252
 253 a 4 operand variant which becomes more along the lines of an FPGA:
 254
 255 | 0.5|6.10|11.15|16.20|21.25| 26...30  |31|
 256 | -- | -- | --- | --- | --- | -------- |--|
 257 | NN | RT | RA  | RB  | RC  | mode 001 |Rc|
 258
 259     for i in range(64):
 260         idx = RT[i] << 2 | RA[i] << 1 | RB[i]
 261         RT[i] = (RC & (1<<idx)) != 0
 262
 263 mode (2 bit) may be used to do inversion of ordering, similar to carryless mul,
 264 3 modes.
 265
 266 also, another possible variant involving swizzle and vec4:
 267
 268 | 0.5|6.10|11.15| 16.23 |24.27 | 28.30 |31|
 269 | -- | -- | --- | ----- | ---- | ----- |--|
 270 | NN | RT | RA  | imm   | mask | 101   |1 |
 271
 272     for i in range(8):
 273         idx = RA.x[i] << 2 | RA.y[i] << 1 | RA.z[i]
 274         res = (imm & (1<<idx)) != 0
 275         for j in range(3):
 276              if mask[j]: RT[i+j*8] = res
 277
 278 another mode selection would be CRs not Ints.
 279
 280 | 0.5|6.8 | 9.11|12.14|15|16.23|24.27 | 28.30|31|
 281 | -- | -- | --- | --- |- |-----|----- | -----|--|
 282 | NN | BA | BB  | BC  |0 |imm  | mask | 101  |0 |
 283
 284     for i in range(4):
 285         if not mask[i] continue
 286         idx = crregs[BA][i] << 2 |
 287               crregs[BB][i] << 1 |
 288               crregs[BC][i]
 289         crregs[BA][i] = (imm & (1<<idx)) != 0
 290
 291 # bitmask set
 292
 293 based on RV bitmanip singlebit set, instruction format similar to shift
 294 [[isa/fixedshift]].  bmext is actually covered already (shift-with-mask rldicl but only immediate version).
 295 however bitmask-invert is not, and set/clr are not covered, although they can use the same Shift ALU.
 296
 297 bmext (RB) version is not the same as rldicl because bmext is a right shift by RC, where rldicl is a left rotate.  for the immediate version this does not matter, so a bmexti is not required.
 298 bmrev however there is no direct equivalent and consequently a bmrevi is required.
 299
 300 bmset (register for mask amount) is particularly useful for creating
 301 predicate masks where the length is a dynamic runtime quantity.
 302 bmset(RA=0, RB=0, RC=mask) will produce a run of ones of length "mask" in a single instruction without needing to initialise or depend on any other registers.
 303
 304 | 0.5|6.10|11.15|16.20|21.25| 26..30  |31| name  |
 305 | -- | -- | --- | --- | --- | ------- |--| ----- |
 306 | NN | RT | RA  | RB  | RC  | mode 010 |Rc| bm*   |
 307 | NN | RT | RA  | RB  | RC  | 0 1  111 |Rc| bmrev |
 308
 309
 310 ```
 311 uint_xlen_t bmset(RA, RB, sh)
 312 {
 313     int shamt = RB & (XLEN - 1);
 314     mask = (2<<sh)-1;
 315     return RA | (mask << shamt);
 316 }
 317
 318 uint_xlen_t bmclr(RA, RB, sh)
 319 {
 320     int shamt = RB & (XLEN - 1);
 321     mask = (2<<sh)-1;
 322     return RA & ~(mask << shamt);
 323 }
 324
 325 uint_xlen_t bminv(RA, RB, sh)
 326 {
 327     int shamt = RB & (XLEN - 1);
 328     mask = (2<<sh)-1;
 329     return RA ^ (mask << shamt);
 330 }
 331
 332 uint_xlen_t bmext(RA, RB, sh)
 333 {
 334     int shamt = RB & (XLEN - 1);
 335     mask = (2<<sh)-1;
 336     return mask & (RA >> shamt);
 337 }
 338 ```
 339
 340 bitmask extract with reverse.  can be done by bitinverting all of RA and getting bits of RA from the opposite end.
 341
 342 ```
 343 msb = rb[5:0];
 344 rev[0:msb] = ra[msb:0];
 345 rt = ZE(rev[msb:0]);
 346
 347 uint_xlen_t bmextrev(RA, RB, sh)
 348 {
 349     int shamt = (RB & (XLEN - 1));
 350     shamt = (XLEN-1)-shamt;  # shift other end
 351     bra = bitreverse(RA)     # swap LSB-MSB
 352     mask = (2<<sh)-1;
 353     return mask & (bra >> shamt);
 354 }
 355 ```
 356
 357 | 0.5|6.10|11.15|16.20|21.26| 27..30  |31| name   |
 358 | -- | -- | --- | --- | --- | ------- |--| ------ |
 359 | NN | RT | RA  | RB  | sh  | 0   111 |Rc| bmrevi |
 360
 361
 362
 363 # grev
 364
 365 based on RV bitmanip
 366
 367 ```
 368 uint64_t grev64(uint64_t RA, uint64_t RB)
 369 {
 370     uint64_t x = RA;
 371     int shamt = RB & 63;
 372     if (shamt & 1) x = ((x &  0x5555555555555555LL) <<  1) |
 373                         ((x & 0xAAAAAAAAAAAAAAAALL) >>  1);
 374     if (shamt & 2) x = ((x &  0x3333333333333333LL) <<  2) |
 375                         ((x & 0xCCCCCCCCCCCCCCCCLL) >>  2);
 376     if (shamt & 4) x = ((x &  0x0F0F0F0F0F0F0F0FLL) <<  4) |
 377                         ((x & 0xF0F0F0F0F0F0F0F0LL) >>  4);
 378     if (shamt & 8) x = ((x &  0x00FF00FF00FF00FFLL) <<  8) |
 379                         ((x & 0xFF00FF00FF00FF00LL) >>  8);
 380     if (shamt & 16) x = ((x & 0x0000FFFF0000FFFFLL) << 16) |
 381                         ((x & 0xFFFF0000FFFF0000LL) >> 16);
 382     if (shamt & 32) x = ((x & 0x00000000FFFFFFFFLL) << 32) |
 383                         ((x & 0xFFFFFFFF00000000LL) >> 32);
 384     return x;
 385 }
 386
 387 ```
 388
 389 # shuffle / unshuffle
 390
 391 based on RV bitmanip
 392
 393 ```
 394 uint32_t shfl32(uint32_t RA, uint32_t RB)
 395 {
 396     uint32_t x = RA;
 397     int shamt = RB & 15;
 398     if (shamt & 8) x  = shuffle32_stage(x, 0x00ff0000, 0x0000ff00, 8);
 399     if (shamt & 4) x  = shuffle32_stage(x, 0x0f000f00, 0x00f000f0, 4);
 400     if (shamt & 2) x  = shuffle32_stage(x, 0x30303030, 0x0c0c0c0c, 2);
 401     if (shamt & 1) x  = shuffle32_stage(x, 0x44444444, 0x22222222, 1);
 402     return x;
 403 }
 404 uint32_t unshfl32(uint32_t RA, uint32_t RB)
 405 {
 406     uint32_t x = RA;
 407     int shamt = RB & 15;
 408     if (shamt & 1) x  = shuffle32_stage(x, 0x44444444, 0x22222222, 1);
 409     if (shamt & 2) x  = shuffle32_stage(x, 0x30303030, 0x0c0c0c0c, 2);
 410     if (shamt & 4) x  = shuffle32_stage(x, 0x0f000f00, 0x00f000f0, 4);
 411     if (shamt & 8) x  = shuffle32_stage(x, 0x00ff0000, 0x0000ff00, 8);
 412     return x;
 413 }
 414
 415 uint64_t shuffle64_stage(uint64_t src, uint64_t maskL, uint64_t maskR, int N)
 416 {
 417     uint64_t x = src & ~(maskL | maskR);
 418     x |= ((src << N) & maskL) | ((src >> N) & maskR);
 419     return x;
 420 }
 421 uint64_t shfl64(uint64_t RA, uint64_t RB)
 422 {
 423     uint64_t x = RA;
 424     int shamt = RB & 31;
 425     if (shamt & 16) x = shuffle64_stage(x, 0x0000ffff00000000LL,
 426                                            0x00000000ffff0000LL, 16);
 427     if (shamt & 8) x = shuffle64_stage(x, 0x00ff000000ff0000LL,
 428                                            0x0000ff000000ff00LL, 8);
 429     if (shamt & 4) x = shuffle64_stage(x, 0x0f000f000f000f00LL,
 430                                            0x00f000f000f000f0LL, 4);
 431     if (shamt & 2) x = shuffle64_stage(x, 0x3030303030303030LL,
 432                                            0x0c0c0c0c0c0c0c0cLL, 2);
 433     if (shamt & 1) x = shuffle64_stage(x, 0x4444444444444444LL,
 434                                            0x2222222222222222LL, 1);
 435     return x;
 436 }
 437 uint64_t unshfl64(uint64_t RA, uint64_t RB)
 438 {
 439     uint64_t x = RA;
 440     int shamt = RB & 31;
 441     if (shamt &  1) x = shuffle64_stage(x, 0x4444444444444444LL,
 442                                            0x2222222222222222LL, 1);
 443     if (shamt &  2) x = shuffle64_stage(x, 0x3030303030303030LL,
 444                                            0x0c0c0c0c0c0c0c0cLL, 2);
 445     if (shamt &  4) x = shuffle64_stage(x, 0x0f000f000f000f00LL,
 446                                            0x00f000f000f000f0LL, 4);
 447     if (shamt &  8) x = shuffle64_stage(x, 0x00ff000000ff0000LL,
 448                                            0x0000ff000000ff00LL, 8);
 449     if (shamt & 16) x = shuffle64_stage(x, 0x0000ffff00000000LL,
 450                                            0x00000000ffff0000LL, 16);
 451     return x;
 452 }
 453 ```
 454
 455 # xperm
 456
 457 based on RV bitmanip
 458
 459 ```
 460 uint_xlen_t xperm(uint_xlen_t RA, uint_xlen_t RB, int sz_log2)
 461 {
 462     uint_xlen_t r = 0;
 463     uint_xlen_t sz = 1LL << sz_log2;
 464     uint_xlen_t mask = (1LL << sz) - 1;
 465     for (int i = 0; i < XLEN; i += sz) {
 466         uint_xlen_t pos = ((RB >> i) & mask) << sz_log2;
 467         if (pos < XLEN)
 468             r |= ((RA >> pos) & mask) << i;
 469     }
 470     return r;
 471 }
 472 uint_xlen_t xperm_n (uint_xlen_t RA, uint_xlen_t RB)
 473 {  return xperm(RA, RB, 2); }
 474 uint_xlen_t xperm_b (uint_xlen_t RA, uint_xlen_t RB)
 475 {  return xperm(RA, RB, 3); }
 476 uint_xlen_t xperm_h (uint_xlen_t RA, uint_xlen_t RB)
 477 {  return xperm(RA, RB, 4); }
 478 uint_xlen_t xperm_w (uint_xlen_t RA, uint_xlen_t RB)
 479 {  return xperm(RA, RB, 5); }
 480 ```
 481
 482 # gorc
 483
 484 based on RV bitmanip
 485
 486 ```
 487 uint32_t gorc32(uint32_t RA, uint32_t RB)
 488 {
 489     uint32_t x = RA;
 490     int shamt = RB & 31;
 491     if (shamt & 1) x |= ((x & 0x55555555) << 1)   |  ((x &  0xAAAAAAAA) >> 1);
 492     if (shamt & 2) x |= ((x & 0x33333333) << 2)   |  ((x &  0xCCCCCCCC) >> 2);
 493     if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4)   |  ((x &  0xF0F0F0F0) >> 4);
 494     if (shamt & 8) x |= ((x & 0x00FF00FF) << 8)   |  ((x &  0xFF00FF00) >> 8);
 495     if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) |  ((x &  0xFFFF0000) >> 16);
 496     return x;
 497 }
 498 uint64_t gorc64(uint64_t RA, uint64_t RB)
 499 {
 500     uint64_t x = RA;
 501     int shamt = RB & 63;
 502     if (shamt & 1) x |= ((x & 0x5555555555555555LL)   <<   1) |
 503                          ((x & 0xAAAAAAAAAAAAAAAALL)  >>  1);
 504     if (shamt & 2) x |= ((x & 0x3333333333333333LL)   <<   2) |
 505                          ((x & 0xCCCCCCCCCCCCCCCCLL)  >>  2);
 506     if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL)   <<   4) |
 507                          ((x & 0xF0F0F0F0F0F0F0F0LL)  >>  4);
 508     if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL)   <<   8) |
 509                          ((x & 0xFF00FF00FF00FF00LL)  >>  8);
 510     if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL)  << 16) |
 511                          ((x & 0xFFFF0000FFFF0000LL)  >> 16);
 512     if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL)  << 32) |
 513                          ((x & 0xFFFFFFFF00000000LL)  >> 32);
 514     return x;
 515 }
 516
 517 ```
 518
 519 # cmix
 520
 521 based on RV bitmanip, covered by ternlog bitops
 522
 523 ```
 524 uint_xlen_t cmix(uint_xlen_t RA, uint_xlen_t RB, uint_xlen_t RC) {
 525     return (RA & RB) | (RC & ~RB);
 526 }
 527 ```
 528
 529 # carryless mul
 530
 531 based on RV bitmanip
 532 see https://en.wikipedia.org/wiki/CLMUL_instruction_set
 533
 534 ```
 535 uint_xlen_t clmul(uint_xlen_t RA, uint_xlen_t RB)
 536 {
 537     uint_xlen_t x = 0;
 538     for (int i = 0; i < XLEN; i++)
 539         if ((RB >> i) & 1)
 540             x ^= RA << i;
 541     return x;
 542 }
 543 uint_xlen_t clmulh(uint_xlen_t RA, uint_xlen_t RB)
 544 {
 545     uint_xlen_t x = 0;
 546     for (int i = 1; i < XLEN; i++)
 547         if ((RB >> i) & 1)
 548             x ^= RA >> (XLEN-i);
 549     return x;
 550 }
 551 uint_xlen_t clmulr(uint_xlen_t RA, uint_xlen_t RB)
 552 {
 553     uint_xlen_t x = 0;
 554     for (int i = 0; i < XLEN; i++)
 555         if ((RB >> i) & 1)
 556             x ^= RA >> (XLEN-i-1);
 557     return x;
 558 }
 559 ```
 560 # Galois Field
 561
 562 see <https://courses.csail.mit.edu/6.857/2016/files/ffield.py>
 563
 564 ## Multiply
 565
 566 this requires 3 parameters and a "degree"
 567
 568     RT = GFMUL(RA, RB, gfdegree, modulo=RC)
 569
 570 realistically with the degree also needing to be an immediate it should be brought down to an overwrite version:
 571
 572     RS = GFMUL(RS, RA, gfdegree, modulo=RB)
 573     RS = GFMUL(RS, RA, gfdegree=RC, modulo=RB)
 574
 575 | 0.5|6.10|11.15|16.20|21.25| 26..30  |31|
 576 | -- | -- | --- | --- | --- | ------- |--|
 577 | NN | RS | RA  | RB  | deg | 00  011 |Rc|
 578 | NN | RS | RA  | RB  | RC  | 11  011 |Rc|
 579
 580 where the SimpleV variant may override RS-as-src differently from RS-as-dest
 581
 582
 583
 584 ```
 585 from functools import reduce
 586
 587 # constants used in the multGF2 function
 588 mask1 = mask2 = polyred = None
 589
 590 def setGF2(degree, irPoly):
 591     """Define parameters of binary finite field GF(2^m)/g(x)
 592        - degree: extension degree of binary field
 593        - irPoly: coefficients of irreducible polynomial g(x)
 594     """
 595     def i2P(sInt):
 596         """Convert an integer into a polynomial"""
 597         return [(sInt >> i) & 1
 598                 for i in reversed(range(sInt.bit_length()))]
 599
 600     global mask1, mask2, polyred
 601     mask1 = mask2 = 1 << degree
 602     mask2 -= 1
 603     polyred = reduce(lambda x, y: (x << 1) + y, i2P(irPoly)[1:])
 604
 605 def multGF2(p1, p2):
 606     """Multiply two polynomials in GF(2^m)/g(x)"""
 607     p = 0
 608     while p2:
 609         if p2 & 1:
 610             p ^= p1
 611         p1 <<= 1
 612         if p1 & mask1:
 613             p1 ^= polyred
 614         p2 >>= 1
 615     return p & mask2
 616
 617 if __name__ == "__main__":
 618
 619     # Define binary field GF(2^3)/x^3 + x + 1
 620     setGF2(3, 0b1011)
 621
 622     # Evaluate the product (x^2 + x + 1)(x^2 + 1)
 623     print("{:02x}".format(multGF2(0b111, 0b101)))
 624
 625     # Define binary field GF(2^8)/x^8 + x^4 + x^3 + x + 1
 626     # (used in the Advanced Encryption Standard-AES)
 627     setGF2(8, 0b100011011)
 628
 629     # Evaluate the product (x^7)(x^7 + x + 1)
 630     print("{:02x}".format(multGF2(0b10000000, 0b10000011)))
 631 ```
 632 ## GF add
 633
 634     RS = GFADDI(RS, RA|0, gfdegree, modulo=RB)
 635     RS = GFADD(RS, RA|0, gfdegree=RC, modulo=RB)
 636
 637 | 0.5|6.10|11.15|16.20|21.25| 26..30  |31| name  |
 638 | -- | -- | --- | --- | --- | ------- |--| ----- |
 639 | NN | RS | RA  | RB  | deg | 0 1  011 |Rc| gfaddi |
 640 | NN | RS | RA  | RB  | RC  | 1 1  111 |Rc| gfadd |
 641
 642 GFMOD is a pseudo-op where RA=0
 643
 644 ## gf invert
 645
 646 ```
 647 def gf_degree(a) :
 648   res = 0
 649   a >>= 1
 650   while (a != 0) :
 651     a >>= 1;
 652     res += 1;
 653   return res
 654
 655 def gf_invert(a, mod=0x1B) :
 656   v = mod
 657   g1 = 1
 658   g2 = 0
 659   j = gf_degree(a) - 8
 660
 661   while (a != 1) :
 662     if (j < 0) :
 663       a, v = v, a
 664       g1, g2 = g2, g1
 665       j = -j
 666
 667     a ^= v << j
 668     g1 ^= g2 << j
 669
 670     a %= 256  # Emulating 8-bit overflow
 671     g1 %= 256 # Emulating 8-bit overflow
 672
 673     j = gf_degree(a) - gf_degree(v)
 674
 675   return g1
 676 ```
 677
 678 # bitmatrix
 679
 680 ```
 681 uint64_t bmatflip(uint64_t RA)
 682 {
 683     uint64_t x = RA;
 684     x = shfl64(x, 31);
 685     x = shfl64(x, 31);
 686     x = shfl64(x, 31);
 687     return x;
 688 }
 689 uint64_t bmatxor(uint64_t RA, uint64_t RB)
 690 {
 691     // transpose of RB
 692     uint64_t RBt = bmatflip(RB);
 693     uint8_t u[8]; // rows of RA
 694     uint8_t v[8]; // cols of RB
 695     for (int i = 0; i < 8; i++) {
 696         u[i] = RA >> (i*8);
 697         v[i] = RBt >> (i*8);
 698     }
 699     uint64_t x = 0;
 700     for (int i = 0; i < 64; i++) {
 701         if (pcnt(u[i / 8] & v[i % 8]) & 1)
 702             x |= 1LL << i;
 703     }
 704     return x;
 705 }
 706 uint64_t bmator(uint64_t RA, uint64_t RB)
 707 {
 708     // transpose of RB
 709     uint64_t RBt = bmatflip(RB);
 710     uint8_t u[8]; // rows of RA
 711     uint8_t v[8]; // cols of RB
 712     for (int i = 0; i < 8; i++) {
 713         u[i] = RA >> (i*8);
 714         v[i] = RBt >> (i*8);
 715     }
 716     uint64_t x = 0;
 717     for (int i = 0; i < 64; i++) {
 718         if ((u[i / 8] & v[i % 8]) != 0)
 719             x |= 1LL << i;
 720     }
 721     return x;
 722 }
 723
 724 ```