7 * ternlogi <https://bugs.libre-soc.org/show_bug.cgi?id=745>
8 * grev <https://bugs.libre-soc.org/show_bug.cgi?id=755>
9 * GF2^M <https://bugs.libre-soc.org/show_bug.cgi?id=782>
16 pseudocode: [[openpower/isa/bitmanip]]
18 this extension amalgamates bitmanipulation primitives from many sources,
19 including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX.
20 Also included are DSP/Multimedia operations suitable for Audio/Video.
21 Vectorisation and SIMD are removed: these are straight scalar (element)
22 operations making them suitable for embedded applications. Vectorisation
23 Context is provided by [[openpower/sv]].
25 When combined with SV, scalar variants of bitmanip operations found in
26 VSX are added so that the Packed SIMD aspects of VSX may be retired as
27 "legacy" in the far future (10 to 20 years). Also, VSX is hundreds of
28 opcodes, requires 128 bit pathways, and is wholly unsuited to low power
29 or embedded scenarios.
31 ternlogv is experimental and is the only operation that may be considered
32 a "Packed SIMD". It is added as a variant of the already well-justified
33 ternlog operation (done in AVX512 as an immediate only) "because it
34 looks fun". As it is based on the LUT4 concept it will allow accelerated
35 emulation of FPGAs. Other vendors of ISAs are buying FPGA companies to
36 achieve similar objectives.
38 general-purpose Galois Field 2^M operations are added so as to avoid
39 huge custom opcode proliferation across many areas of Computer Science.
40 however for convenience and also to avoid setup costs, some of the more
41 common operations (clmul, crc32) are also added. The expectation is
42 that these operations would all be covered by the same pipeline.
44 note that there are brownfield spaces below that could incorporate
45 some of the set-before-first and other scalar operations listed in
47 [[sv/vector_ops]], [[sv/int_fp_mv]] and the [[sv/av_opcodes]] as well as
48 [[sv/setvl]], [[sv/svstep]], [[sv/remap]]
52 * <https://en.wikiversity.org/wiki/Reed%E2%80%93Solomon_codes_for_coders>
53 * <https://maths-people.anu.edu.au/~brent/pd/rpb232tr.pdf>
57 two major opcodes are needed
59 ternlog has its own major opcode
61 | 29.30 |31| name | Form |
62 | ------ |--| --------- | ---- |
63 | 0 0 |Rc| ternlogi | TLI-Form |
64 | 0 1 | | crternlogi | TLI-Form |
65 | 1 iv | | grevlogi | TLI-Form |
67 2nd major opcode for other bitmanip: minor opcode allocation
70 | ------ |--| --------- |
72 | -00 |1 | binary lut |
74 | -01 |1 | swizzle mv/fmv |
83 | dest | src1 | subop | op |
84 | ---- | ---- | ----- | -------- |
85 | RT | RA | .. | bmatflip |
89 | dest | src1 | src2 | subop | op |
90 | ---- | ---- | ---- | ----- | -------- |
91 | RT | RA | RB | or | bmatflip |
92 | RT | RA | RB | xor | bmatflip |
93 | RT | RA | RB | | grev |
94 | RT | RA | RB | | clmul\* |
95 | RT | RA | RB | | gorc |
96 | RT | RA | RB | shuf | shuffle |
97 | RT | RA | RB | unshuf| shuffle |
98 | RT | RA | RB | width | xperm |
99 | RT | RA | RB | type | av minmax |
100 | RT | RA | RB | | av abs avgadd |
101 | RT | RA | RB | type | vmask ops |
102 | RT | RA | RB | type | abs accumulate (overwrite) |
110 TODO: convert all instructions to use RT and not RS
112 | 0.5|6.10|11.15|16.20 |21..25 | 26....30 |31| name | Form |
113 | -- | -- | --- | --- | ----- | -------- |--| ------ | -------- |
114 | NN | RT | RA |itype/| im0-4 | im5-7 00 |0 | xpermi | TLI-Form |
115 | NN | RT | RA | RB | RC | nh 00 00 |1 | binlut | VA-Form |
116 | NN | RT | RA | RB | /BFA/ | 0 01 00 |1 | bincrflut | VA-Form |
117 | NN | | | | | 1 01 00 |1 | svindex | TODO |
118 | NN | | | | | - 10 00 |1 | rsvd | |
119 | NN | | | | | 0 11 00 |1 | svshape | SVM-Form |
120 | NN | | | | | 1 11 00 |1 | svremap | SVRM-Form |
121 | NN | RT | RA | RB | im0-4 | im5-7 01 |0 | grevlog | TLI-Form |
122 | NN | RT | RA | RB | im0-4 | im5-7 01 |1 | grevlogw | TLI-Form |
123 | NN | RT | RA | RB | RC | mode 010 |Rc| bitmask\* | VA2-Form |
124 | NN |FRS | d1 | d0 | d0 | 00 011 |d2| fmvis | DX-Form |
125 | NN |FRS | d1 | d0 | d0 | 01 011 |d2| fishmv | DX-Form |
126 | NN | | | | | 10 011 |Rc| svstep | SVL-Form |
127 | NN | | | | | 11 011 |Rc| setvl | SVL-Form |
128 | NN | | | | | ---- 110 | | 1/2 ops | other table [1] |
129 | NN | RT | RA | RB | RC | 11 110 |Rc| bmrev | VA2-Form |
130 | NN | RT | RA | RB | sh0-4 | sh5 1 111 |Rc| bmrevi | MDS-Form |
134 ops (note that av avg and abs as well as vec scalar mask
135 are included here [[sv/vector_ops]], and
136 the [[sv/av_opcodes]])
138 | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name | Form |
139 | -- | -- | --- | --- | -- | ----- | -------- |--| ---- | ------- |
140 | NN | RS | me | sh | SH | ME 0 | nn00 110 |Rc| bmopsi | BM-Form |
141 | NN | RS | RA | sh | SH | 0 1 | nn00 110 |Rc| bmopsi | XB-Form |
142 | NN | RS | RA |im04 | im5| 1 1 | im67 00 110 |Rc| bmatxori | TODO |
143 | NN | RT | RA | RB | 1 | 00 | 0001 110 |Rc| cldiv | X-Form |
144 | NN | RT | RA | RB | 1 | 01 | 0001 110 |Rc| clmod | X-Form |
145 | NN | RT | RA | | 1 | 10 | 0001 110 |Rc| clmulh | X-Form |
146 | NN | RT | RA | RB | 1 | 11 | 0001 110 |Rc| clmul | X-Form |
147 | NN | RT | RA | RB | 0 | 00 | 0001 110 |Rc| vec sbfm | X-Form |
148 | NN | RT | RA | RB | 0 | 01 | 0001 110 |Rc| vec sofm | X-Form |
149 | NN | RT | RA | RB | 0 | 10 | 0001 110 |Rc| vec sifm | X-Form |
150 | NN | RT | RA | RB | 0 | 11 | 0001 110 |Rc| vec cprop | X-Form |
151 | NN | | | | | -0 | 0101 110 |Rc| crfbinlog | {TODO} |
152 | NN | | | | | -1 | 0101 110 |Rc| rsvd | |
153 | NN | RT | RA | RB | 0 | itype | 1001 110 |Rc| av minmax | X-Form |
154 | NN | RT | RA | RB | 1 | 00 | 1001 110 |Rc| av abss | X-Form |
155 | NN | RT | RA | RB | 1 | 01 | 1001 110 |Rc| av absu | X-Form |
156 | NN | RT | RA | RB | 1 | 10 | 1001 110 |Rc| av avgadd | X-Form |
157 | NN | RT | RA | RB | 1 | 11 | 1001 110 |Rc| grevlutr | X-Form |
158 | NN | RT | RA | RB | 0 | itype | 1101 110 |Rc| shadd | X-Form |
159 | NN | RT | RA | RB | 1 | itype | 1101 110 |Rc| shadduw | X-Form |
160 | NN | RT | RA | RB | 0 | 00 | 0010 110 |Rc| rsvd | |
161 | NN | RS | RA | sh | SH | 00 | 1010 110 |Rc| rsvd | |
162 | NN | RT | RA | RB | 0 | 00 | 0110 110 |Rc| rsvd | |
163 | NN | RS | RA | SH | 0 | 00 | 1110 110 |Rc| rsvd | |
164 | NN | RT | RA | RB | 1 | 00 | 1110 110 |Rc| rsvd | |
165 | NN | RT | RA | RB | 0 | 01 | 0010 110 |Rc| rsvd | |
166 | NN | RT | RA | RB | 1 | 01 | 0010 110 |Rc| clmulr | X-Form |
167 | NN | RS | RA | sh | SH | 01 | 1010 110 |Rc| rsvd | |
168 | NN | RT | RA | RB | 0 | 01 | 0110 110 |Rc| rsvd | |
169 | NN | RS | RA | SH | 0 | 01 | 1110 110 |Rc| rsvd | |
170 | NN | RT | RA | RB | 1 | 01 | 1110 110 |Rc| absdu | X-Form |
171 | NN | RS | RA | RB | 0 | 10 | 0010 110 |Rc| bmator | X-Form |
172 | NN | RS | RA | RB | 0 | 10 | 0110 110 |Rc| bmatand | X-Form |
173 | NN | RS | RA | RB | 0 | 10 | 1010 110 |Rc| bmatxor | X-Form |
174 | NN | RS | RA | RB | 0 | 10 | 1110 110 |Rc| bmatflip | X-Form |
175 | NN | RT | RA | RB | 1 | 10 | 0010 110 |Rc| xpermn | X-Form |
176 | NN | RT | RA | RB | 1 | 10 | 0110 110 |Rc| xpermb | X-Form |
177 | NN | RT | RA | RB | 1 | 10 | 1010 110 |Rc| xpermh | X-Form |
178 | NN | RT | RA | RB | 1 | 10 | 1110 110 |Rc| xpermw | X-Form |
179 | NN | RT | RA | RB | 0 | 11 | 1110 110 |Rc| abssa | X-Form |
180 | NN | RT | RA | RB | 1 | 11 | 1110 110 |Rc| absua | X-Form |
181 | NN | | | | | | --11 110 |Rc| bmrev | VA2-Form |
183 # binary and ternary bitops
185 Similar to FPGA LUTs: for two (binary) or three (ternary) inputs take
186 bits from each input, concatenate them and perform a lookup into a
187 table using an 8-8-bit immediate (for the ternary instructions), or in
188 another register (4-bit for the binary instructions). The binary lookup
189 instructions have CR Field lookup variants due to CR Fields being 4 bit.
192 [vpternlogd/vpternlogq](https://www.felixcloutier.com/x86/vpternlogd:vpternlogq)
197 | 0.5|6.10|11.15|16.20| 21..28|29.30|31|
198 | -- | -- | --- | --- | ----- | --- |--|
199 | NN | RT | RA | RB | im0-7 | 00 |Rc|
202 idx = c << 2 | b << 1 | a
203 return imm[idx] # idx by LSB0 order
206 RT[i] = lut3(imm, RB[i], RA[i], RT[i])
210 Binary lookup is a dynamic LUT2 version of ternlogi. Firstly, the
211 lookup table is 4 bits wide not 8 bits, and secondly the lookup
212 table comes from a register not an immediate.
214 | 0.5|6.10|11.15|16.20| 21..25|26..31 | Form |
215 | -- | -- | --- | --- | ----- |--------|---------|
216 | NN | RT | RA | RB | RC |nh 00001| VA-Form |
217 | NN | RT | RA | RB | /BFA/ |0 01001| VA-Form |
219 For binlut, the 4-bit LUT may be selected from either the high nibble
220 or the low nibble of the first byte of RC:
224 return imm[idx] # idx by LSB0 order
226 imm = (RC>>(nh*4))&0b1111
228 RT[i] = lut2(imm, RB[i], RA[i])
230 For bincrlut, `BFA` selects the 4-bit CR Field as the LUT2:
233 RT[i] = lut2(CRs{BFA}, RB[i], RA[i])
235 When Vectorised with SVP64, as usual both source and destination may be
238 *Programmer's note: a dynamic ternary lookup may be synthesised from
239 a pair of `binlut` instructions followed by a `ternlogi` to select which
240 to merge. Use `nh` to select which nibble to use as the lookup table
241 from the RC source register (`nh=1` nibble high), i.e. keeping
242 an 8-bit LUT3 in RC, the first `binlut` instruction may set nh=0 and
247 another mode selection would be CRs not Ints.
249 | 0.5|6.8 | 9.11|12.14|15.17|18.20|21.28 | 29.30|31|
250 | -- | -- | --- | --- | --- |-----|----- | -----|--|
251 | NN | BT | BA | BB | BC |m0-2 | imm | 01 |m3|
255 a,b,c = CRs[BA][i], CRs[BB][i], CRs[BC][i])
256 if mask[i] CRs[BT][i] = lut3(imm, a, b, c)
258 This instruction is remarkably similar to the existing crops, `crand` etc.
259 which have been noted to be a 4-bit (binary) LUT. In effect `crternlogi`
260 is the ternary LUT version of crops, having an 8-bit LUT.
264 With ternary (LUT3) dynamic instructions being very costly,
265 and CR Fields being only 4 bit, a binary (LUT2) variant is better
267 | 0.5|6.8 | 9.11|12.14|15.17|18.22|23...30 |31|
268 | -- | -- | --- | --- | --- |-----| --------|--|
269 | NN | BT | BA | BB | BC |m0-m2|00101110 |m3|
273 a,b = CRs[BA][i], CRs[BB][i])
274 if mask[i] CRs[BT][i] = lut2(CRs[BC], a, b)
276 When SVP64 Vectorised any of the 4 operands may be Scalar or
277 Vector, including `BC` meaning that multiple different dynamic
278 lookups may be performed with a single instruction.
280 *Programmer's note: just as with binlut and ternlogi, a pair
281 of crbinlog instructions followed by a merging crternlogi may
282 be deployed to synthesise dynamic ternary (LUT3) CR Field
289 required for the [[sv/av_opcodes]]
291 signed and unsigned min/max for integer. this is sort-of partly
292 synthesiseable in [[sv/svp64]] with pred-result as long as the dest reg
293 is one of the sources, but not both signed and unsigned. when the dest
294 is also one of the srces and the mv fails due to the CR bittest failing
295 this will only overwrite the dest where the src is greater (or less).
297 signed/unsigned min/max gives more flexibility.
301 * XO=0001001110, itype=0b00 min, unsigned
302 * XO=0101001110, itype=0b01 min, signed
303 * XO=0011001110, itype=0b10 max, unsigned
304 * XO=0111001110, itype=0b11 max, signed
308 uint_xlen_t mins(uint_xlen_t rs1, uint_xlen_t rs2)
309 { return (int_xlen_t)rs1 < (int_xlen_t)rs2 ? rs1 : rs2;
311 uint_xlen_t maxs(uint_xlen_t rs1, uint_xlen_t rs2)
312 { return (int_xlen_t)rs1 > (int_xlen_t)rs2 ? rs1 : rs2;
314 uint_xlen_t minu(uint_xlen_t rs1, uint_xlen_t rs2)
315 { return rs1 < rs2 ? rs1 : rs2;
317 uint_xlen_t maxu(uint_xlen_t rs1, uint_xlen_t rs2)
318 { return rs1 > rs2 ? rs1 : rs2;
324 required for the [[sv/av_opcodes]], these exist in Packed SIMD (VSX)
328 uint_xlen_t intavg(uint_xlen_t rs1, uint_xlen_t rs2) {
329 return (rs1 + rs2 + 1) >> 1:
335 required for the [[sv/av_opcodes]], these exist in Packed SIMD (VSX)
339 uint_xlen_t absdu(uint_xlen_t rs1, uint_xlen_t rs2) {
340 return (src1 > src2) ? (src1-src2) : (src2-src1)
346 required for the [[sv/av_opcodes]], these are needed for motion estimation.
347 both are overwrite on RS.
350 uint_xlen_t uintabsacc(uint_xlen_t rs, uint_xlen_t ra, uint_xlen_t rb) {
351 return rs + (src1 > src2) ? (src1-src2) : (src2-src1)
353 uint_xlen_t intabsacc(uint_xlen_t rs, int_xlen_t ra, int_xlen_t rb) {
354 return rs + (src1 > src2) ? (src1-src2) : (src2-src1)
358 For SVP64, the twin Elwidths allows e.g. a 16 bit accumulator for 8 bit
359 differences. Form is `RM-1P-3S1D` where RS-as-source has a separate
360 SVP64 designation from RS-as-dest. This gives a limited range of
361 non-overwrite capability.
365 Power ISA is missing LD/ST with shift, which is present in both ARM and x86.
366 Too complex to add more LD/ST, a compromise is to add shift-and-add.
367 Replaces a pair of explicit instructions in hot-loops.
370 uint_xlen_t shadd(uint_xlen_t rs1, uint_xlen_t rs2, uint8_t sh) {
371 return (rs1 << (sh+1)) + rs2;
374 uint_xlen_t shadduw(uint_xlen_t rs1, uint_xlen_t rs2, uint8_t sh) {
375 uint_xlen_t rs1z = rs1 & 0xFFFFFFFF;
376 return (rs1z << (sh+1)) + rs2;
382 based on RV bitmanip singlebit set, instruction format similar to shift
383 [[isa/fixedshift]]. bmext is actually covered already (shift-with-mask
384 rldicl but only immediate version). however bitmask-invert is not,
385 and set/clr are not covered, although they can use the same Shift ALU.
387 bmext (RB) version is not the same as rldicl because bmext is a right
388 shift by RC, where rldicl is a left rotate. for the immediate version
389 this does not matter, so a bmexti is not required. bmrev however there
390 is no direct equivalent and consequently a bmrevi is required.
392 bmset (register for mask amount) is particularly useful for creating
393 predicate masks where the length is a dynamic runtime quantity.
394 bmset(RA=0, RB=0, RC=mask) will produce a run of ones of length "mask"
395 in a single instruction without needing to initialise or depend on any
398 | 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name |
399 | -- | -- | --- | --- | --- | ------- |--| ----- |
400 | NN | RS | RA | RB | RC | mode 010 |Rc| bm\* |
402 Immediate-variant is an overwrite form:
404 | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name |
405 | -- | -- | --- | --- | -- | ----- | -------- |--| ---- |
406 | NN | RS | RB | sh | SH | itype | 1000 110 |Rc| bm\*i |
412 mask_a = ((1 << x) - 1) & ((1 << 64) - 1)
413 mask_b = ((1 << y) - 1) & ((1 << 64) - 1)
418 mask_a = ((1 << x) - 1) & ((1 << 64) - 1)
419 mask_b = (~((1 << y) - 1)) & ((1 << 64) - 1)
420 return mask_a ^ mask_b
423 uint_xlen_t bmset(RS, RB, sh)
425 int shamt = RB & (XLEN - 1);
427 return RS | (mask << shamt);
430 uint_xlen_t bmclr(RS, RB, sh)
432 int shamt = RB & (XLEN - 1);
434 return RS & ~(mask << shamt);
437 uint_xlen_t bminv(RS, RB, sh)
439 int shamt = RB & (XLEN - 1);
441 return RS ^ (mask << shamt);
444 uint_xlen_t bmext(RS, RB, sh)
446 int shamt = RB & (XLEN - 1);
448 return mask & (RS >> shamt);
452 bitmask extract with reverse. can be done by bit-order-inverting all
453 of RB and getting bits of RB from the opposite end.
455 when RA is zero, no shift occurs. this makes bmextrev useful for
456 simply reversing all bits of a register.
460 rev[0:msb] = rb[msb:0];
463 uint_xlen_t bmrevi(RA, RB, sh)
466 if (RA != 0) shamt = (GPR(RA) & (XLEN - 1));
467 shamt = (XLEN-1)-shamt; # shift other end
468 brb = bitreverse(GPR(RB)) # swap LSB-MSB
470 return mask & (brb >> shamt);
473 uint_xlen_t bmrev(RA, RB, RC) {
474 return bmrevi(RA, RB, GPR(RC) & 0b111111);
478 | 0.5|6.10|11.15|16.20|21.26| 27..30 |31| name | Form |
479 | -- | -- | --- | --- | --- | ------- |--| ------ | -------- |
480 | NN | RT | RA | RB | sh | 1111 |Rc| bmrevi | MDS-Form |
482 | 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name | Form |
483 | -- | -- | --- | --- | --- | ------- |--| ------ | -------- |
484 | NN | RT | RA | RB | RC | 11110 |Rc| bmrev | VA2-Form |
486 # grevlut <a name="grevlut"> </a>
488 ([3x lower latency alternative](grev_gorc_design/) which is
489 not equivalent and has limited constant-generation capability)
491 generalised reverse combined with a pair of LUT2s and allowing
492 a constant `0b0101...0101` when RA=0, and an option to invert
493 (including when RA=0, giving a constant 0b1010...1010 as the
494 initial value) provides a wide range of instructions
495 and a means to set hundreds of regular 64 bit patterns with one
496 single 32 bit instruction.
498 the two LUT2s are applied left-half (when not swapping)
499 and right-half (when swapping) so as to allow a wider
502 <img src="/openpower/sv/grevlut2x2.jpg" width=700 />
504 * A value of `0b11001010` for the immediate provides
505 the functionality of a standard "grev".
506 * `0b11101110` provides gorc
508 grevlut should be arranged so as to produce the constants
509 needed to put into bext (bitextract) so as in turn to
510 be able to emulate x86 pmovmask instructions
511 <https://www.felixcloutier.com/x86/pmovmskb>.
512 This only requires 2 instructions (grevlut, bext).
514 Note that if the mask is required to be placed
515 directly into CR Fields (for use as CR Predicate
516 masks rather than a integer mask) then sv.cmpi or sv.ori
517 may be used instead, bearing in mind that sv.ori
518 is a 64-bit instruction, and `VL` must have been
519 set to the required length:
521 sv.ori./elwid=8 r10.v, r10.v, 0
523 The following settings provide the required mask constants:
525 | RA=0 | RB | imm | iv | result |
526 | ------- | ------- | ---------- | -- | ---------- |
527 | 0x555.. | 0b10 | 0b01101100 | 0 | 0x111111... |
528 | 0x555.. | 0b110 | 0b01101100 | 0 | 0x010101... |
529 | 0x555.. | 0b1110 | 0b01101100 | 0 | 0x00010001... |
530 | 0x555.. | 0b10 | 0b11000110 | 1 | 0x88888... |
531 | 0x555.. | 0b110 | 0b11000110 | 1 | 0x808080... |
532 | 0x555.. | 0b1110 | 0b11000110 | 1 | 0x80008000... |
534 Better diagram showing the correct ordering of shamt (RB). A LUT2
535 is applied to all locations marked in red using the first 4
536 bits of the immediate, and a separate LUT2 applied to all
537 locations in green using the upper 4 bits of the immediate.
539 <img src="/openpower/sv/grevlut.png" width=700 />
541 demo code [[openpower/sv/grevlut.py]]
546 return imm[idx] # idx by LSB0 order
548 dorow(imm8, step_i, chunksize, us32b):
549 for j in 0 to 31 if is32b else 63:
550 if (j&chunk_size) == 0
554 step_o[j] = lut2(imm, step_i[j], step_i[j ^ chunk_size])
557 uint64_t grevlut(uint64_t RA, uint64_t RB, uint8 imm, bool iv, bool is32b)
559 uint64_t x = 0x5555_5555_5555_5555;
560 if (RA != 0) x = GPR(RA);
562 int shamt = RB & 31 if is32b else 63
563 for i in 0 to (6-is32b)
565 if (shamt & step) x = dorow(imm, x, step, is32b)
570 A variant may specify different LUT-pairs per row,
571 using one byte of RB for each. If it is desired that
572 a particular row-crossover shall not be applied it is
573 a simple matter to set the appropriate LUT-pair in RB
574 to effect an identity transform for that row (`0b11001010`).
577 uint64_t grevlutr(uint64_t RA, uint64_t RB, bool iv, bool is32b)
579 uint64_t x = 0x5555_5555_5555_5555;
580 if (RA != 0) x = GPR(RA);
582 for i in 0 to (6-is32b)
584 imm = (RB>>(i*8))&0xff
585 x = dorow(imm, x, step, is32b)
591 | 0.5|6.10|11.15|16.20 |21..28 | 29.30|31| name | Form |
592 | -- | -- | --- | --- | ----- | -----|--| ------ | ----- |
593 | NN | RT | RA | s0-4 | im0-7 | 1 iv |s5| grevlogi | |
594 | NN | RT | RA | RB | im0-7 | 01 |0 | grevlog | |
595 | NN | RT | RA | RB | im0-7 | 01 |1 | grevlogw | |
599 based on RV bitmanip.
601 RA contains a vector of indices to select parts of RB to be
602 copied to RT. The immediate-variant allows up to an 8 bit
603 pattern (repeated) to be targetted at different parts of RT.
605 xperm shares some similarity with one of the uses of bmator
606 in that xperm indices are binary addressing where bitmator
607 may be considered to be unary addressing.
610 uint_xlen_t xpermi(uint8_t imm8, uint_xlen_t RB, int sz_log2)
613 uint_xlen_t sz = 1LL << sz_log2;
614 uint_xlen_t mask = (1LL << sz) - 1;
615 uint_xlen_t RA = imm8 | imm8<<8 | ... | imm8<<56;
616 for (int i = 0; i < XLEN; i += sz) {
617 uint_xlen_t pos = ((RA >> i) & mask) << sz_log2;
619 r |= ((RB >> pos) & mask) << i;
623 uint_xlen_t xperm(uint_xlen_t RA, uint_xlen_t RB, int sz_log2)
626 uint_xlen_t sz = 1LL << sz_log2;
627 uint_xlen_t mask = (1LL << sz) - 1;
628 for (int i = 0; i < XLEN; i += sz) {
629 uint_xlen_t pos = ((RA >> i) & mask) << sz_log2;
631 r |= ((RB >> pos) & mask) << i;
635 uint_xlen_t xperm_n (uint_xlen_t RA, uint_xlen_t RB)
636 { return xperm(RA, RB, 2); }
637 uint_xlen_t xperm_b (uint_xlen_t RA, uint_xlen_t RB)
638 { return xperm(RA, RB, 3); }
639 uint_xlen_t xperm_h (uint_xlen_t RA, uint_xlen_t RB)
640 { return xperm(RA, RB, 4); }
641 uint_xlen_t xperm_w (uint_xlen_t RA, uint_xlen_t RB)
642 { return xperm(RA, RB, 5); }
647 bmatflip and bmatxor is found in the Cray XMT, and in x86 is known
648 as GF2P8AFFINEQB. uses:
650 * <https://gist.github.com/animetosho/d3ca95da2131b5813e16b5bb1b137ca0>
651 * SM4, Reed Solomon, RAID6
652 <https://stackoverflow.com/questions/59124720/what-are-the-avx-512-galois-field-related-instructions-for>
653 * Vector bit-reverse <https://reviews.llvm.org/D91515?id=305411>
654 * Affine Inverse <https://github.com/HJLebbink/asm-dude/wiki/GF2P8AFFINEINVQB>
656 | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name | Form |
657 | -- | -- | --- | --- | -- | ----- | -------- |--| ---- | ------- |
658 | NN | RS | RA |im04 | im5| 1 1 | im67 00 110 |Rc| bmatxori | TODO |
662 uint64_t bmatflip(uint64_t RA)
671 uint64_t bmatxori(uint64_t RS, uint64_t RA, uint8_t imm) {
673 uint64_t RAt = bmatflip(RA);
674 uint8_t u[8]; // rows of RS
675 uint8_t v[8]; // cols of RA
676 for (int i = 0; i < 8; i++) {
681 for (int i = 0; i < 64; i++) {
682 bit = (imm >> (i%8)) & 1;
683 bit ^= pcnt(u[i / 8] & v[i % 8]) & 1;
689 uint64_t bmatxor(uint64_t RA, uint64_t RB) {
690 return bmatxori(RA, RB, 0xff)
693 uint64_t bmator(uint64_t RA, uint64_t RB) {
695 uint64_t RBt = bmatflip(RB);
696 uint8_t u[8]; // rows of RA
697 uint8_t v[8]; // cols of RB
698 for (int i = 0; i < 8; i++) {
703 for (int i = 0; i < 64; i++) {
704 if ((u[i / 8] & v[i % 8]) != 0)
710 uint64_t bmatand(uint64_t RA, uint64_t RB) {
712 uint64_t RBt = bmatflip(RB);
713 uint8_t u[8]; // rows of RA
714 uint8_t v[8]; // cols of RB
715 for (int i = 0; i < 8; i++) {
720 for (int i = 0; i < 64; i++) {
721 if ((u[i / 8] & v[i % 8]) == 0xff)
728 # Introduction to Carry-less and GF arithmetic
730 * obligatory xkcd <https://xkcd.com/2595/>
732 There are three completely separate types of Galois-Field-based arithmetic
733 that we implement which are not well explained even in introductory
734 literature. A slightly oversimplified explanation is followed by more
735 accurate descriptions:
737 * `GF(2)` carry-less binary arithmetic. this is not actually a Galois Field,
738 but is accidentally referred to as GF(2) - see below as to why.
739 * `GF(p)` modulo arithmetic with a Prime number, these are "proper"
741 * `GF(2^N)` carry-less binary arithmetic with two limits: modulo a power-of-2
742 (2^N) and a second "reducing" polynomial (similar to a prime number), these
743 are said to be GF(2^N) arithmetic.
745 further detailed and more precise explanations are provided below
747 * **Polynomials with coefficients in `GF(2)`**
748 (aka. Carry-less arithmetic -- the `cl*` instructions).
749 This isn't actually a Galois Field, but its coefficients are. This is
750 basically binary integer addition, subtraction, and multiplication like
751 usual, except that carries aren't propagated at all, effectively turning
752 both addition and subtraction into the bitwise xor operation. Division and
753 remainder are defined to match how addition and multiplication works.
754 * **Galois Fields with a prime size**
755 (aka. `GF(p)` or Prime Galois Fields -- the `gfp*` instructions).
756 This is basically just the integers mod `p`.
757 * **Galois Fields with a power-of-a-prime size**
758 (aka. `GF(p^n)` or `GF(q)` where `q == p^n` for prime `p` and
760 We only implement these for `p == 2`, called Binary Galois Fields
761 (`GF(2^n)` -- the `gfb*` instructions).
762 For any prime `p`, `GF(p^n)` is implemented as polynomials with
763 coefficients in `GF(p)` and degree `< n`, where the polynomials are the
764 remainders of dividing by a specificly chosen polynomial in `GF(p)` called
765 the Reducing Polynomial (we will denote that by `red_poly`). The Reducing
766 Polynomial must be an irreducable polynomial (like primes, but for
767 polynomials), as well as have degree `n`. All `GF(p^n)` for the same `p`
768 and `n` are isomorphic to each other -- the choice of `red_poly` doesn't
769 affect `GF(p^n)`'s mathematical shape, all that changes is the specific
770 polynomials used to implement `GF(p^n)`.
772 Many implementations and much of the literature do not make a clear
773 distinction between these three categories, which makes it confusing
774 to understand what their purpose and value is.
776 * carry-less multiply is extremely common and is used for the ubiquitous
777 CRC32 algorithm. [TODO add many others, helps justify to ISA WG]
778 * GF(2^N) forms the basis of Rijndael (the current AES standard) and
779 has significant uses throughout cryptography
780 * GF(p) is the basis again of a significant quantity of algorithms
781 (TODO, list them, jacob knows what they are), even though the
782 modulo is limited to be below 64-bit (size of a scalar int)
784 # Instructions for Carry-less Operations
786 aka. Polynomials with coefficients in `GF(2)`
788 Carry-less addition/subtraction is simply XOR, so a `cladd`
789 instruction is not provided since the `xor[i]` instruction can be used instead.
791 These are operations on polynomials with coefficients in `GF(2)`, with the
792 polynomial's coefficients packed into integers with the following algorithm:
795 [[!inline pagenames="gf_reference/pack_poly.py" raw="yes"]]
798 ## Carry-less Multiply Instructions
801 see <https://en.wikipedia.org/wiki/CLMUL_instruction_set> and
802 <https://www.felixcloutier.com/x86/pclmulqdq> and
803 <https://en.m.wikipedia.org/wiki/Carry-less_product>
805 They are worth adding as their own non-overwrite operations
806 (in the same pipeline).
808 ### `clmul` Carry-less Multiply
811 [[!inline pagenames="gf_reference/clmul.py" raw="yes"]]
814 ### `clmulh` Carry-less Multiply High
817 [[!inline pagenames="gf_reference/clmulh.py" raw="yes"]]
820 ### `clmulr` Carry-less Multiply (Reversed)
822 Useful for CRCs. Equivalent to bit-reversing the result of `clmul` on
826 [[!inline pagenames="gf_reference/clmulr.py" raw="yes"]]
829 ## `clmadd` Carry-less Multiply-Add
832 clmadd RT, RA, RB, RC
836 (RT) = clmul((RA), (RB)) ^ (RC)
839 ## `cltmadd` Twin Carry-less Multiply-Add (for FFTs)
841 Used in combination with SV FFT REMAP to perform a full Discrete Fourier
842 Transform of Polynomials over GF(2) in-place. Possible by having 3-in 2-out,
843 to avoid the need for a temp register. RS is written to as well as RT.
845 Note: Polynomials over GF(2) are a Ring rather than a Field, so, because the
846 definition of the Inverse Discrete Fourier Transform involves calculating a
847 multiplicative inverse, which may not exist in every Ring, therefore the
848 Inverse Discrete Fourier Transform may not exist. (AFAICT the number of inputs
849 to the IDFT must be odd for the IDFT to be defined for Polynomials over GF(2).
850 TODO: check with someone who knows for sure if that's correct.)
853 cltmadd RT, RA, RB, RC
856 TODO: add link to explanation for where `RS` comes from.
861 # read all inputs before writing to any outputs in case
862 # an input overlaps with an output register.
863 (RT) = clmul(a, (RB)) ^ c
867 ## `cldivrem` Carry-less Division and Remainder
869 `cldivrem` isn't an actual instruction, but is just used in the pseudo-code
870 for other instructions.
873 [[!inline pagenames="gf_reference/cldivrem.py" raw="yes"]]
876 ## `cldiv` Carry-less Division
885 q, r = cldivrem(n, d, width=XLEN)
889 ## `clrem` Carry-less Remainder
898 q, r = cldivrem(n, d, width=XLEN)
902 # Instructions for Binary Galois Fields `GF(2^m)`
906 * <https://courses.csail.mit.edu/6.857/2016/files/ffield.py>
907 * <https://engineering.purdue.edu/kak/compsec/NewLectures/Lecture7.pdf>
908 * <https://foss.heptapod.net/math/libgf2/-/blob/branch/default/src/libgf2/gf2.py>
910 Binary Galois Field addition/subtraction is simply XOR, so a `gfbadd`
911 instruction is not provided since the `xor[i]` instruction can be used instead.
913 ## `GFBREDPOLY` SPR -- Reducing Polynomial
915 In order to save registers and to make operations orthogonal with standard
916 arithmetic, the reducing polynomial is stored in a dedicated SPR `GFBREDPOLY`.
917 This also allows hardware to pre-compute useful parameters (such as the
918 degree, or look-up tables) based on the reducing polynomial, and store them
919 alongside the SPR in hidden registers, only recomputing them whenever the SPR
920 is written to, rather than having to recompute those values for every
923 Because Galois Fields require the reducing polynomial to be an irreducible
924 polynomial, that guarantees that any polynomial of `degree > 1` must have
925 the LSB set, since otherwise it would be divisible by the polynomial `x`,
926 making it reducible, making whatever we're working on no longer a Field.
927 Therefore, we can reuse the LSB to indicate `degree == XLEN`.
930 [[!inline pagenames="gf_reference/decode_reducing_polynomial.py" raw="yes"]]
933 ## `gfbredpoly` -- Set the Reducing Polynomial SPR `GFBREDPOLY`
935 unless this is an immediate op, `mtspr` is completely sufficient.
938 [[!inline pagenames="gf_reference/gfbredpoly.py" raw="yes"]]
941 ## `gfbmul` -- Binary Galois Field `GF(2^m)` Multiplication
948 [[!inline pagenames="gf_reference/gfbmul.py" raw="yes"]]
951 ## `gfbmadd` -- Binary Galois Field `GF(2^m)` Multiply-Add
954 gfbmadd RT, RA, RB, RC
958 [[!inline pagenames="gf_reference/gfbmadd.py" raw="yes"]]
961 ## `gfbtmadd` -- Binary Galois Field `GF(2^m)` Twin Multiply-Add (for FFT)
963 Used in combination with SV FFT REMAP to perform a full `GF(2^m)` Discrete
964 Fourier Transform in-place. Possible by having 3-in 2-out, to avoid the need
965 for a temp register. RS is written to as well as RT.
968 gfbtmadd RT, RA, RB, RC
971 TODO: add link to explanation for where `RS` comes from.
976 # read all inputs before writing to any outputs in case
977 # an input overlaps with an output register.
978 (RT) = gfbmadd(a, (RB), c)
979 # use gfbmadd again since it reduces the result
980 (RS) = gfbmadd(a, 1, c) # "a * 1 + c"
983 ## `gfbinv` -- Binary Galois Field `GF(2^m)` Inverse
990 [[!inline pagenames="gf_reference/gfbinv.py" raw="yes"]]
993 # Instructions for Prime Galois Fields `GF(p)`
995 ## `GFPRIME` SPR -- Prime Modulus For `gfp*` Instructions
997 ## `gfpadd` Prime Galois Field `GF(p)` Addition
1004 [[!inline pagenames="gf_reference/gfpadd.py" raw="yes"]]
1007 the addition happens on infinite-precision integers
1009 ## `gfpsub` Prime Galois Field `GF(p)` Subtraction
1016 [[!inline pagenames="gf_reference/gfpsub.py" raw="yes"]]
1019 the subtraction happens on infinite-precision integers
1021 ## `gfpmul` Prime Galois Field `GF(p)` Multiplication
1028 [[!inline pagenames="gf_reference/gfpmul.py" raw="yes"]]
1031 the multiplication happens on infinite-precision integers
1033 ## `gfpinv` Prime Galois Field `GF(p)` Invert
1039 Some potential hardware implementations are found in:
1040 <https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.90.5233&rep=rep1&type=pdf>
1043 [[!inline pagenames="gf_reference/gfpinv.py" raw="yes"]]
1046 ## `gfpmadd` Prime Galois Field `GF(p)` Multiply-Add
1049 gfpmadd RT, RA, RB, RC
1053 [[!inline pagenames="gf_reference/gfpmadd.py" raw="yes"]]
1056 the multiplication and addition happens on infinite-precision integers
1058 ## `gfpmsub` Prime Galois Field `GF(p)` Multiply-Subtract
1061 gfpmsub RT, RA, RB, RC
1065 [[!inline pagenames="gf_reference/gfpmsub.py" raw="yes"]]
1068 the multiplication and subtraction happens on infinite-precision integers
1070 ## `gfpmsubr` Prime Galois Field `GF(p)` Multiply-Subtract-Reversed
1073 gfpmsubr RT, RA, RB, RC
1077 [[!inline pagenames="gf_reference/gfpmsubr.py" raw="yes"]]
1080 the multiplication and subtraction happens on infinite-precision integers
1082 ## `gfpmaddsubr` Prime Galois Field `GF(p)` Multiply-Add and Multiply-Sub-Reversed (for FFT)
1084 Used in combination with SV FFT REMAP to perform
1085 a full Number-Theoretic-Transform in-place. Possible by having 3-in 2-out,
1086 to avoid the need for a temp register. RS is written
1090 gfpmaddsubr RT, RA, RB, RC
1093 TODO: add link to explanation for where `RS` comes from.
1099 # read all inputs before writing to any outputs in case
1100 # an input overlaps with an output register.
1101 (RT) = gfpmadd(factor1, factor2, term)
1102 (RS) = gfpmsubr(factor1, factor2, term)
1105 # Already in POWER ISA or subsumed
1107 Lists operations either included as part of
1108 other bitmanip operations, or are already in
1113 based on RV bitmanip, covered by ternlog bitops
1116 uint_xlen_t cmix(uint_xlen_t RA, uint_xlen_t RB, uint_xlen_t RC) {
1117 return (RA & RB) | (RC & ~RB);
1121 ## count leading/trailing zeros with mask
1127 do i = 0 to 63 if((RB)i=1) then do
1128 if((RS)i=1) then break end end count ← count + 1
1134 pdepd VRT,VRA,VRB, identical to RV bitmamip bdep, found already in v3.1 p106
1137 if VSR[VRB+32].dword[i].bit[63-m]=1 then do
1138 result = VSR[VRA+32].dword[i].bit[63-k]
1139 VSR[VRT+32].dword[i].bit[63-m] = result
1145 uint_xlen_t bdep(uint_xlen_t RA, uint_xlen_t RB)
1148 for (int i = 0, j = 0; i < XLEN; i++)
1149 if ((RB >> i) & 1) {
1151 r |= uint_xlen_t(1) << i;
1161 other way round: identical to RV bext: pextd, found in v3.1 p196
1164 uint_xlen_t bext(uint_xlen_t RA, uint_xlen_t RB)
1167 for (int i = 0, j = 0; i < XLEN; i++)
1168 if ((RB >> i) & 1) {
1170 r |= uint_xlen_t(1) << j;
1179 found in v3.1 p106 so not to be added here
1189 if((RB)63-i==1) then do
1190 result63-ptr1 = (RS)63-i
1196 ## bit to byte permute
1198 similar to matrix permute in RV bitmanip, which has XOR and OR variants,
1199 these perform a transpose (bmatflip).
1200 TODO this looks VSX is there a scalar variant
1205 b = VSR[VRB+32].dword[i].byte[k].bit[j]
1206 VSR[VRT+32].dword[i].byte[j].bit[k] = b
1210 superceded by grevlut
1212 based on RV bitmanip, this is also known as a butterfly network. however
1213 where a butterfly network allows setting of every crossbar setting in
1214 every row and every column, generalised-reverse (grev) only allows
1215 a per-row decision: every entry in the same row must either switch or
1218 <img src="https://upload.wikimedia.org/wikipedia/commons/thumb/8/8c/Butterfly_Network.jpg/474px-Butterfly_Network.jpg" />
1221 uint64_t grev64(uint64_t RA, uint64_t RB)
1224 int shamt = RB & 63;
1225 if (shamt & 1) x = ((x & 0x5555555555555555LL) << 1) |
1226 ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
1227 if (shamt & 2) x = ((x & 0x3333333333333333LL) << 2) |
1228 ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
1229 if (shamt & 4) x = ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
1230 ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
1231 if (shamt & 8) x = ((x & 0x00FF00FF00FF00FFLL) << 8) |
1232 ((x & 0xFF00FF00FF00FF00LL) >> 8);
1233 if (shamt & 16) x = ((x & 0x0000FFFF0000FFFFLL) << 16) |
1234 ((x & 0xFFFF0000FFFF0000LL) >> 16);
1235 if (shamt & 32) x = ((x & 0x00000000FFFFFFFFLL) << 32) |
1236 ((x & 0xFFFFFFFF00000000LL) >> 32);
1244 based on RV bitmanip, gorc is superceded by grevlut
1247 uint32_t gorc32(uint32_t RA, uint32_t RB)
1250 int shamt = RB & 31;
1251 if (shamt & 1) x |= ((x & 0x55555555) << 1) | ((x & 0xAAAAAAAA) >> 1);
1252 if (shamt & 2) x |= ((x & 0x33333333) << 2) | ((x & 0xCCCCCCCC) >> 2);
1253 if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4) | ((x & 0xF0F0F0F0) >> 4);
1254 if (shamt & 8) x |= ((x & 0x00FF00FF) << 8) | ((x & 0xFF00FF00) >> 8);
1255 if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16);
1258 uint64_t gorc64(uint64_t RA, uint64_t RB)
1261 int shamt = RB & 63;
1262 if (shamt & 1) x |= ((x & 0x5555555555555555LL) << 1) |
1263 ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
1264 if (shamt & 2) x |= ((x & 0x3333333333333333LL) << 2) |
1265 ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
1266 if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
1267 ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
1268 if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL) << 8) |
1269 ((x & 0xFF00FF00FF00FF00LL) >> 8);
1270 if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL) << 16) |
1271 ((x & 0xFFFF0000FFFF0000LL) >> 16);
1272 if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL) << 32) |
1273 ((x & 0xFFFFFFFF00000000LL) >> 32);
1282 see [[bitmanip/appendix]]