5 * ternlogi <https://bugs.libre-soc.org/show_bug.cgi?id=745>
6 * grev <https://bugs.libre-soc.org/show_bug.cgi?id=755>
7 * remove Rc=1 from ternlog due to conflicts in encoding as well
8 as saving space <https://bugs.libre-soc.org/show_bug.cgi?id=753#c5>
9 * GF2^M <https://bugs.libre-soc.org/show_bug.cgi?id=782>
15 pseudocode: <https://libre-soc.org/openpower/isa/bitmanip/>
17 this extension amalgamates bitmanipulation primitives from many sources, including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX. Vectorisation and SIMD are removed: these are straight scalar (element) operations making them suitable for embedded applications.
18 Vectorisation Context is provided by [[openpower/sv]].
20 When combined with SV, scalar variants of bitmanip operations found in VSX are added so that VSX may be retired as "legacy" in the far future (10 to 20 years). Also, VSX is hundreds of opcodes, requires 128 bit pathways, and is wholly unsuited to low power or embedded scenarios.
22 ternlogv is experimental and is the only operation that may be considered a "Packed SIMD". It is added as a variant of the already well-justified ternlog operation (done in AVX512 as an immediate only) "because it looks fun". As it is based on the LUT4 concept it will allow accelerated emulation of FPGAs. Other vendors of ISAs are buying FPGA companies to achieve similar objectives.
24 general-purpose Galois Field 2^M operations are added so as to avoid huge custom opcode proliferation across many areas of Computer Science. however for convenience and also to avoid setup costs, some of the more common operations (clmul, crc32) are also added. The expectation is that these operations would all be covered by the same pipeline.
26 note that there are brownfield spaces below that could incorporate some of the set-before-first and other scalar operations listed in [[sv/vector_ops]], and
27 the [[sv/av_opcodes]] as well as [[sv/setvl]]
31 * <https://en.wikiversity.org/wiki/Reed%E2%80%93Solomon_codes_for_coders>
32 * <https://maths-people.anu.edu.au/~brent/pd/rpb232tr.pdf>
36 ternlog has its own major opcode
39 | ------ |--| --------- |
45 2nd major opcode for other bitmanip: minor opcode allocation
48 | ------ |--| --------- |
61 | dest | src1 | subop | op |
62 | ---- | ---- | ----- | -------- |
63 | RT | RA | .. | bmatflip |
67 | dest | src1 | src2 | subop | op |
68 | ---- | ---- | ---- | ----- | -------- |
69 | RT | RA | RB | or | bmatflip |
70 | RT | RA | RB | xor | bmatflip |
71 | RT | RA | RB | | grev |
72 | RT | RA | RB | | clmul* |
73 | RT | RA | RB | | gorc |
74 | RT | RA | RB | shuf | shuffle |
75 | RT | RA | RB | unshuf| shuffle |
76 | RT | RA | RB | width | xperm |
77 | RT | RA | RB | type | minmax |
78 | RT | RA | RB | | av abs avgadd |
79 | RT | RA | RB | type | vmask ops |
89 TODO: convert all instructions to use RT and not RS
91 | 0.5|6.10|11.15|16.20 |21..25 | 26....30 |31| name |
92 | -- | -- | --- | --- | ----- | -------- |--| ------ |
93 | NN | RT | RA | RB | im0-4 | im5-7 00 |0 | |
94 | NN | RT | RA | RB | im0-4 | im5-7 00 |1 | grevlog |
95 | NN | RT | RA | s0-4 | im0-4 | im5-7 01 |s5| grevlogi |
96 | NN | RS | RA | RB | RC | 00 011 |0 | gfbmadd |
97 | NN | RS | RA | RB | RC | 10 011 |0 | gfbmaddsub |
98 | NN | RS | RA | RB | RC | 00 011 |1 | clmadd |
99 | NN | RS | RA | RB | RC | 10 011 |1 | clmaddsub |
100 | NN | RT | RA | RB | sh0-4 | sh5 1 011 |Rc| bmrevi |
102 ops (note that av avg and abs as well as vec scalar mask
105 TODO: convert from RA, RB, and RC to correct field names of RT, RA, and RB, and
106 double check that instructions didn't need 3 inputs.
108 | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name |
109 | -- | -- | --- | --- | -- | ----- | -------- |--| ---- |
110 | NN | RA | RB | | 0 | | 0000 110 |Rc| rsvd |
111 | NN | RA | RB | RC | 1 | itype | 0000 110 |Rc| xperm |
112 | NN | RA | RB | RC | 0 | itype | 0100 110 |Rc| minmax |
113 | NN | RA | RB | RC | 1 | 00 | 0100 110 |Rc| av avgadd |
114 | NN | RA | RB | RC | 1 | 01 | 0100 110 |Rc| av abs |
115 | NN | RA | RB | | 1 | 10 | 0100 110 |Rc| rsvd |
116 | NN | RA | RB | | 1 | 11 | 0100 110 |Rc| rsvd |
117 | NN | RA | RB | sh | SH | itype | 1000 110 |Rc| bmopsi |
118 | NN | RA | RB | | | | 1100 110 |Rc| rsvd |
119 | NN | RT | RA | RB | 1 | 00 | 0001 110 |Rc| cldiv |
120 | NN | RT | RA | RB | 1 | 01 | 0001 110 |Rc| clmod |
121 | NN | RT | RA | RB | 1 | 10 | 0001 110 |Rc| |
122 | NN | RT | RB | RB | 1 | 11 | 0001 110 |Rc| clinv |
123 | NN | RA | RB | RC | 0 | 00 | 0001 110 |Rc| vec sbfm |
124 | NN | RA | RB | RC | 0 | 01 | 0001 110 |Rc| vec sofm |
125 | NN | RA | RB | RC | 0 | 10 | 0001 110 |Rc| vec sifm |
126 | NN | RA | RB | RC | 0 | 11 | 0001 110 |Rc| vec cprop |
127 | NN | RA | RB | | 0 | | 0101 110 |Rc| rsvd |
128 | NN | RA | RB | RC | 0 | 00 | 0010 110 |Rc| gorc |
129 | NN | RA | RB | sh | SH | 00 | 1010 110 |Rc| gorci |
130 | NN | RA | RB | RC | 0 | 00 | 0110 110 |Rc| gorcw |
131 | NN | RA | RB | sh | 0 | 00 | 1110 110 |Rc| gorcwi |
132 | NN | RA | RB | RC | 1 | 00 | 1110 110 |Rc| bmator |
133 | NN | RA | RB | RC | 0 | 01 | 0010 110 |Rc| grev |
134 | NN | RA | RB | RC | 1 | 01 | 0010 110 |Rc| clmul |
135 | NN | RA | RB | sh | SH | 01 | 1010 110 |Rc| grevi |
136 | NN | RA | RB | RC | 0 | 01 | 0110 110 |Rc| grevw |
137 | NN | RA | RB | sh | 0 | 01 | 1110 110 |Rc| grevwi |
138 | NN | RA | RB | RC | 1 | 01 | 1110 110 |Rc| bmatxor |
139 | NN | RA | RB | RC | 0 | 10 | 0010 110 |Rc| shfl |
140 | NN | RA | RB | sh | SH | 10 | 1010 110 |Rc| shfli |
141 | NN | RA | RB | RC | 0 | 10 | 0110 110 |Rc| shflw |
142 | NN | RA | RB | RC | | 10 | 1110 110 |Rc| rsvd |
143 | NN | RA | RB | RC | 0 | 11 | 1110 110 |Rc| clmulr |
144 | NN | RA | RB | RC | 1 | 11 | 1110 110 |Rc| clmulh |
145 | NN | | | | | | --11 110 |Rc| setvl |
147 # bit to byte permute
149 similar to matrix permute in RV bitmanip, which has XOR and OR variants
153 b = VSR[VRB+32].dword[i].byte[k].bit[j]
154 VSR[VRT+32].dword[i].byte[j].bit[k] = b
158 signed and unsigned min/max for integer. this is sort-of partly synthesiseable in [[sv/svp64]] with pred-result as long as the dest reg is one of the sources, but not both signed and unsigned. when the dest is also one of the srces and the mv fails due to the CR bittest failing this will only overwrite the dest where the src is greater (or less).
160 signed/unsigned min/max gives more flexibility.
163 uint_xlen_t min(uint_xlen_t rs1, uint_xlen_t rs2)
164 { return (int_xlen_t)rs1 < (int_xlen_t)rs2 ? rs1 : rs2;
166 uint_xlen_t max(uint_xlen_t rs1, uint_xlen_t rs2)
167 { return (int_xlen_t)rs1 > (int_xlen_t)rs2 ? rs1 : rs2;
169 uint_xlen_t minu(uint_xlen_t rs1, uint_xlen_t rs2)
170 { return rs1 < rs2 ? rs1 : rs2;
172 uint_xlen_t maxu(uint_xlen_t rs1, uint_xlen_t rs2)
173 { return rs1 > rs2 ? rs1 : rs2;
180 Similar to FPGA LUTs: for every bit perform a lookup into a table using an 8bit immediate, or in another register.
182 Like the x86 AVX512F [vpternlogd/vpternlogq](https://www.felixcloutier.com/x86/vpternlogd:vpternlogq) instructions.
186 TODO: if/when we get more encoding space, add Rc=1 option back to ternlogi, for consistency with OpenPower base logical instructions (and./xor./or./etc.). <https://bugs.libre-soc.org/show_bug.cgi?id=745#c56>
188 | 0.5|6.10|11.15|16.20| 21..25| 26..30 |31|
189 | -- | -- | --- | --- | ----- | -------- |--|
190 | NN | RT | RA | RB | im0-4 | im5-7 00 |Rc|
193 idx = c << 2 | b << 1 | a
194 return imm[idx] # idx by LSB0 order
197 RT[i] = lut3(imm, RB[i], RA[i], RT[i])
199 bits 21..22 may be used to specify a mode, such as treating the whole integer zero/nonzero and putting 1/0 in the result, rather than bitwise test.
203 a 4 operand variant which becomes more along the lines of an FPGA:
205 | 0.5|6.10|11.15|16.20|21.25| 26...30 |31|
206 | -- | -- | --- | --- | --- | -------- |--|
207 | NN | RT | RA | RB | RC | mode 01 |1 |
210 idx = RT[i] << 2 | RA[i] << 1 | RB[i]
211 RT[i] = (RC & (1<<idx)) != 0
213 mode (3 bit) may be used to do inversion of ordering, similar to carryless mul,
218 also, another possible variant involving swizzle and vec4:
220 | 0.5|6.10|11.15| 16.23 |24.27 | 28.30 |31|
221 | -- | -- | --- | ----- | ---- | ----- |--|
222 | NN | RT | RA | imm | mask | -01 |0 |
225 idx = RA.x[i] << 2 | RA.y[i] << 1 | RA.z[i]
226 res = (imm & (1<<idx)) != 0
228 if mask[j]: RT[i+j*8] = res
232 another mode selection would be CRs not Ints.
234 | 0.5|6.8 | 9.11|12.14|15.17|18.20|21.28 | 29.30|31|
235 | -- | -- | --- | --- | --- |-----|----- | -----|--|
236 | NN | BT | BA | BB | BC |m0-3 | imm | 10 |m4|
240 if not mask[i] continue
241 crregs[BT][i] = lut3(imm,
248 based on RV bitmanip, covered by ternlog bitops
251 uint_xlen_t cmix(uint_xlen_t RA, uint_xlen_t RB, uint_xlen_t RC) {
252 return (RA & RB) | (RC & ~RB);
259 based on RV bitmanip singlebit set, instruction format similar to shift
260 [[isa/fixedshift]]. bmext is actually covered already (shift-with-mask rldicl but only immediate version).
261 however bitmask-invert is not, and set/clr are not covered, although they can use the same Shift ALU.
263 bmext (RB) version is not the same as rldicl because bmext is a right shift by RC, where rldicl is a left rotate. for the immediate version this does not matter, so a bmexti is not required.
264 bmrev however there is no direct equivalent and consequently a bmrevi is required.
266 bmset (register for mask amount) is particularly useful for creating
267 predicate masks where the length is a dynamic runtime quantity.
268 bmset(RA=0, RB=0, RC=mask) will produce a run of ones of length "mask" in a single instruction without needing to initialise or depend on any other registers.
270 | 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name |
271 | -- | -- | --- | --- | --- | ------- |--| ----- |
272 | NN | RT | RA | RB | RC | mode 010 |Rc| bm* |
276 uint_xlen_t bmset(RA, RB, sh)
278 int shamt = RB & (XLEN - 1);
280 return RA | (mask << shamt);
283 uint_xlen_t bmclr(RA, RB, sh)
285 int shamt = RB & (XLEN - 1);
287 return RA & ~(mask << shamt);
290 uint_xlen_t bminv(RA, RB, sh)
292 int shamt = RB & (XLEN - 1);
294 return RA ^ (mask << shamt);
297 uint_xlen_t bmext(RA, RB, sh)
299 int shamt = RB & (XLEN - 1);
301 return mask & (RA >> shamt);
305 bitmask extract with reverse. can be done by bitinverting all of RA and getting bits of RA from the opposite end.
309 rev[0:msb] = ra[msb:0];
312 uint_xlen_t bmextrev(RA, RB, sh)
314 int shamt = (RB & (XLEN - 1));
315 shamt = (XLEN-1)-shamt; # shift other end
316 bra = bitreverse(RA) # swap LSB-MSB
318 return mask & (bra >> shamt);
322 | 0.5|6.10|11.15|16.20|21.26| 27..30 |31| name |
323 | -- | -- | --- | --- | --- | ------- |--| ------ |
324 | NN | RT | RA | RB | sh | 1 011 |Rc| bmrevi |
329 generalised reverse combined with a pair of LUT2s and allowing
330 zero when RA=0 provides a wide range of instructions
331 and a means to set regular 64 bit patterns in one
334 the two LUT2s are applied left-half (when not swapping)
335 and right-half (when swapping) so as to allow a wider
338 grevlut should be arranged so as to produce the constants
339 needed to put into bext (bitextract) so as in turn to
340 be able to emulate x86 pmovmask instructions <https://www.felixcloutier.com/x86/pmovmskb>
342 <img src="/openpower/sv/grevlut2x2.jpg" width=700 />
347 return imm[idx] # idx by LSB0 order
349 dorow(imm8, step_i, chunksize):
351 if (j&chunk_size) == 0
355 step_o[j] = lut2(imm, step_i[j], step_i[j ^ chunk_size])
358 uint64_t grevlut64(uint64_t RA, uint64_t RB, uint8 imm)
364 if (shamt & step) x = dorow(imm, x, step)
372 based on RV bitmanip, this is also known as a butterfly network. however
373 where a butterfly network allows setting of every crossbar setting in
374 every row and every column, generalised-reverse (grev) only allows
375 a per-row decision: every entry in the same row must either switch or
378 <img src="https://upload.wikimedia.org/wikipedia/commons/thumb/8/8c/Butterfly_Network.jpg/474px-Butterfly_Network.jpg" />
381 uint64_t grev64(uint64_t RA, uint64_t RB)
385 if (shamt & 1) x = ((x & 0x5555555555555555LL) << 1) |
386 ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
387 if (shamt & 2) x = ((x & 0x3333333333333333LL) << 2) |
388 ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
389 if (shamt & 4) x = ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
390 ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
391 if (shamt & 8) x = ((x & 0x00FF00FF00FF00FFLL) << 8) |
392 ((x & 0xFF00FF00FF00FF00LL) >> 8);
393 if (shamt & 16) x = ((x & 0x0000FFFF0000FFFFLL) << 16) |
394 ((x & 0xFFFF0000FFFF0000LL) >> 16);
395 if (shamt & 32) x = ((x & 0x00000000FFFFFFFFLL) << 32) |
396 ((x & 0xFFFFFFFF00000000LL) >> 32);
402 # shuffle / unshuffle
407 uint32_t shfl32(uint32_t RA, uint32_t RB)
411 if (shamt & 8) x = shuffle32_stage(x, 0x00ff0000, 0x0000ff00, 8);
412 if (shamt & 4) x = shuffle32_stage(x, 0x0f000f00, 0x00f000f0, 4);
413 if (shamt & 2) x = shuffle32_stage(x, 0x30303030, 0x0c0c0c0c, 2);
414 if (shamt & 1) x = shuffle32_stage(x, 0x44444444, 0x22222222, 1);
417 uint32_t unshfl32(uint32_t RA, uint32_t RB)
421 if (shamt & 1) x = shuffle32_stage(x, 0x44444444, 0x22222222, 1);
422 if (shamt & 2) x = shuffle32_stage(x, 0x30303030, 0x0c0c0c0c, 2);
423 if (shamt & 4) x = shuffle32_stage(x, 0x0f000f00, 0x00f000f0, 4);
424 if (shamt & 8) x = shuffle32_stage(x, 0x00ff0000, 0x0000ff00, 8);
428 uint64_t shuffle64_stage(uint64_t src, uint64_t maskL, uint64_t maskR, int N)
430 uint64_t x = src & ~(maskL | maskR);
431 x |= ((src << N) & maskL) | ((src >> N) & maskR);
434 uint64_t shfl64(uint64_t RA, uint64_t RB)
438 if (shamt & 16) x = shuffle64_stage(x, 0x0000ffff00000000LL,
439 0x00000000ffff0000LL, 16);
440 if (shamt & 8) x = shuffle64_stage(x, 0x00ff000000ff0000LL,
441 0x0000ff000000ff00LL, 8);
442 if (shamt & 4) x = shuffle64_stage(x, 0x0f000f000f000f00LL,
443 0x00f000f000f000f0LL, 4);
444 if (shamt & 2) x = shuffle64_stage(x, 0x3030303030303030LL,
445 0x0c0c0c0c0c0c0c0cLL, 2);
446 if (shamt & 1) x = shuffle64_stage(x, 0x4444444444444444LL,
447 0x2222222222222222LL, 1);
450 uint64_t unshfl64(uint64_t RA, uint64_t RB)
454 if (shamt & 1) x = shuffle64_stage(x, 0x4444444444444444LL,
455 0x2222222222222222LL, 1);
456 if (shamt & 2) x = shuffle64_stage(x, 0x3030303030303030LL,
457 0x0c0c0c0c0c0c0c0cLL, 2);
458 if (shamt & 4) x = shuffle64_stage(x, 0x0f000f000f000f00LL,
459 0x00f000f000f000f0LL, 4);
460 if (shamt & 8) x = shuffle64_stage(x, 0x00ff000000ff0000LL,
461 0x0000ff000000ff00LL, 8);
462 if (shamt & 16) x = shuffle64_stage(x, 0x0000ffff00000000LL,
463 0x00000000ffff0000LL, 16);
473 uint_xlen_t xperm(uint_xlen_t RA, uint_xlen_t RB, int sz_log2)
476 uint_xlen_t sz = 1LL << sz_log2;
477 uint_xlen_t mask = (1LL << sz) - 1;
478 for (int i = 0; i < XLEN; i += sz) {
479 uint_xlen_t pos = ((RB >> i) & mask) << sz_log2;
481 r |= ((RA >> pos) & mask) << i;
485 uint_xlen_t xperm_n (uint_xlen_t RA, uint_xlen_t RB)
486 { return xperm(RA, RB, 2); }
487 uint_xlen_t xperm_b (uint_xlen_t RA, uint_xlen_t RB)
488 { return xperm(RA, RB, 3); }
489 uint_xlen_t xperm_h (uint_xlen_t RA, uint_xlen_t RB)
490 { return xperm(RA, RB, 4); }
491 uint_xlen_t xperm_w (uint_xlen_t RA, uint_xlen_t RB)
492 { return xperm(RA, RB, 5); }
500 uint32_t gorc32(uint32_t RA, uint32_t RB)
504 if (shamt & 1) x |= ((x & 0x55555555) << 1) | ((x & 0xAAAAAAAA) >> 1);
505 if (shamt & 2) x |= ((x & 0x33333333) << 2) | ((x & 0xCCCCCCCC) >> 2);
506 if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4) | ((x & 0xF0F0F0F0) >> 4);
507 if (shamt & 8) x |= ((x & 0x00FF00FF) << 8) | ((x & 0xFF00FF00) >> 8);
508 if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16);
511 uint64_t gorc64(uint64_t RA, uint64_t RB)
515 if (shamt & 1) x |= ((x & 0x5555555555555555LL) << 1) |
516 ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
517 if (shamt & 2) x |= ((x & 0x3333333333333333LL) << 2) |
518 ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
519 if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
520 ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
521 if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL) << 8) |
522 ((x & 0xFF00FF00FF00FF00LL) >> 8);
523 if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL) << 16) |
524 ((x & 0xFFFF0000FFFF0000LL) >> 16);
525 if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL) << 32) |
526 ((x & 0xFFFFFFFF00000000LL) >> 32);
532 # Instructions for Carry-less Operations aka. Polynomials with coefficients in `GF(2)`
534 Carry-less addition/subtraction is simply XOR, so a `cladd`
535 instruction is not provided since the `xor[i]` instruction can be used instead.
537 These are operations on polynomials with coefficients in `GF(2)`, with the
538 polynomial's coefficients packed into integers with the following algorithm:
542 """`poly` is a list where `poly[i]` is the coefficient for `x ** i`"""
544 for i, v in enumerate(poly):
549 """returns a list `poly`, where `poly[i]` is the coefficient for `x ** i`.
558 ## Carry-less Multiply Instructions
561 see <https://en.wikipedia.org/wiki/CLMUL_instruction_set> and
562 <https://www.felixcloutier.com/x86/pclmulqdq> and
563 <https://en.m.wikipedia.org/wiki/Carry-less_product>
565 They are worth adding as their own non-overwrite operations
566 (in the same pipeline).
568 ### `clmul` Carry-less Multiply
571 uint_xlen_t clmul(uint_xlen_t RA, uint_xlen_t RB)
574 for (int i = 0; i < XLEN; i++)
581 ### `clmulh` Carry-less Multiply High
584 uint_xlen_t clmulh(uint_xlen_t RA, uint_xlen_t RB)
587 for (int i = 1; i < XLEN; i++)
594 ### `clmulr` Carry-less Multiply (Reversed)
596 Useful for CRCs. Equivalent to bit-reversing the result of `clmul` on
600 uint_xlen_t clmulr(uint_xlen_t RA, uint_xlen_t RB)
603 for (int i = 0; i < XLEN; i++)
605 x ^= RA >> (XLEN-i-1);
610 ## `clmadd` Carry-less Multiply-Add
613 clmadd RT, RA, RB, RC
617 (RT) = clmul((RA), (RB)) ^ (RC)
620 ## `cltmadd` Twin Carry-less Multiply-Add (for FFTs)
623 cltmadd RT, RA, RB, RC
626 TODO: add link to explanation for where `RS` comes from.
629 temp = clmul((RA), (RB)) ^ (RC)
634 ## `cldiv` Carry-less Division
640 TODO: decide what happens on division by zero
643 (RT) = cldiv((RA), (RB))
646 ## `clrem` Carry-less Remainder
652 TODO: decide what happens on division by zero
655 (RT) = clrem((RA), (RB))
658 # Instructions for Binary Galois Fields `GF(2^m)`
662 * <https://courses.csail.mit.edu/6.857/2016/files/ffield.py>
663 * <https://engineering.purdue.edu/kak/compsec/NewLectures/Lecture7.pdf>
664 * <https://foss.heptapod.net/math/libgf2/-/blob/branch/default/src/libgf2/gf2.py>
666 Binary Galois Field addition/subtraction is simply XOR, so a `gfbadd`
667 instruction is not provided since the `xor[i]` instruction can be used instead.
669 ## `GFBREDPOLY` SPR -- Reducing Polynomial
671 In order to save registers and to make operations orthogonal with standard
672 arithmetic, the reducing polynomial is stored in a dedicated SPR `GFBREDPOLY`.
673 This also allows hardware to pre-compute useful parameters (such as the
674 degree, or look-up tables) based on the reducing polynomial, and store them
675 alongside the SPR in hidden registers, only recomputing them whenever the SPR
676 is written to, rather than having to recompute those values for every
679 Because Galois Fields require the reducing polynomial to be an irreducible
680 polynomial, that guarantees that any polynomial of `degree > 1` must have
681 the LSB set, since otherwise it would be divisible by the polynomial `x`,
682 making it reducible, making whatever we're working on no longer a Field.
683 Therefore, we can reuse the LSB to indicate `degree == XLEN`.
686 def decode_reducing_polynomial(GFBREDPOLY, XLEN):
687 """returns the decoded coefficient list in LSB to MSB order,
688 len(retval) == degree + 1"""
689 v = GFBREDPOLY & ((1 << XLEN) - 1) # mask to XLEN bits
690 if v == 0 or v == 2: # GF(2)
691 return [0, 1] # degree = 1, poly = x
693 degree = floor_log2(v)
695 # all reducing polynomials of degree > 1 must have the LSB set,
696 # because they must be irreducible polynomials (meaning they
697 # can't be factored), if the LSB was clear, then they would
698 # have `x` as a factor. Therefore, we can reuse the LSB clear
699 # to instead mean the polynomial has degree XLEN.
702 v |= 1 # LSB must be set
703 return [(v >> i) & 1 for i in range(1 + degree)]
706 ## `gfbredpoly` -- Set the Reducing Polynomial SPR `GFBREDPOLY`
708 unless this is an immediate op, `mtspr` is completely sufficient.
710 ## `gfbmul` -- Binary Galois Field `GF(2^m)` Multiplication
717 (RT) = gfbmul((RA), (RB))
720 ## `gfbmadd` -- Binary Galois Field `GF(2^m)` Multiply-Add
723 gfbmadd RT, RA, RB, RC
727 (RT) = gfbadd(gfbmul((RA), (RB)), (RC))
730 ## `gfbtmadd` -- Binary Galois Field `GF(2^m)` Twin Multiply-Add (for FFT)
733 gfbtmadd RT, RA, RB, RC
736 TODO: add link to explanation for where `RS` comes from.
739 temp = gfbadd(gfbmul((RA), (RB)), (RC))
744 ## `gfbinv` -- Binary Galois Field `GF(2^m)` Inverse
754 # Instructions for Prime Galois Fields `GF(p)`
759 def int_to_gfp(int_value, prime):
760 return int_value % prime # follows Python remainder semantics
763 ## `GFPRIME` SPR -- Prime Modulus For `gfp*` Instructions
765 ## `gfpadd` Prime Galois Field `GF(p)` Addition
772 (RT) = int_to_gfp((RA) + (RB), GFPRIME)
775 the addition happens on infinite-precision integers
777 ## `gfpsub` Prime Galois Field `GF(p)` Subtraction
784 (RT) = int_to_gfp((RA) - (RB), GFPRIME)
787 the subtraction happens on infinite-precision integers
789 ## `gfpmul` Prime Galois Field `GF(p)` Multiplication
796 (RT) = int_to_gfp((RA) * (RB), GFPRIME)
799 the multiplication happens on infinite-precision integers
801 ## `gfpinv` Prime Galois Field `GF(p)` Invert
807 Some potential hardware implementations are found in:
808 <https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.90.5233&rep=rep1&type=pdf>
811 (RT) = gfpinv((RA), GFPRIME)
814 the multiplication happens on infinite-precision integers
816 ## `gfpmadd` Prime Galois Field `GF(p)` Multiply-Add
819 gfpmadd RT, RA, RB, RC
823 (RT) = int_to_gfp((RA) * (RB) + (RC), GFPRIME)
826 the multiplication and addition happens on infinite-precision integers
828 ## `gfpmsub` Prime Galois Field `GF(p)` Multiply-Subtract
831 gfpmsub RT, RA, RB, RC
835 (RT) = int_to_gfp((RA) * (RB) - (RC), GFPRIME)
838 the multiplication and subtraction happens on infinite-precision integers
840 ## `gfpmsubr` Prime Galois Field `GF(p)` Multiply-Subtract-Reversed
843 gfpmsubr RT, RA, RB, RC
847 (RT) = int_to_gfp((RC) - (RA) * (RB), GFPRIME)
850 the multiplication and subtraction happens on infinite-precision integers
852 ## `gfpmaddsubr` Prime Galois Field `GF(p)` Multiply-Add and Multiply-Sub-Reversed (for FFT)
855 gfpmaddsubr RT, RA, RB, RC
858 TODO: add link to explanation for where `RS` comes from.
861 product = (RA) * (RB)
863 (RT) = int_to_gfp(product + term, GFPRIME)
864 (RS) = int_to_gfp(term - product, GFPRIME)
867 the multiplication, addition, and subtraction happens on infinite-precision integers
869 ## Twin Butterfly (Tukey-Cooley) Mul-add-sub
871 used in combination with SV FFT REMAP to perform
872 a full NTT in-place. possible by having 3-in 2-out,
873 to avoid the need for a temp register. RS is written
876 gffmadd RT,RA,RC,RB (Rc=0)
877 gffmadd. RT,RA,RC,RB (Rc=1)
881 RT <- GFADD(GFMUL(RA, RC), RB))
882 RS <- GFADD(GFMUL(RA, RC), RB))
887 with the modulo and degree being in an SPR, multiply can be identical
888 equivalent to standard integer add
892 | 0.5|6.10|11.15|16.20|21.25| 26..30 |31|
893 | -- | -- | --- | --- | --- | ------ |--|
894 | NN | RT | RA | RB |11000| 01110 |Rc|
899 from functools import reduce
909 # constants used in the multGF2 function
910 mask1 = mask2 = polyred = None
913 """Define parameters of binary finite field GF(2^m)/g(x)
914 - irPoly: coefficients of irreducible polynomial g(x)
916 # degree: extension degree of binary field
917 degree = gf_degree(irPoly)
920 """Convert an integer into a polynomial"""
921 return [(sInt >> i) & 1
922 for i in reversed(range(sInt.bit_length()))]
924 global mask1, mask2, polyred
925 mask1 = mask2 = 1 << degree
927 polyred = reduce(lambda x, y: (x << 1) + y, i2P(irPoly)[1:])
930 """Multiply two polynomials in GF(2^m)/g(x)"""
933 # standard long-multiplication: check LSB and add
937 # standard modulo: check MSB and add polynomial
943 if __name__ == "__main__":
945 # Define binary field GF(2^3)/x^3 + x + 1
946 setGF2(0b1011) # degree 3
948 # Evaluate the product (x^2 + x + 1)(x^2 + 1)
949 print("{:02x}".format(multGF2(0b111, 0b101)))
951 # Define binary field GF(2^8)/x^8 + x^4 + x^3 + x + 1
952 # (used in the Advanced Encryption Standard-AES)
953 setGF2(0b100011011) # degree 8
955 # Evaluate the product (x^7)(x^7 + x + 1)
956 print("{:02x}".format(multGF2(0b10000000, 0b10000011)))
962 # https://bugs.libre-soc.org/show_bug.cgi?id=782#c33
963 # https://ftp.libre-soc.org/ARITH18_Kobayashi.pdf
966 s = getGF2() # get the full polynomial (including the MSB)
972 for i in range(1, 2*degree+1):
973 # could use count-trailing-1s here to skip ahead
974 if r & mask1: # test MSB of r
975 if s & mask1: # test MSB of s
978 s <<= 1 # shift left 1
980 r, s = s, r # swap r,s
981 u, v = v<<1, u # shift v and swap
984 u >>= 1 # right shift left
987 r <<= 1 # shift left 1
988 u <<= 1 # shift left 1
996 ## GF2 (carryless) div and mod
1007 def FullDivision(self, f, v):
1009 Takes two arguments, f, v
1010 fDegree and vDegree are the degrees of the field elements
1011 f and v represented as a polynomials.
1012 This method returns the field elements a and b such that
1014 f(x) = a(x) * v(x) + b(x).
1016 That is, a is the divisor and b is the remainder, or in
1017 other words a is like floor(f/v) and b is like f modulo v.
1020 fDegree, vDegree = gf_degree(f), gf_degree(v)
1022 for i in reversed(range(vDegree, fDegree+1):
1023 if ((rem >> i) & 1): # check bit
1024 res ^= (1 << (i - vDegree))
1025 rem ^= ( v << (i - vDegree)))
1029 | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name |
1030 | -- | -- | --- | --- | -- | ----- | -------- |--| ---- |
1031 | NN | RT | RA | RB | 1 | 00 | 0001 110 |Rc| cldiv |
1032 | NN | RT | RA | RB | 1 | 01 | 0001 110 |Rc| clmod |
1034 ## GF2 carryless mul
1036 based on RV bitmanip
1037 see <https://en.wikipedia.org/wiki/CLMUL_instruction_set> and
1038 <https://www.felixcloutier.com/x86/pclmulqdq> and
1039 <https://en.m.wikipedia.org/wiki/Carry-less_product>
1041 these are GF2 operations with the modulo set to 2^degree.
1042 they are worth adding as their own non-overwrite operations
1043 (in the same pipeline).
1046 uint_xlen_t clmul(uint_xlen_t RA, uint_xlen_t RB)
1049 for (int i = 0; i < XLEN; i++)
1054 uint_xlen_t clmulh(uint_xlen_t RA, uint_xlen_t RB)
1057 for (int i = 1; i < XLEN; i++)
1059 x ^= RA >> (XLEN-i);
1062 uint_xlen_t clmulr(uint_xlen_t RA, uint_xlen_t RB)
1065 for (int i = 0; i < XLEN; i++)
1067 x ^= RA >> (XLEN-i-1);
1071 ## carryless Twin Butterfly (Tukey-Cooley) Mul-add-sub
1073 used in combination with SV FFT REMAP to perform
1074 a full NTT in-place. possible by having 3-in 2-out,
1075 to avoid the need for a temp register. RS is written
1078 clfmadd RT,RA,RC,RB (Rc=0)
1079 clfmadd. RT,RA,RC,RB (Rc=1)
1083 RT <- CLMUL(RA, RC) ^ RB
1084 RS <- CLMUL(RA, RC) ^ RB
1090 uint64_t bmatflip(uint64_t RA)
1098 uint64_t bmatxor(uint64_t RA, uint64_t RB)
1101 uint64_t RBt = bmatflip(RB);
1102 uint8_t u[8]; // rows of RA
1103 uint8_t v[8]; // cols of RB
1104 for (int i = 0; i < 8; i++) {
1106 v[i] = RBt >> (i*8);
1109 for (int i = 0; i < 64; i++) {
1110 if (pcnt(u[i / 8] & v[i % 8]) & 1)
1115 uint64_t bmator(uint64_t RA, uint64_t RB)
1118 uint64_t RBt = bmatflip(RB);
1119 uint8_t u[8]; // rows of RA
1120 uint8_t v[8]; // cols of RB
1121 for (int i = 0; i < 8; i++) {
1123 v[i] = RBt >> (i*8);
1126 for (int i = 0; i < 64; i++) {
1127 if ((u[i / 8] & v[i % 8]) != 0)
1135 # Already in POWER ISA
1137 ## count leading/trailing zeros with mask
1143 do i = 0 to 63 if((RB)i=1) then do
1144 if((RS)i=1) then break end end count ← count + 1
1150 vpdepd VRT,VRA,VRB, identical to RV bitmamip bdep, found already in v3.1 p106
1153 if VSR[VRB+32].dword[i].bit[63-m]=1 then do
1154 result = VSR[VRA+32].dword[i].bit[63-k]
1155 VSR[VRT+32].dword[i].bit[63-m] = result
1161 uint_xlen_t bdep(uint_xlen_t RA, uint_xlen_t RB)
1164 for (int i = 0, j = 0; i < XLEN; i++)
1165 if ((RB >> i) & 1) {
1167 r |= uint_xlen_t(1) << i;
1177 other way round: identical to RV bext, found in v3.1 p196
1180 uint_xlen_t bext(uint_xlen_t RA, uint_xlen_t RB)
1183 for (int i = 0, j = 0; i < XLEN; i++)
1184 if ((RB >> i) & 1) {
1186 r |= uint_xlen_t(1) << j;
1195 found in v3.1 p106 so not to be added here
1205 if((RB)63-i==1) then do
1206 result63-ptr1 = (RS)63-i