5 * ternlogi <https://bugs.libre-soc.org/show_bug.cgi?id=745>
6 * grev <https://bugs.libre-soc.org/show_bug.cgi?id=755>
7 * GF2^M <https://bugs.libre-soc.org/show_bug.cgi?id=782>
13 pseudocode: <https://libre-soc.org/openpower/isa/bitmanip/>
15 this extension amalgamates bitmanipulation primitives from many sources, including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX. Vectorisation and SIMD are removed: these are straight scalar (element) operations making them suitable for embedded applications.
16 Vectorisation Context is provided by [[openpower/sv]].
18 When combined with SV, scalar variants of bitmanip operations found in VSX are added so that VSX may be retired as "legacy" in the far future (10 to 20 years). Also, VSX is hundreds of opcodes, requires 128 bit pathways, and is wholly unsuited to low power or embedded scenarios.
20 ternlogv is experimental and is the only operation that may be considered a "Packed SIMD". It is added as a variant of the already well-justified ternlog operation (done in AVX512 as an immediate only) "because it looks fun". As it is based on the LUT4 concept it will allow accelerated emulation of FPGAs. Other vendors of ISAs are buying FPGA companies to achieve similar objectives.
22 general-purpose Galois Field 2^M operations are added so as to avoid huge custom opcode proliferation across many areas of Computer Science. however for convenience and also to avoid setup costs, some of the more common operations (clmul, crc32) are also added. The expectation is that these operations would all be covered by the same pipeline.
24 note that there are brownfield spaces below that could incorporate some of the set-before-first and other scalar operations listed in [[sv/vector_ops]], and
25 the [[sv/av_opcodes]] as well as [[sv/setvl]]
29 * <https://en.wikiversity.org/wiki/Reed%E2%80%93Solomon_codes_for_coders>
30 * <https://maths-people.anu.edu.au/~brent/pd/rpb232tr.pdf>
34 two major opcodes are needed
36 ternlog has its own major opcode
39 | ------ |--| --------- |
44 2nd major opcode for other bitmanip: minor opcode allocation
47 | ------ |--| --------- |
52 | 011 | | gf/cl madd* |
59 | dest | src1 | subop | op |
60 | ---- | ---- | ----- | -------- |
61 | RT | RA | .. | bmatflip |
65 | dest | src1 | src2 | subop | op |
66 | ---- | ---- | ---- | ----- | -------- |
67 | RT | RA | RB | or | bmatflip |
68 | RT | RA | RB | xor | bmatflip |
69 | RT | RA | RB | | grev |
70 | RT | RA | RB | | clmul* |
71 | RT | RA | RB | | gorc |
72 | RT | RA | RB | shuf | shuffle |
73 | RT | RA | RB | unshuf| shuffle |
74 | RT | RA | RB | width | xperm |
75 | RT | RA | RB | type | av minmax |
76 | RT | RA | RB | | av abs avgadd |
77 | RT | RA | RB | type | vmask ops |
86 TODO: convert all instructions to use RT and not RS
88 | 0.5|6.8 | 9.11|12.14|15.17|18.20|21.28 | 29.30|31|name|
89 | -- | -- | --- | --- | --- |-----|----- | -----|--|----|
90 | NN | BT | BA | BB | BC |m0-2 | imm | 10 |m3|crternlog|
92 | 0.5|6.10|11.15|16.20 |21..25 | 26....30 |31| name |
93 | -- | -- | --- | --- | ----- | -------- |--| ------ |
94 | NN | RT | RA |itype/| im0-4 | im5-7 00 |0 | xpermi |
95 | NN | RT | RA | RB | im0-4 | im5-7 00 |1 | grevlog |
96 | NN | | | | | ..... 01 |0 | crternlog |
97 | NN | RT | RA | RB | RC | mode 010 |Rc| bitmask* |
98 | NN | RS | RA | RB | RC | 00 011 |0 | gfbmadd |
99 | NN | RS | RA | RB | RC | 00 011 |1 | gfbmaddsub |
100 | NN | RS | RA | RB | RC | 01 011 |0 | clmadd |
101 | NN | RS | RA | RB | RC | 01 011 |1 | clmaddsub |
102 | NN | RS | RA | RB | RC | 10 011 |0 | gfpmadd |
103 | NN | RS | RA | RB | RC | 10 011 |1 | gfpmaddsub |
104 | NN | RS | RA | RB | RC | 11 011 | | rsvd |
105 | NN | RT | RA | RB | sh0-4 | sh5 1 111 |Rc| bmrevi |
107 ops (note that av avg and abs as well as vec scalar mask
108 are included here [[sv/vector_ops]], and
109 the [[sv/av_opcodes]])
111 TODO: convert from RA, RB, and RC to correct field names of RT, RA, and RB, and
112 double check that instructions didn't need 3 inputs.
114 | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name |
115 | -- | -- | --- | --- | -- | ----- | -------- |--| ---- |
116 | NN | RS | me | sh | SH | ME 0 | nn00 110 |Rc| bmopsi |
117 | NN | RS | RB | sh | SH | 0 1 | nn00 110 |Rc| bmopsi |
118 | NN | RT | RA | RB | 1 | 00 | 0001 110 |Rc| cldiv |
119 | NN | RT | RA | RB | 1 | 01 | 0001 110 |Rc| clmod |
120 | NN | RT | RA | RB | 1 | 10 | 0001 110 |Rc| |
121 | NN | RT | RB | RB | 1 | 11 | 0001 110 |Rc| clinv |
122 | NN | RA | RB | RC | 0 | 00 | 0001 110 |Rc| vec sbfm |
123 | NN | RA | RB | RC | 0 | 01 | 0001 110 |Rc| vec sofm |
124 | NN | RA | RB | RC | 0 | 10 | 0001 110 |Rc| vec sifm |
125 | NN | RA | RB | RC | 0 | 11 | 0001 110 |Rc| vec cprop |
126 | NN | RT | RA | RB | 1 | itype | 0101 110 |Rc| xperm |
127 | NN | RA | RB | RC | 0 | itype | 0101 110 |Rc| av minmax |
128 | NN | RA | RB | RC | 1 | 00 | 0101 110 |Rc| av abss |
129 | NN | RA | RB | RC | 1 | 01 | 0101 110 |Rc| av absu|
130 | NN | RA | RB | | 1 | 10 | 0101 110 |Rc| av avgadd |
131 | NN | RA | RB | | 1 | 11 | 0101 110 |Rc| rsvd |
132 | NN | RA | RB | | | | 1001 110 |Rc| rsvd |
133 | NN | RA | RB | | | | 1101 110 |Rc| rsvd |
134 | NN | RA | RB | RC | 0 | 00 | 0010 110 |Rc| gorc |
135 | NN | RA | RB | sh | SH | 00 | 1010 110 |Rc| gorci |
136 | NN | RA | RB | RC | 0 | 00 | 0110 110 |Rc| gorcw |
137 | NN | RA | RB | sh | 0 | 00 | 1110 110 |Rc| gorcwi |
138 | NN | RA | RB | RC | 1 | 00 | 1110 110 |Rc| bmator |
139 | NN | RA | RB | RC | 0 | 01 | 0010 110 |Rc| grev |
140 | NN | RA | RB | RC | 1 | 01 | 0010 110 |Rc| clmul |
141 | NN | RA | RB | sh | SH | 01 | 1010 110 |Rc| grevi |
142 | NN | RA | RB | RC | 0 | 01 | 0110 110 |Rc| grevw |
143 | NN | RA | RB | sh | 0 | 01 | 1110 110 |Rc| grevwi |
144 | NN | RA | RB | RC | 1 | 01 | 1110 110 |Rc| bmatxor |
145 | NN | RA | RB | RC | | 10 | --10 110 |Rc| rsvd |
146 | NN | RA | RB | RC | 0 | 11 | 1110 110 |Rc| clmulr |
147 | NN | RA | RB | RC | 1 | 11 | 1110 110 |Rc| clmulh |
148 | NN | | | | | | --11 110 |Rc| setvl |
152 Similar to FPGA LUTs: for every bit perform a lookup into a table using an 8bit immediate, or in another register.
154 Like the x86 AVX512F [vpternlogd/vpternlogq](https://www.felixcloutier.com/x86/vpternlogd:vpternlogq) instructions.
158 | 0.5|6.10|11.15|16.20| 21..28|29.30|31|
159 | -- | -- | --- | --- | ----- | --- |--|
160 | NN | RT | RA | RB | im0-7 | 00 |Rc|
163 idx = c << 2 | b << 1 | a
164 return imm[idx] # idx by LSB0 order
167 RT[i] = lut3(imm, RB[i], RA[i], RT[i])
171 also, another possible variant involving swizzle-like selection
172 and masking, this only requires 3 64 bit registers (RA, RS, RB) and
175 Note however that unless XLEN matches sz, this instruction
176 is a Read-Modify-Write: RS must be read as a second operand
177 and all unmodified bits preserved. SVP64 may provide limited
178 alternative destination for RS from RS-as-source, but again
179 all unmodified bits must still be copied.
181 | 0.5|6.10|11.15|16.20|21.28 | 29.30 |31|
182 | -- | -- | --- | --- | ---- | ----- |--|
183 | NN | RS | RA | RB |idx0-3| 01 |sz|
185 SZ = (1+sz) * 8 # 8 or 16
186 raoff = MIN(XLEN, idx0 * SZ)
187 rboff = MIN(XLEN, idx1 * SZ)
188 rcoff = MIN(XLEN, idx2 * SZ)
189 rsoff = MIN(XLEN, idx3 * SZ)
191 for i in range(MIN(XLEN, SZ)):
195 res = lut3(imm, ra, rb, rc)
200 another mode selection would be CRs not Ints.
202 | 0.5|6.8 | 9.11|12.14|15.17|18.20|21.28 | 29.30|31|
203 | -- | -- | --- | --- | --- |-----|----- | -----|--|
204 | NN | BT | BA | BB | BC |m0-2 | imm | 10 |m3|
208 if not mask[i] continue
209 crregs[BT][i] = lut3(imm,
218 the [[sv/av_opcodes]]
220 signed and unsigned min/max for integer. this is sort-of partly synthesiseable in [[sv/svp64]] with pred-result as long as the dest reg is one of the sources, but not both signed and unsigned. when the dest is also one of the srces and the mv fails due to the CR bittest failing this will only overwrite the dest where the src is greater (or less).
222 signed/unsigned min/max gives more flexibility.
225 uint_xlen_t min(uint_xlen_t rs1, uint_xlen_t rs2)
226 { return (int_xlen_t)rs1 < (int_xlen_t)rs2 ? rs1 : rs2;
228 uint_xlen_t max(uint_xlen_t rs1, uint_xlen_t rs2)
229 { return (int_xlen_t)rs1 > (int_xlen_t)rs2 ? rs1 : rs2;
231 uint_xlen_t minu(uint_xlen_t rs1, uint_xlen_t rs2)
232 { return rs1 < rs2 ? rs1 : rs2;
234 uint_xlen_t maxu(uint_xlen_t rs1, uint_xlen_t rs2)
235 { return rs1 > rs2 ? rs1 : rs2;
242 based on RV bitmanip, covered by ternlog bitops
245 uint_xlen_t cmix(uint_xlen_t RA, uint_xlen_t RB, uint_xlen_t RC) {
246 return (RA & RB) | (RC & ~RB);
253 based on RV bitmanip singlebit set, instruction format similar to shift
254 [[isa/fixedshift]]. bmext is actually covered already (shift-with-mask rldicl but only immediate version).
255 however bitmask-invert is not, and set/clr are not covered, although they can use the same Shift ALU.
257 bmext (RB) version is not the same as rldicl because bmext is a right shift by RC, where rldicl is a left rotate. for the immediate version this does not matter, so a bmexti is not required.
258 bmrev however there is no direct equivalent and consequently a bmrevi is required.
260 bmset (register for mask amount) is particularly useful for creating
261 predicate masks where the length is a dynamic runtime quantity.
262 bmset(RA=0, RB=0, RC=mask) will produce a run of ones of length "mask" in a single instruction without needing to initialise or depend on any other registers.
264 | 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name |
265 | -- | -- | --- | --- | --- | ------- |--| ----- |
266 | NN | RS | RA | RB | RC | mode 010 |Rc| bm* |
268 Immediate-variant is an overwrite form:
270 | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name |
271 | -- | -- | --- | --- | -- | ----- | -------- |--| ---- |
272 | NN | RS | RB | sh | SH | itype | 1000 110 |Rc| bm*i |
278 mask_a = ((1 << x) - 1) & ((1 << 64) - 1)
279 mask_b = ((1 << y) - 1) & ((1 << 64) - 1)
284 mask_a = ((1 << x) - 1) & ((1 << 64) - 1)
285 mask_b = (~((1 << y) - 1)) & ((1 << 64) - 1)
286 return mask_a ^ mask_b
289 uint_xlen_t bmset(RS, RB, sh)
291 int shamt = RB & (XLEN - 1);
293 return RS | (mask << shamt);
296 uint_xlen_t bmclr(RS, RB, sh)
298 int shamt = RB & (XLEN - 1);
300 return RS & ~(mask << shamt);
303 uint_xlen_t bminv(RS, RB, sh)
305 int shamt = RB & (XLEN - 1);
307 return RS ^ (mask << shamt);
310 uint_xlen_t bmext(RS, RB, sh)
312 int shamt = RB & (XLEN - 1);
314 return mask & (RS >> shamt);
318 bitmask extract with reverse. can be done by bit-order-inverting all of RB and getting bits of RB from the opposite end.
320 when RA is zero, no shift occurs. this makes bmextrev useful for
321 simply reversing all bits of a register.
325 rev[0:msb] = rb[msb:0];
328 uint_xlen_t bmextrev(RA, RB, sh)
331 if (RA != 0) shamt = (GPR(RA) & (XLEN - 1));
332 shamt = (XLEN-1)-shamt; # shift other end
333 bra = bitreverse(RB) # swap LSB-MSB
335 return mask & (bra >> shamt);
339 | 0.5|6.10|11.15|16.20|21.26| 27..30 |31| name |
340 | -- | -- | --- | --- | --- | ------- |--| ------ |
341 | NN | RT | RA | RB | sh | 1 011 |Rc| bmrevi |
346 generalised reverse combined with a pair of LUT2s and allowing
347 a constant `0b0101...0101` when RA=0, and an option to invert
348 (including when RA=0, giving a constant 0b1010...1010 as the
349 initial value) provides a wide range of instructions
350 and a means to set regular 64 bit patterns in one
353 the two LUT2s are applied left-half (when not swapping)
354 and right-half (when swapping) so as to allow a wider
357 <img src="/openpower/sv/grevlut2x2.jpg" width=700 />
359 * A value of `0b11001010` for the immediate provides
360 the functionality of a standard "grev".
361 * `0b11101110` provides gorc
363 grevlut should be arranged so as to produce the constants
364 needed to put into bext (bitextract) so as in turn to
365 be able to emulate x86 pmovmask instructions <https://www.felixcloutier.com/x86/pmovmskb>.
366 This only requires 2 instructions (grevlut, bext).
368 Note that if the mask is required to be placed
369 directly into CR Fields (for use as CR Predicate
370 masks rather than a integer mask) then sv.ori
371 may be used instead, bearing in mind that sv.ori
372 is a 64-bit instruction, and `VL` must have been
373 set to the required length:
375 sv.ori./elwid=8 r10.v, r10.v, 0
377 The following settings provide the required mask constants:
379 | RA | RB | imm | iv | result |
380 | ------- | ------- | ---------- | -- | ---------- |
381 | 0x555.. | 0b10 | 0b01101100 | 0 | 0x111111... |
382 | 0x555.. | 0b110 | 0b01101100 | 0 | 0x010101... |
383 | 0x555.. | 0b1110 | 0b01101100 | 0 | 0x00010001... |
384 | 0x555.. | 0b10 | 0b11000110 | 1 | 0x88888... |
385 | 0x555.. | 0b110 | 0b11000110 | 1 | 0x808080... |
386 | 0x555.. | 0b1110 | 0b11000110 | 1 | 0x80008000... |
388 Better diagram showing the correct ordering of shamt (RB). A LUT2
389 is applied to all locations marked in red using the first 4
390 bits of the immediate, and a separate LUT2 applied to all
391 locations in green using the upper 4 bits of the immediate.
393 <img src="/openpower/sv/grevlut.png" width=700 />
395 demo code [[openpower/sv/grevlut.py]]
400 return imm[idx] # idx by LSB0 order
402 dorow(imm8, step_i, chunksize):
404 if (j&chunk_size) == 0
408 step_o[j] = lut2(imm, step_i[j], step_i[j ^ chunk_size])
411 uint64_t grevlut64(uint64_t RA, uint64_t RB, uint8 imm, bool iv)
413 uint64_t x = 0x5555_5555_5555_5555;
414 if (RA != 0) x = GPR(RA);
419 if (shamt & step) x = dorow(imm, x, step)
425 | 0.5|6.10|11.15|16.20 |21..25 | 26....30 |31| name |
426 | -- | -- | --- | --- | ----- | -------- |--| ------ |
427 | NN | RT | RA | s0-4 | im0-4 | im5-7 1 iv |s5| grevlogi |
428 | NN | RT | RA | RB | im0-4 | im5-7 00 |1 | grevlog |
433 based on RV bitmanip, this is also known as a butterfly network. however
434 where a butterfly network allows setting of every crossbar setting in
435 every row and every column, generalised-reverse (grev) only allows
436 a per-row decision: every entry in the same row must either switch or
439 <img src="https://upload.wikimedia.org/wikipedia/commons/thumb/8/8c/Butterfly_Network.jpg/474px-Butterfly_Network.jpg" />
442 uint64_t grev64(uint64_t RA, uint64_t RB)
446 if (shamt & 1) x = ((x & 0x5555555555555555LL) << 1) |
447 ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
448 if (shamt & 2) x = ((x & 0x3333333333333333LL) << 2) |
449 ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
450 if (shamt & 4) x = ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
451 ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
452 if (shamt & 8) x = ((x & 0x00FF00FF00FF00FFLL) << 8) |
453 ((x & 0xFF00FF00FF00FF00LL) >> 8);
454 if (shamt & 16) x = ((x & 0x0000FFFF0000FFFFLL) << 16) |
455 ((x & 0xFFFF0000FFFF0000LL) >> 16);
456 if (shamt & 32) x = ((x & 0x00000000FFFFFFFFLL) << 32) |
457 ((x & 0xFFFFFFFF00000000LL) >> 32);
465 based on RV bitmanip.
467 RA contains a vector of indices to select parts of RB to be
468 copied to RT. The immediate-variant allows up to an 8 bit
469 pattern (repeated) to be targetted at different parts of RT
472 uint_xlen_t xpermi(uint8_t imm8, uint_xlen_t RB, int sz_log2)
475 uint_xlen_t sz = 1LL << sz_log2;
476 uint_xlen_t mask = (1LL << sz) - 1;
477 uint_xlen_t RA = imm8 | imm8<<8 | ... | imm8<<56;
478 for (int i = 0; i < XLEN; i += sz) {
479 uint_xlen_t pos = ((RA >> i) & mask) << sz_log2;
481 r |= ((RB >> pos) & mask) << i;
485 uint_xlen_t xperm(uint_xlen_t RA, uint_xlen_t RB, int sz_log2)
488 uint_xlen_t sz = 1LL << sz_log2;
489 uint_xlen_t mask = (1LL << sz) - 1;
490 for (int i = 0; i < XLEN; i += sz) {
491 uint_xlen_t pos = ((RA >> i) & mask) << sz_log2;
493 r |= ((RB >> pos) & mask) << i;
497 uint_xlen_t xperm_n (uint_xlen_t RA, uint_xlen_t RB)
498 { return xperm(RA, RB, 2); }
499 uint_xlen_t xperm_b (uint_xlen_t RA, uint_xlen_t RB)
500 { return xperm(RA, RB, 3); }
501 uint_xlen_t xperm_h (uint_xlen_t RA, uint_xlen_t RB)
502 { return xperm(RA, RB, 4); }
503 uint_xlen_t xperm_w (uint_xlen_t RA, uint_xlen_t RB)
504 { return xperm(RA, RB, 5); }
512 uint32_t gorc32(uint32_t RA, uint32_t RB)
516 if (shamt & 1) x |= ((x & 0x55555555) << 1) | ((x & 0xAAAAAAAA) >> 1);
517 if (shamt & 2) x |= ((x & 0x33333333) << 2) | ((x & 0xCCCCCCCC) >> 2);
518 if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4) | ((x & 0xF0F0F0F0) >> 4);
519 if (shamt & 8) x |= ((x & 0x00FF00FF) << 8) | ((x & 0xFF00FF00) >> 8);
520 if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16);
523 uint64_t gorc64(uint64_t RA, uint64_t RB)
527 if (shamt & 1) x |= ((x & 0x5555555555555555LL) << 1) |
528 ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
529 if (shamt & 2) x |= ((x & 0x3333333333333333LL) << 2) |
530 ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
531 if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
532 ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
533 if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL) << 8) |
534 ((x & 0xFF00FF00FF00FF00LL) >> 8);
535 if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL) << 16) |
536 ((x & 0xFFFF0000FFFF0000LL) >> 16);
537 if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL) << 32) |
538 ((x & 0xFFFFFFFF00000000LL) >> 32);
543 # Introductory Explanation for Carry-less and Gallois Field
545 There are three completely separate types of Galois Field
546 arithmetic which are not well explained even in introductory
549 * GF(2) which is covered by bibary XOR
551 # Instructions for Carry-less Operations aka. Polynomials with coefficients in `GF(2)`
553 Carry-less addition/subtraction is simply XOR, so a `cladd`
554 instruction is not provided since the `xor[i]` instruction can be used instead.
556 These are operations on polynomials with coefficients in `GF(2)`, with the
557 polynomial's coefficients packed into integers with the following algorithm:
559 [[!inline pagenames="openpower/sv/bitmanip/pack_poly.py" raw="true" feeds="no" actions="yes"]]
561 ## Carry-less Multiply Instructions
564 see <https://en.wikipedia.org/wiki/CLMUL_instruction_set> and
565 <https://www.felixcloutier.com/x86/pclmulqdq> and
566 <https://en.m.wikipedia.org/wiki/Carry-less_product>
568 They are worth adding as their own non-overwrite operations
569 (in the same pipeline).
571 ### `clmul` Carry-less Multiply
573 [[!inline pagenames="openpower/sv/bitmanip/clmul.py" raw="true" feeds="no" actions="yes"]]
575 ### `clmulh` Carry-less Multiply High
577 [[!inline pagenames="openpower/sv/bitmanip/clmulh.py" raw="true" feeds="no" actions="yes"]]
579 ### `clmulr` Carry-less Multiply (Reversed)
581 Useful for CRCs. Equivalent to bit-reversing the result of `clmul` on
584 [[!inline pagenames="openpower/sv/bitmanip/clmulr.py" raw="true" feeds="no" actions="yes"]]
586 ## `clmadd` Carry-less Multiply-Add
589 clmadd RT, RA, RB, RC
593 (RT) = clmul((RA), (RB)) ^ (RC)
596 ## `cltmadd` Twin Carry-less Multiply-Add (for FFTs)
598 Used in combination with SV FFT REMAP to perform a full Discrete Fourier
599 Transform of Polynomials over GF(2) in-place. Possible by having 3-in 2-out,
600 to avoid the need for a temp register. RS is written to as well as RT.
602 Note: Polynomials over GF(2) are a Ring rather than a Field, so, because the
603 definition of the Inverse Discrete Fourier Transform involves calculating a
604 multiplicative inverse, which may not exist in every Ring, therefore the
605 Inverse Discrete Fourier Transform may not exist. (AFAICT the number of inputs
606 to the IDFT must be odd for the IDFT to be defined for Polynomials over GF(2).
607 TODO: check with someone who knows for sure if that's correct.)
610 cltmadd RT, RA, RB, RC
613 TODO: add link to explanation for where `RS` comes from.
618 # read all inputs before writing to any outputs in case
619 # an input overlaps with an output register.
620 (RT) = clmul(a, (RB)) ^ c
624 ## `cldivrem` Carry-less Division and Remainder
626 `cldivrem` isn't an actual instruction, but is just used in the pseudo-code
627 for other instructions.
629 [[!inline pagenames="openpower/sv/bitmanip/cldivrem.py" raw="true" feeds="no" actions="yes"]]
631 ## `cldiv` Carry-less Division
640 q, r = cldivrem(n, d, width=XLEN)
644 ## `clrem` Carry-less Remainder
653 q, r = cldivrem(n, d, width=XLEN)
657 # Instructions for Binary Galois Fields `GF(2^m)`
661 * <https://courses.csail.mit.edu/6.857/2016/files/ffield.py>
662 * <https://engineering.purdue.edu/kak/compsec/NewLectures/Lecture7.pdf>
663 * <https://foss.heptapod.net/math/libgf2/-/blob/branch/default/src/libgf2/gf2.py>
665 Binary Galois Field addition/subtraction is simply XOR, so a `gfbadd`
666 instruction is not provided since the `xor[i]` instruction can be used instead.
668 ## `GFBREDPOLY` SPR -- Reducing Polynomial
670 In order to save registers and to make operations orthogonal with standard
671 arithmetic, the reducing polynomial is stored in a dedicated SPR `GFBREDPOLY`.
672 This also allows hardware to pre-compute useful parameters (such as the
673 degree, or look-up tables) based on the reducing polynomial, and store them
674 alongside the SPR in hidden registers, only recomputing them whenever the SPR
675 is written to, rather than having to recompute those values for every
678 Because Galois Fields require the reducing polynomial to be an irreducible
679 polynomial, that guarantees that any polynomial of `degree > 1` must have
680 the LSB set, since otherwise it would be divisible by the polynomial `x`,
681 making it reducible, making whatever we're working on no longer a Field.
682 Therefore, we can reuse the LSB to indicate `degree == XLEN`.
684 [[!inline pagenames="openpower/sv/bitmanip/decode_reducing_polynomial.py" raw="true" feeds="no" actions="yes"]]
686 ## `gfbredpoly` -- Set the Reducing Polynomial SPR `GFBREDPOLY`
688 unless this is an immediate op, `mtspr` is completely sufficient.
690 [[!inline pagenames="openpower/sv/bitmanip/gfbredpoly.py" raw="true" feeds="no" actions="yes"]]
692 ## `gfbmul` -- Binary Galois Field `GF(2^m)` Multiplication
698 [[!inline pagenames="openpower/sv/bitmanip/gfbmul.py" raw="true" feeds="no" actions="yes"]]
700 ## `gfbmadd` -- Binary Galois Field `GF(2^m)` Multiply-Add
703 gfbmadd RT, RA, RB, RC
706 [[!inline pagenames="openpower/sv/bitmanip/gfbmadd.py" raw="true" feeds="no" actions="yes"]]
708 ## `gfbtmadd` -- Binary Galois Field `GF(2^m)` Twin Multiply-Add (for FFT)
710 Used in combination with SV FFT REMAP to perform a full `GF(2^m)` Discrete
711 Fourier Transform in-place. Possible by having 3-in 2-out, to avoid the need
712 for a temp register. RS is written to as well as RT.
715 gfbtmadd RT, RA, RB, RC
718 TODO: add link to explanation for where `RS` comes from.
723 # read all inputs before writing to any outputs in case
724 # an input overlaps with an output register.
725 (RT) = gfbmadd(a, (RB), c)
726 # use gfbmadd again since it reduces the result
727 (RS) = gfbmadd(a, 1, c) # "a * 1 + c"
730 ## `gfbinv` -- Binary Galois Field `GF(2^m)` Inverse
736 [[!inline pagenames="openpower/sv/bitmanip/gfbinv.py" raw="true" feeds="no" actions="yes"]]
738 # Instructions for Prime Galois Fields `GF(p)`
740 ## `GFPRIME` SPR -- Prime Modulus For `gfp*` Instructions
742 ## `gfpadd` Prime Galois Field `GF(p)` Addition
748 [[!inline pagenames="openpower/sv/bitmanip/gfpadd.py" raw="true" feeds="no" actions="yes"]]
750 the addition happens on infinite-precision integers
752 ## `gfpsub` Prime Galois Field `GF(p)` Subtraction
758 [[!inline pagenames="openpower/sv/bitmanip/gfpsub.py" raw="true" feeds="no" actions="yes"]]
760 the subtraction happens on infinite-precision integers
762 ## `gfpmul` Prime Galois Field `GF(p)` Multiplication
768 [[!inline pagenames="openpower/sv/bitmanip/gfpmul.py" raw="true" feeds="no" actions="yes"]]
770 the multiplication happens on infinite-precision integers
772 ## `gfpinv` Prime Galois Field `GF(p)` Invert
778 Some potential hardware implementations are found in:
779 <https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.90.5233&rep=rep1&type=pdf>
781 [[!inline pagenames="openpower/sv/bitmanip/gfpinv.py" raw="true" feeds="no" actions="yes"]]
783 ## `gfpmadd` Prime Galois Field `GF(p)` Multiply-Add
786 gfpmadd RT, RA, RB, RC
789 [[!inline pagenames="openpower/sv/bitmanip/gfpmadd.py" raw="true" feeds="no" actions="yes"]]
791 the multiplication and addition happens on infinite-precision integers
793 ## `gfpmsub` Prime Galois Field `GF(p)` Multiply-Subtract
796 gfpmsub RT, RA, RB, RC
799 [[!inline pagenames="openpower/sv/bitmanip/gfpmsub.py" raw="true" feeds="no" actions="yes"]]
801 the multiplication and subtraction happens on infinite-precision integers
803 ## `gfpmsubr` Prime Galois Field `GF(p)` Multiply-Subtract-Reversed
806 gfpmsubr RT, RA, RB, RC
809 [[!inline pagenames="openpower/sv/bitmanip/gfpmsubr.py" raw="true" feeds="no" actions="yes"]]
811 the multiplication and subtraction happens on infinite-precision integers
813 ## `gfpmaddsubr` Prime Galois Field `GF(p)` Multiply-Add and Multiply-Sub-Reversed (for FFT)
815 Used in combination with SV FFT REMAP to perform
816 a full Number-Theoretic-Transform in-place. Possible by having 3-in 2-out,
817 to avoid the need for a temp register. RS is written
821 gfpmaddsubr RT, RA, RB, RC
824 TODO: add link to explanation for where `RS` comes from.
830 # read all inputs before writing to any outputs in case
831 # an input overlaps with an output register.
832 (RT) = gfpmadd(factor1, factor2, term)
833 (RS) = gfpmsubr(factor1, factor2, term)
839 uint64_t bmatflip(uint64_t RA)
847 uint64_t bmatxor(uint64_t RA, uint64_t RB)
850 uint64_t RBt = bmatflip(RB);
851 uint8_t u[8]; // rows of RA
852 uint8_t v[8]; // cols of RB
853 for (int i = 0; i < 8; i++) {
858 for (int i = 0; i < 64; i++) {
859 if (pcnt(u[i / 8] & v[i % 8]) & 1)
864 uint64_t bmator(uint64_t RA, uint64_t RB)
867 uint64_t RBt = bmatflip(RB);
868 uint8_t u[8]; // rows of RA
869 uint8_t v[8]; // cols of RB
870 for (int i = 0; i < 8; i++) {
875 for (int i = 0; i < 64; i++) {
876 if ((u[i / 8] & v[i % 8]) != 0)
884 # Already in POWER ISA
886 ## count leading/trailing zeros with mask
892 do i = 0 to 63 if((RB)i=1) then do
893 if((RS)i=1) then break end end count ← count + 1
899 vpdepd VRT,VRA,VRB, identical to RV bitmamip bdep, found already in v3.1 p106
902 if VSR[VRB+32].dword[i].bit[63-m]=1 then do
903 result = VSR[VRA+32].dword[i].bit[63-k]
904 VSR[VRT+32].dword[i].bit[63-m] = result
910 uint_xlen_t bdep(uint_xlen_t RA, uint_xlen_t RB)
913 for (int i = 0, j = 0; i < XLEN; i++)
916 r |= uint_xlen_t(1) << i;
926 other way round: identical to RV bext, found in v3.1 p196
929 uint_xlen_t bext(uint_xlen_t RA, uint_xlen_t RB)
932 for (int i = 0, j = 0; i < XLEN; i++)
935 r |= uint_xlen_t(1) << j;
944 found in v3.1 p106 so not to be added here
954 if((RB)63-i==1) then do
955 result63-ptr1 = (RS)63-i
961 # bit to byte permute
963 similar to matrix permute in RV bitmanip, which has XOR and OR variants,
964 these perform a transpose.
968 b = VSR[VRB+32].dword[i].byte[k].bit[j]
969 VSR[VRT+32].dword[i].byte[j].bit[k] = b