7 * ternlogi <https://bugs.libre-soc.org/show_bug.cgi?id=745>
8 * grev <https://bugs.libre-soc.org/show_bug.cgi?id=755>
9 * GF2^M <https://bugs.libre-soc.org/show_bug.cgi?id=782>
16 pseudocode: [[openpower/isa/bitmanip]]
18 this extension amalgamates bitmanipulation primitives from many sources,
19 including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX.
20 Also included are DSP/Multimedia operations suitable for Audio/Video.
21 Vectorisation and SIMD are removed: these are straight scalar (element)
22 operations making them suitable for embedded applications. Vectorisation
23 Context is provided by [[openpower/sv]].
25 When combined with SV, scalar variants of bitmanip operations found in
26 VSX are added so that the Packed SIMD aspects of VSX may be retired as
27 "legacy" in the far future (10 to 20 years). Also, VSX is hundreds of
28 opcodes, requires 128 bit pathways, and is wholly unsuited to low power
29 or embedded scenarios.
31 ternlogv is experimental and is the only operation that may be considered
32 a "Packed SIMD". It is added as a variant of the already well-justified
33 ternlog operation (done in AVX512 as an immediate only) "because it
34 looks fun". As it is based on the LUT4 concept it will allow accelerated
35 emulation of FPGAs. Other vendors of ISAs are buying FPGA companies to
36 achieve similar objectives.
38 general-purpose Galois Field 2^M operations are added so as to avoid
39 huge custom opcode proliferation across many areas of Computer Science.
40 however for convenience and also to avoid setup costs, some of the more
41 common operations (clmul, crc32) are also added. The expectation is
42 that these operations would all be covered by the same pipeline.
44 note that there are brownfield spaces below that could incorporate
45 some of the set-before-first and other scalar operations listed in
46 [[sv/vector_ops]], [[sv/int_fp_mv]] and the [[sv/av_opcodes]] as well as
47 [[sv/setvl]], [[sv/svstep]], [[sv/remap]]
51 * <https://en.wikiversity.org/wiki/Reed%E2%80%93Solomon_codes_for_coders>
52 * <https://maths-people.anu.edu.au/~brent/pd/rpb232tr.pdf>
56 two major opcodes are needed
58 ternlog has its own major opcode
60 | 29.30 |31| name | Form |
61 | ------ |--| --------- | ---- |
62 | 0 0 |Rc| ternlogi | TLI-Form |
63 | 0 1 | | crternlogi | TLI-Form |
64 | 1 iv | | grevlogi | TLI-Form |
66 2nd major opcode for other bitmanip: minor opcode allocation
69 | ------ |--| --------- |
71 | -00 |1 | binary lut |
82 | dest | src1 | subop | op |
83 | ---- | ---- | ----- | -------- |
84 | RT | RA | .. | bmatflip |
88 | dest | src1 | src2 | subop | op |
89 | ---- | ---- | ---- | ----- | -------- |
90 | RT | RA | RB | or | bmatflip |
91 | RT | RA | RB | xor | bmatflip |
92 | RT | RA | RB | | grev |
93 | RT | RA | RB | | clmul\* |
94 | RT | RA | RB | | gorc |
95 | RT | RA | RB | shuf | shuffle |
96 | RT | RA | RB | unshuf| shuffle |
97 | RT | RA | RB | width | xperm |
98 | RT | RA | RB | type | av minmax |
99 | RT | RA | RB | | av abs avgadd |
100 | RT | RA | RB | type | vmask ops |
101 | RT | RA | RB | type | abs accumulate (overwrite) |
109 TODO: convert all instructions to use RT and not RS
111 | 0.5|6.10|11.15|16.20 |21..25 | 26....30 |31| name | Form |
112 | -- | -- | --- | --- | ----- | -------- |--| ------ | -------- |
113 | NN | RT | RA |itype/| im0-4 | im5-7 00 |0 | xpermi | TLI-Form |
114 | NN | RT | RA | RB | RC | nh 00 00 |1 | binlut | VA-Form |
115 | NN | RT | RA | RB | /BFA/ | 0 01 00 |1 | bincrflut | VA-Form |
116 | NN | | | | | 1 01 00 |1 | rsvd | |
117 | NN | | | | | - 10 00 |1 | rsvd | |
118 | NN | | | | | 0 11 00 |1 | svshape | SVM-Form |
119 | NN | | | | | 1 11 00 |1 | svremap | SVRM-Form |
120 | NN | RT | RA | RB | im0-4 | im5-7 01 |0 | grevlog | TLI-Form |
121 | NN | RT | RA | RB | im0-4 | im5-7 01 |1 | grevlogw | TLI-Form |
122 | NN | RT | RA | RB | RC | mode 010 |Rc| bitmask\* | VA2-Form |
123 | NN |FRS | d1 | d0 | d0 | 00 011 |d2| fmvis | DX-Form |
124 | NN |FRS | d1 | d0 | d0 | 01 011 |d2| fishmv | DX-Form |
125 | NN | | | | | 10 011 |Rc| svstep | SVL-Form |
126 | NN | | | | | 11 011 |Rc| setvl | SVL-Form |
127 | NN | | | | | ---- 110 | | 1/2 ops | other table [1] |
128 | NN | RT | RA | RB | RC | 11 110 |Rc| bmrev | VA2-Form |
129 | NN | RT | RA | RB | sh0-4 | sh5 1 111 |Rc| bmrevi | MDS-Form |
133 ops (note that av avg and abs as well as vec scalar mask
134 are included here [[sv/vector_ops]], and
135 the [[sv/av_opcodes]])
137 | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name | Form |
138 | -- | -- | --- | --- | -- | ----- | -------- |--| ---- | ------- |
139 | NN | RS | me | sh | SH | ME 0 | nn00 110 |Rc| bmopsi | BM-Form |
140 | NN | RS | RA | sh | SH | 0 1 | nn00 110 |Rc| bmopsi | XB-Form |
141 | NN | RS | RA |im04 | im5| 1 1 | im67 00 110 |Rc| bmatxori | TODO |
142 | NN | RT | RA | RB | 1 | 00 | 0001 110 |Rc| cldiv | X-Form |
143 | NN | RT | RA | RB | 1 | 01 | 0001 110 |Rc| clmod | X-Form |
144 | NN | RT | RA | | 1 | 10 | 0001 110 |Rc| clmulh | X-Form |
145 | NN | RT | RA | RB | 1 | 11 | 0001 110 |Rc| clmul | X-Form |
146 | NN | RT | RA | RB | 0 | 00 | 0001 110 |Rc| vec sbfm | X-Form |
147 | NN | RT | RA | RB | 0 | 01 | 0001 110 |Rc| vec sofm | X-Form |
148 | NN | RT | RA | RB | 0 | 10 | 0001 110 |Rc| vec sifm | X-Form |
149 | NN | RT | RA | RB | 0 | 11 | 0001 110 |Rc| vec cprop | X-Form |
150 | NN | | | | | -0 | 0101 110 |Rc| crfbinlog | {TODO} |
151 | NN | | | | | -1 | 0101 110 |Rc| rsvd | |
152 | NN | RT | RA | RB | 0 | itype | 1001 110 |Rc| av minmax | X-Form |
153 | NN | RT | RA | RB | 1 | 00 | 1001 110 |Rc| av abss | X-Form |
154 | NN | RT | RA | RB | 1 | 01 | 1001 110 |Rc| av absu | X-Form |
155 | NN | RT | RA | RB | 1 | 10 | 1001 110 |Rc| av avgadd | X-Form |
156 | NN | RT | RA | RB | 1 | 11 | 1001 110 |Rc| grevlutr | X-Form |
157 | NN | RT | RA | RB | 0 | itype | 1101 110 |Rc| shadd | X-Form |
158 | NN | RT | RA | RB | 1 | itype | 1101 110 |Rc| shadduw | X-Form |
159 | NN | RT | RA | RB | 0 | 00 | 0010 110 |Rc| gorc | X-Form |
160 | NN | RS | RA | sh | SH | 00 | 1010 110 |Rc| gorci | XB-Form |
161 | NN | RT | RA | RB | 0 | 00 | 0110 110 |Rc| gorcw | X-Form |
162 | NN | RS | RA | SH | 0 | 00 | 1110 110 |Rc| gorcwi | X-Form |
163 | NN | RT | RA | RB | 1 | 00 | 1110 110 |Rc| rsvd | |
164 | NN | RT | RA | RB | 0 | 01 | 0010 110 |Rc| grev | X-Form |
165 | NN | RT | RA | RB | 1 | 01 | 0010 110 |Rc| clmulr | X-Form |
166 | NN | RS | RA | sh | SH | 01 | 1010 110 |Rc| grevi | XB-Form |
167 | NN | RT | RA | RB | 0 | 01 | 0110 110 |Rc| grevw | X-Form |
168 | NN | RS | RA | SH | 0 | 01 | 1110 110 |Rc| grevwi | X-Form |
169 | NN | RT | RA | RB | 1 | 01 | 1110 110 |Rc| rsvd | |
170 | NN | RS | RA | RB | 0 | 10 | 0010 110 |Rc| bmator | X-Form |
171 | NN | RS | RA | RB | 0 | 10 | 0110 110 |Rc| bmatand | X-Form |
172 | NN | RS | RA | RB | 0 | 10 | 1010 110 |Rc| bmatxor | X-Form |
173 | NN | RS | RA | RB | 0 | 10 | 1110 110 |Rc| bmatflip | X-Form |
174 | NN | RT | RA | RB | 1 | 10 | 0010 110 |Rc| xpermn | X-Form |
175 | NN | RT | RA | RB | 1 | 10 | 0110 110 |Rc| xpermb | X-Form |
176 | NN | RT | RA | RB | 1 | 10 | 1010 110 |Rc| xpermh | X-Form |
177 | NN | RT | RA | RB | 1 | 10 | 1110 110 |Rc| xpermw | X-Form |
178 | NN | RT | RA | RB | 0 | 11 | 1110 110 |Rc| abssa | X-Form |
179 | NN | RT | RA | RB | 1 | 11 | 1110 110 |Rc| absua | X-Form |
180 | NN | | | | | | --11 110 |Rc| bmrev | VA2-Form |
182 # binary and ternary bitops
184 Similar to FPGA LUTs: for two (binary) or three (ternary) inputs take
185 bits from each input, concatenate them and perform a lookup into a
186 table using an 8-8-bit immediate (for the ternary instructions), or in
187 another register (4-bit for the binary instructions). The binary lookup
188 instructions have CR Field lookup variants due to CR Fields being 4 bit.
191 [vpternlogd/vpternlogq](https://www.felixcloutier.com/x86/vpternlogd:vpternlogq)
196 | 0.5|6.10|11.15|16.20| 21..28|29.30|31|
197 | -- | -- | --- | --- | ----- | --- |--|
198 | NN | RT | RA | RB | im0-7 | 00 |Rc|
201 idx = c << 2 | b << 1 | a
202 return imm[idx] # idx by LSB0 order
205 RT[i] = lut3(imm, RB[i], RA[i], RT[i])
209 Binary lookup is a dynamic LUT2 version of ternlogi. Firstly, the
210 lookup table is 4 bits wide not 8 bits, and secondly the lookup
211 table comes from a register not an immediate.
213 | 0.5|6.10|11.15|16.20| 21..25|26..31 | Form |
214 | -- | -- | --- | --- | ----- |--------|---------|
215 | NN | RT | RA | RB | RC |nh 00001| VA-Form |
216 | NN | RT | RA | RB | /BFA/ |0 01001| VA-Form |
218 For binlut, the 4-bit LUT may be selected from either the high nibble
219 or the low nibble of the first byte of RC:
223 return imm[idx] # idx by LSB0 order
225 imm = (RC>>(nh*4))&0b1111
227 RT[i] = lut2(imm, RB[i], RA[i])
229 For bincrlut, `BFA` selects the 4-bit CR Field as the LUT2:
232 RT[i] = lut2(CRs{BFA}, RB[i], RA[i])
234 When Vectorised with SVP64, as usual both source and destination may be
237 *Programmer's note: a dynamic ternary lookup may be synthesised from
238 a pair of `binlut` instructions followed by a `ternlogi` to select which
239 to merge. Use `nh` to select which nibble to use as the lookup table
240 from the RC source register (`nh=1` nibble high), i.e. keeping
241 an 8-bit LUT3 in RC, the first `binlut` instruction may set nh=0 and
246 another mode selection would be CRs not Ints.
248 | 0.5|6.8 | 9.11|12.14|15.17|18.20|21.28 | 29.30|31|
249 | -- | -- | --- | --- | --- |-----|----- | -----|--|
250 | NN | BT | BA | BB | BC |m0-2 | imm | 01 |m3|
254 a,b,c = CRs[BA][i], CRs[BB][i], CRs[BC][i])
255 if mask[i] CRs[BT][i] = lut3(imm, a, b, c)
257 This instruction is remarkably similar to the existing crops, `crand` etc.
258 which have been noted to be a 4-bit (binary) LUT. In effect `crternlogi`
259 is the ternary LUT version of crops, having an 8-bit LUT.
263 With ternary (LUT3) dynamic instructions being very costly,
264 and CR Fields being only 4 bit, a binary (LUT2) variant is better
266 | 0.5|6.8 | 9.11|12.14|15.17|18.22|23...30 |31|
267 | -- | -- | --- | --- | --- |-----| --------|--|
268 | NN | BT | BA | BB | BC |m0-m2|00101110 |m3|
272 a,b = CRs[BA][i], CRs[BB][i])
273 if mask[i] CRs[BT][i] = lut2(CRs[BC], a, b)
275 When SVP64 Vectorised any of the 4 operands may be Scalar or
276 Vector, including `BC` meaning that multiple different dynamic
277 lookups may be performed with a single instruction.
279 *Programmer's note: just as with binlut and ternlogi, a pair
280 of crbinlog instructions followed by a merging crternlogi may
281 be deployed to synthesise dynamic ternary (LUT3) CR Field
288 required for the [[sv/av_opcodes]]
290 signed and unsigned min/max for integer. this is sort-of partly
291 synthesiseable in [[sv/svp64]] with pred-result as long as the dest reg
292 is one of the sources, but not both signed and unsigned. when the dest
293 is also one of the srces and the mv fails due to the CR bittest failing
294 this will only overwrite the dest where the src is greater (or less).
296 signed/unsigned min/max gives more flexibility.
299 uint_xlen_t min(uint_xlen_t rs1, uint_xlen_t rs2)
300 { return (int_xlen_t)rs1 < (int_xlen_t)rs2 ? rs1 : rs2;
302 uint_xlen_t max(uint_xlen_t rs1, uint_xlen_t rs2)
303 { return (int_xlen_t)rs1 > (int_xlen_t)rs2 ? rs1 : rs2;
305 uint_xlen_t minu(uint_xlen_t rs1, uint_xlen_t rs2)
306 { return rs1 < rs2 ? rs1 : rs2;
308 uint_xlen_t maxu(uint_xlen_t rs1, uint_xlen_t rs2)
309 { return rs1 > rs2 ? rs1 : rs2;
315 required for the [[sv/av_opcodes]], these exist in Packed SIMD (VSX)
319 uint_xlen_t intavg(uint_xlen_t rs1, uint_xlen_t rs2) {
320 return (rs1 + rs2 + 1) >> 1:
326 required for the [[sv/av_opcodes]], these exist in Packed SIMD (VSX)
330 uint_xlen_t intabs(uint_xlen_t rs1, uint_xlen_t rs2) {
331 return (src1 > src2) ? (src1-src2) : (src2-src1)
337 required for the [[sv/av_opcodes]], these are needed for motion estimation.
338 both are overwrite on RS.
341 uint_xlen_t uintabsacc(uint_xlen_t rs, uint_xlen_t ra, uint_xlen_t rb) {
342 return rs + (src1 > src2) ? (src1-src2) : (src2-src1)
344 uint_xlen_t intabsacc(uint_xlen_t rs, int_xlen_t ra, int_xlen_t rb) {
345 return rs + (src1 > src2) ? (src1-src2) : (src2-src1)
349 For SVP64, the twin Elwidths allows e.g. a 16 bit accumulator for 8 bit
350 differences. Form is `RM-1P-3S1D` where RS-as-source has a separate
351 SVP64 designation from RS-as-dest. This gives a limited range of
352 non-overwrite capability.
356 Power ISA is missing LD/ST with shift, which is present in both ARM and x86.
357 Too complex to add more LD/ST, a compromise is to add shift-and-add.
358 Replaces a pair of explicit instructions in hot-loops.
361 uint_xlen_t shadd(uint_xlen_t rs1, uint_xlen_t rs2, uint8_t sh) {
362 return (rs1 << (sh+1)) + rs2;
365 uint_xlen_t shadduw(uint_xlen_t rs1, uint_xlen_t rs2, uint8_t sh) {
366 uint_xlen_t rs1z = rs1 & 0xFFFFFFFF;
367 return (rs1z << (sh+1)) + rs2;
373 based on RV bitmanip singlebit set, instruction format similar to shift
374 [[isa/fixedshift]]. bmext is actually covered already (shift-with-mask
375 rldicl but only immediate version). however bitmask-invert is not,
376 and set/clr are not covered, although they can use the same Shift ALU.
378 bmext (RB) version is not the same as rldicl because bmext is a right
379 shift by RC, where rldicl is a left rotate. for the immediate version
380 this does not matter, so a bmexti is not required. bmrev however there
381 is no direct equivalent and consequently a bmrevi is required.
383 bmset (register for mask amount) is particularly useful for creating
384 predicate masks where the length is a dynamic runtime quantity.
385 bmset(RA=0, RB=0, RC=mask) will produce a run of ones of length "mask"
386 in a single instruction without needing to initialise or depend on any
389 | 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name |
390 | -- | -- | --- | --- | --- | ------- |--| ----- |
391 | NN | RS | RA | RB | RC | mode 010 |Rc| bm\* |
393 Immediate-variant is an overwrite form:
395 | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name |
396 | -- | -- | --- | --- | -- | ----- | -------- |--| ---- |
397 | NN | RS | RB | sh | SH | itype | 1000 110 |Rc| bm\*i |
403 mask_a = ((1 << x) - 1) & ((1 << 64) - 1)
404 mask_b = ((1 << y) - 1) & ((1 << 64) - 1)
409 mask_a = ((1 << x) - 1) & ((1 << 64) - 1)
410 mask_b = (~((1 << y) - 1)) & ((1 << 64) - 1)
411 return mask_a ^ mask_b
414 uint_xlen_t bmset(RS, RB, sh)
416 int shamt = RB & (XLEN - 1);
418 return RS | (mask << shamt);
421 uint_xlen_t bmclr(RS, RB, sh)
423 int shamt = RB & (XLEN - 1);
425 return RS & ~(mask << shamt);
428 uint_xlen_t bminv(RS, RB, sh)
430 int shamt = RB & (XLEN - 1);
432 return RS ^ (mask << shamt);
435 uint_xlen_t bmext(RS, RB, sh)
437 int shamt = RB & (XLEN - 1);
439 return mask & (RS >> shamt);
443 bitmask extract with reverse. can be done by bit-order-inverting all
444 of RB and getting bits of RB from the opposite end.
446 when RA is zero, no shift occurs. this makes bmextrev useful for
447 simply reversing all bits of a register.
451 rev[0:msb] = rb[msb:0];
454 uint_xlen_t bmrevi(RA, RB, sh)
457 if (RA != 0) shamt = (GPR(RA) & (XLEN - 1));
458 shamt = (XLEN-1)-shamt; # shift other end
459 brb = bitreverse(GPR(RB)) # swap LSB-MSB
461 return mask & (brb >> shamt);
464 uint_xlen_t bmrev(RA, RB, RC) {
465 return bmrevi(RA, RB, GPR(RC) & 0b111111);
469 | 0.5|6.10|11.15|16.20|21.26| 27..30 |31| name | Form |
470 | -- | -- | --- | --- | --- | ------- |--| ------ | -------- |
471 | NN | RT | RA | RB | sh | 1111 |Rc| bmrevi | MDS-Form |
473 | 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name | Form |
474 | -- | -- | --- | --- | --- | ------- |--| ------ | -------- |
475 | NN | RT | RA | RB | RC | 11110 |Rc| bmrev | VA2-Form |
477 # grevlut <a name="grevlut"> </a>
479 ([3x lower latency alternative](grev_gorc_design/) which is
480 not equivalent and has limited constant-generation capability)
482 generalised reverse combined with a pair of LUT2s and allowing
483 a constant `0b0101...0101` when RA=0, and an option to invert
484 (including when RA=0, giving a constant 0b1010...1010 as the
485 initial value) provides a wide range of instructions
486 and a means to set hundreds of regular 64 bit patterns with one
487 single 32 bit instruction.
489 the two LUT2s are applied left-half (when not swapping)
490 and right-half (when swapping) so as to allow a wider
493 <img src="/openpower/sv/grevlut2x2.jpg" width=700 />
495 * A value of `0b11001010` for the immediate provides
496 the functionality of a standard "grev".
497 * `0b11101110` provides gorc
499 grevlut should be arranged so as to produce the constants
500 needed to put into bext (bitextract) so as in turn to
501 be able to emulate x86 pmovmask instructions
502 <https://www.felixcloutier.com/x86/pmovmskb>.
503 This only requires 2 instructions (grevlut, bext).
505 Note that if the mask is required to be placed
506 directly into CR Fields (for use as CR Predicate
507 masks rather than a integer mask) then sv.cmpi or sv.ori
508 may be used instead, bearing in mind that sv.ori
509 is a 64-bit instruction, and `VL` must have been
510 set to the required length:
512 sv.ori./elwid=8 r10.v, r10.v, 0
514 The following settings provide the required mask constants:
516 | RA=0 | RB | imm | iv | result |
517 | ------- | ------- | ---------- | -- | ---------- |
518 | 0x555.. | 0b10 | 0b01101100 | 0 | 0x111111... |
519 | 0x555.. | 0b110 | 0b01101100 | 0 | 0x010101... |
520 | 0x555.. | 0b1110 | 0b01101100 | 0 | 0x00010001... |
521 | 0x555.. | 0b10 | 0b11000110 | 1 | 0x88888... |
522 | 0x555.. | 0b110 | 0b11000110 | 1 | 0x808080... |
523 | 0x555.. | 0b1110 | 0b11000110 | 1 | 0x80008000... |
525 Better diagram showing the correct ordering of shamt (RB). A LUT2
526 is applied to all locations marked in red using the first 4
527 bits of the immediate, and a separate LUT2 applied to all
528 locations in green using the upper 4 bits of the immediate.
530 <img src="/openpower/sv/grevlut.png" width=700 />
532 demo code [[openpower/sv/grevlut.py]]
537 return imm[idx] # idx by LSB0 order
539 dorow(imm8, step_i, chunksize, us32b):
540 for j in 0 to 31 if is32b else 63:
541 if (j&chunk_size) == 0
545 step_o[j] = lut2(imm, step_i[j], step_i[j ^ chunk_size])
548 uint64_t grevlut(uint64_t RA, uint64_t RB, uint8 imm, bool iv, bool is32b)
550 uint64_t x = 0x5555_5555_5555_5555;
551 if (RA != 0) x = GPR(RA);
553 int shamt = RB & 31 if is32b else 63
554 for i in 0 to (6-is32b)
556 if (shamt & step) x = dorow(imm, x, step, is32b)
561 A variant may specify different LUT-pairs per row,
562 using one byte of RB for each. If it is desired that
563 a particular row-crossover shall not be applied it is
564 a simple matter to set the appropriate LUT-pair in RB
565 to effect an identity transform for that row (`0b11001010`).
568 uint64_t grevlutr(uint64_t RA, uint64_t RB, bool iv, bool is32b)
570 uint64_t x = 0x5555_5555_5555_5555;
571 if (RA != 0) x = GPR(RA);
573 for i in 0 to (6-is32b)
575 imm = (RB>>(i*8))&0xff
576 x = dorow(imm, x, step, is32b)
582 | 0.5|6.10|11.15|16.20 |21..28 | 29.30|31| name | Form |
583 | -- | -- | --- | --- | ----- | -----|--| ------ | ----- |
584 | NN | RT | RA | s0-4 | im0-7 | 1 iv |s5| grevlogi | |
585 | NN | RT | RA | RB | im0-7 | 01 |0 | grevlog | |
586 | NN | RT | RA | RB | im0-7 | 01 |1 | grevlogw | |
590 superceded by grevlut
592 based on RV bitmanip, this is also known as a butterfly network. however
593 where a butterfly network allows setting of every crossbar setting in
594 every row and every column, generalised-reverse (grev) only allows
595 a per-row decision: every entry in the same row must either switch or
598 <img src="https://upload.wikimedia.org/wikipedia/commons/thumb/8/8c/Butterfly_Network.jpg/474px-Butterfly_Network.jpg" />
601 uint64_t grev64(uint64_t RA, uint64_t RB)
605 if (shamt & 1) x = ((x & 0x5555555555555555LL) << 1) |
606 ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
607 if (shamt & 2) x = ((x & 0x3333333333333333LL) << 2) |
608 ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
609 if (shamt & 4) x = ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
610 ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
611 if (shamt & 8) x = ((x & 0x00FF00FF00FF00FFLL) << 8) |
612 ((x & 0xFF00FF00FF00FF00LL) >> 8);
613 if (shamt & 16) x = ((x & 0x0000FFFF0000FFFFLL) << 16) |
614 ((x & 0xFFFF0000FFFF0000LL) >> 16);
615 if (shamt & 32) x = ((x & 0x00000000FFFFFFFFLL) << 32) |
616 ((x & 0xFFFFFFFF00000000LL) >> 32);
624 based on RV bitmanip, gorc is superceded by grevlut
627 uint32_t gorc32(uint32_t RA, uint32_t RB)
631 if (shamt & 1) x |= ((x & 0x55555555) << 1) | ((x & 0xAAAAAAAA) >> 1);
632 if (shamt & 2) x |= ((x & 0x33333333) << 2) | ((x & 0xCCCCCCCC) >> 2);
633 if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4) | ((x & 0xF0F0F0F0) >> 4);
634 if (shamt & 8) x |= ((x & 0x00FF00FF) << 8) | ((x & 0xFF00FF00) >> 8);
635 if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16);
638 uint64_t gorc64(uint64_t RA, uint64_t RB)
642 if (shamt & 1) x |= ((x & 0x5555555555555555LL) << 1) |
643 ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
644 if (shamt & 2) x |= ((x & 0x3333333333333333LL) << 2) |
645 ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
646 if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
647 ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
648 if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL) << 8) |
649 ((x & 0xFF00FF00FF00FF00LL) >> 8);
650 if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL) << 16) |
651 ((x & 0xFFFF0000FFFF0000LL) >> 16);
652 if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL) << 32) |
653 ((x & 0xFFFFFFFF00000000LL) >> 32);
661 based on RV bitmanip.
663 RA contains a vector of indices to select parts of RB to be
664 copied to RT. The immediate-variant allows up to an 8 bit
665 pattern (repeated) to be targetted at different parts of RT.
667 xperm shares some similarity with one of the uses of bmator
668 in that xperm indices are binary addressing where bitmator
669 may be considered to be unary addressing.
672 uint_xlen_t xpermi(uint8_t imm8, uint_xlen_t RB, int sz_log2)
675 uint_xlen_t sz = 1LL << sz_log2;
676 uint_xlen_t mask = (1LL << sz) - 1;
677 uint_xlen_t RA = imm8 | imm8<<8 | ... | imm8<<56;
678 for (int i = 0; i < XLEN; i += sz) {
679 uint_xlen_t pos = ((RA >> i) & mask) << sz_log2;
681 r |= ((RB >> pos) & mask) << i;
685 uint_xlen_t xperm(uint_xlen_t RA, uint_xlen_t RB, int sz_log2)
688 uint_xlen_t sz = 1LL << sz_log2;
689 uint_xlen_t mask = (1LL << sz) - 1;
690 for (int i = 0; i < XLEN; i += sz) {
691 uint_xlen_t pos = ((RA >> i) & mask) << sz_log2;
693 r |= ((RB >> pos) & mask) << i;
697 uint_xlen_t xperm_n (uint_xlen_t RA, uint_xlen_t RB)
698 { return xperm(RA, RB, 2); }
699 uint_xlen_t xperm_b (uint_xlen_t RA, uint_xlen_t RB)
700 { return xperm(RA, RB, 3); }
701 uint_xlen_t xperm_h (uint_xlen_t RA, uint_xlen_t RB)
702 { return xperm(RA, RB, 4); }
703 uint_xlen_t xperm_w (uint_xlen_t RA, uint_xlen_t RB)
704 { return xperm(RA, RB, 5); }
709 bmatflip and bmatxor is found in the Cray XMT, and in x86 is known
710 as GF2P8AFFINEQB. uses:
712 * <https://gist.github.com/animetosho/d3ca95da2131b5813e16b5bb1b137ca0>
713 * SM4, Reed Solomon, RAID6
714 <https://stackoverflow.com/questions/59124720/what-are-the-avx-512-galois-field-related-instructions-for>
715 * Vector bit-reverse <https://reviews.llvm.org/D91515?id=305411>
716 * Affine Inverse <https://github.com/HJLebbink/asm-dude/wiki/GF2P8AFFINEINVQB>
718 | 0.5|6.10|11.15|16.20 |21..28 | 29.30|31| name | Form |
719 | -- | -- | --- | --- | ----- | -----|--| ------ | ----- |
720 | NN | RT | RA | RB | im0-7 | 01 |1 | bmatxori | |
722 | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name | Form |
723 | -- | -- | --- | --- | -- | ----- | -------- |--| ---- | ------- |
724 | NN | RS | RA |im04 | im5| 1 1 | im67 00 110 |Rc| bmatxori | TODO |
728 uint64_t bmatflip(uint64_t RA)
737 uint64_t bmatxori(uint64_t RS, uint64_t RA, uint8_t imm) {
739 uint64_t RAt = bmatflip(RA);
740 uint8_t u[8]; // rows of RS
741 uint8_t v[8]; // cols of RA
742 for (int i = 0; i < 8; i++) {
747 for (int i = 0; i < 64; i++) {
748 bit = (imm >> (i%8)) & 1;
749 bit ^= pcnt(u[i / 8] & v[i % 8]) & 1;
755 uint64_t bmatxor(uint64_t RA, uint64_t RB) {
756 return bmatxori(RA, RB, 0xff)
759 uint64_t bmator(uint64_t RA, uint64_t RB) {
761 uint64_t RBt = bmatflip(RB);
762 uint8_t u[8]; // rows of RA
763 uint8_t v[8]; // cols of RB
764 for (int i = 0; i < 8; i++) {
769 for (int i = 0; i < 64; i++) {
770 if ((u[i / 8] & v[i % 8]) != 0)
776 uint64_t bmatand(uint64_t RA, uint64_t RB) {
778 uint64_t RBt = bmatflip(RB);
779 uint8_t u[8]; // rows of RA
780 uint8_t v[8]; // cols of RB
781 for (int i = 0; i < 8; i++) {
786 for (int i = 0; i < 64; i++) {
787 if ((u[i / 8] & v[i % 8]) == 0xff)
794 # Introduction to Carry-less and GF arithmetic
796 * obligatory xkcd <https://xkcd.com/2595/>
798 There are three completely separate types of Galois-Field-based arithmetic
799 that we implement which are not well explained even in introductory
800 literature. A slightly oversimplified explanation is followed by more
801 accurate descriptions:
803 * `GF(2)` carry-less binary arithmetic. this is not actually a Galois Field,
804 but is accidentally referred to as GF(2) - see below as to why.
805 * `GF(p)` modulo arithmetic with a Prime number, these are "proper"
807 * `GF(2^N)` carry-less binary arithmetic with two limits: modulo a power-of-2
808 (2^N) and a second "reducing" polynomial (similar to a prime number), these
809 are said to be GF(2^N) arithmetic.
811 further detailed and more precise explanations are provided below
813 * **Polynomials with coefficients in `GF(2)`**
814 (aka. Carry-less arithmetic -- the `cl*` instructions).
815 This isn't actually a Galois Field, but its coefficients are. This is
816 basically binary integer addition, subtraction, and multiplication like
817 usual, except that carries aren't propagated at all, effectively turning
818 both addition and subtraction into the bitwise xor operation. Division and
819 remainder are defined to match how addition and multiplication works.
820 * **Galois Fields with a prime size**
821 (aka. `GF(p)` or Prime Galois Fields -- the `gfp*` instructions).
822 This is basically just the integers mod `p`.
823 * **Galois Fields with a power-of-a-prime size**
824 (aka. `GF(p^n)` or `GF(q)` where `q == p^n` for prime `p` and
826 We only implement these for `p == 2`, called Binary Galois Fields
827 (`GF(2^n)` -- the `gfb*` instructions).
828 For any prime `p`, `GF(p^n)` is implemented as polynomials with
829 coefficients in `GF(p)` and degree `< n`, where the polynomials are the
830 remainders of dividing by a specificly chosen polynomial in `GF(p)` called
831 the Reducing Polynomial (we will denote that by `red_poly`). The Reducing
832 Polynomial must be an irreducable polynomial (like primes, but for
833 polynomials), as well as have degree `n`. All `GF(p^n)` for the same `p`
834 and `n` are isomorphic to each other -- the choice of `red_poly` doesn't
835 affect `GF(p^n)`'s mathematical shape, all that changes is the specific
836 polynomials used to implement `GF(p^n)`.
838 Many implementations and much of the literature do not make a clear
839 distinction between these three categories, which makes it confusing
840 to understand what their purpose and value is.
842 * carry-less multiply is extremely common and is used for the ubiquitous
843 CRC32 algorithm. [TODO add many others, helps justify to ISA WG]
844 * GF(2^N) forms the basis of Rijndael (the current AES standard) and
845 has significant uses throughout cryptography
846 * GF(p) is the basis again of a significant quantity of algorithms
847 (TODO, list them, jacob knows what they are), even though the
848 modulo is limited to be below 64-bit (size of a scalar int)
850 # Instructions for Carry-less Operations
852 aka. Polynomials with coefficients in `GF(2)`
854 Carry-less addition/subtraction is simply XOR, so a `cladd`
855 instruction is not provided since the `xor[i]` instruction can be used instead.
857 These are operations on polynomials with coefficients in `GF(2)`, with the
858 polynomial's coefficients packed into integers with the following algorithm:
861 [[!inline pagenames="gf_reference/pack_poly.py" raw="yes"]]
864 ## Carry-less Multiply Instructions
867 see <https://en.wikipedia.org/wiki/CLMUL_instruction_set> and
868 <https://www.felixcloutier.com/x86/pclmulqdq> and
869 <https://en.m.wikipedia.org/wiki/Carry-less_product>
871 They are worth adding as their own non-overwrite operations
872 (in the same pipeline).
874 ### `clmul` Carry-less Multiply
877 [[!inline pagenames="gf_reference/clmul.py" raw="yes"]]
880 ### `clmulh` Carry-less Multiply High
883 [[!inline pagenames="gf_reference/clmulh.py" raw="yes"]]
886 ### `clmulr` Carry-less Multiply (Reversed)
888 Useful for CRCs. Equivalent to bit-reversing the result of `clmul` on
892 [[!inline pagenames="gf_reference/clmulr.py" raw="yes"]]
895 ## `clmadd` Carry-less Multiply-Add
898 clmadd RT, RA, RB, RC
902 (RT) = clmul((RA), (RB)) ^ (RC)
905 ## `cltmadd` Twin Carry-less Multiply-Add (for FFTs)
907 Used in combination with SV FFT REMAP to perform a full Discrete Fourier
908 Transform of Polynomials over GF(2) in-place. Possible by having 3-in 2-out,
909 to avoid the need for a temp register. RS is written to as well as RT.
911 Note: Polynomials over GF(2) are a Ring rather than a Field, so, because the
912 definition of the Inverse Discrete Fourier Transform involves calculating a
913 multiplicative inverse, which may not exist in every Ring, therefore the
914 Inverse Discrete Fourier Transform may not exist. (AFAICT the number of inputs
915 to the IDFT must be odd for the IDFT to be defined for Polynomials over GF(2).
916 TODO: check with someone who knows for sure if that's correct.)
919 cltmadd RT, RA, RB, RC
922 TODO: add link to explanation for where `RS` comes from.
927 # read all inputs before writing to any outputs in case
928 # an input overlaps with an output register.
929 (RT) = clmul(a, (RB)) ^ c
933 ## `cldivrem` Carry-less Division and Remainder
935 `cldivrem` isn't an actual instruction, but is just used in the pseudo-code
936 for other instructions.
939 [[!inline pagenames="gf_reference/cldivrem.py" raw="yes"]]
942 ## `cldiv` Carry-less Division
951 q, r = cldivrem(n, d, width=XLEN)
955 ## `clrem` Carry-less Remainder
964 q, r = cldivrem(n, d, width=XLEN)
968 # Instructions for Binary Galois Fields `GF(2^m)`
972 * <https://courses.csail.mit.edu/6.857/2016/files/ffield.py>
973 * <https://engineering.purdue.edu/kak/compsec/NewLectures/Lecture7.pdf>
974 * <https://foss.heptapod.net/math/libgf2/-/blob/branch/default/src/libgf2/gf2.py>
976 Binary Galois Field addition/subtraction is simply XOR, so a `gfbadd`
977 instruction is not provided since the `xor[i]` instruction can be used instead.
979 ## `GFBREDPOLY` SPR -- Reducing Polynomial
981 In order to save registers and to make operations orthogonal with standard
982 arithmetic, the reducing polynomial is stored in a dedicated SPR `GFBREDPOLY`.
983 This also allows hardware to pre-compute useful parameters (such as the
984 degree, or look-up tables) based on the reducing polynomial, and store them
985 alongside the SPR in hidden registers, only recomputing them whenever the SPR
986 is written to, rather than having to recompute those values for every
989 Because Galois Fields require the reducing polynomial to be an irreducible
990 polynomial, that guarantees that any polynomial of `degree > 1` must have
991 the LSB set, since otherwise it would be divisible by the polynomial `x`,
992 making it reducible, making whatever we're working on no longer a Field.
993 Therefore, we can reuse the LSB to indicate `degree == XLEN`.
996 [[!inline pagenames="gf_reference/decode_reducing_polynomial.py" raw="yes"]]
999 ## `gfbredpoly` -- Set the Reducing Polynomial SPR `GFBREDPOLY`
1001 unless this is an immediate op, `mtspr` is completely sufficient.
1004 [[!inline pagenames="gf_reference/gfbredpoly.py" raw="yes"]]
1007 ## `gfbmul` -- Binary Galois Field `GF(2^m)` Multiplication
1014 [[!inline pagenames="gf_reference/gfbmul.py" raw="yes"]]
1017 ## `gfbmadd` -- Binary Galois Field `GF(2^m)` Multiply-Add
1020 gfbmadd RT, RA, RB, RC
1024 [[!inline pagenames="gf_reference/gfbmadd.py" raw="yes"]]
1027 ## `gfbtmadd` -- Binary Galois Field `GF(2^m)` Twin Multiply-Add (for FFT)
1029 Used in combination with SV FFT REMAP to perform a full `GF(2^m)` Discrete
1030 Fourier Transform in-place. Possible by having 3-in 2-out, to avoid the need
1031 for a temp register. RS is written to as well as RT.
1034 gfbtmadd RT, RA, RB, RC
1037 TODO: add link to explanation for where `RS` comes from.
1042 # read all inputs before writing to any outputs in case
1043 # an input overlaps with an output register.
1044 (RT) = gfbmadd(a, (RB), c)
1045 # use gfbmadd again since it reduces the result
1046 (RS) = gfbmadd(a, 1, c) # "a * 1 + c"
1049 ## `gfbinv` -- Binary Galois Field `GF(2^m)` Inverse
1056 [[!inline pagenames="gf_reference/gfbinv.py" raw="yes"]]
1059 # Instructions for Prime Galois Fields `GF(p)`
1061 ## `GFPRIME` SPR -- Prime Modulus For `gfp*` Instructions
1063 ## `gfpadd` Prime Galois Field `GF(p)` Addition
1070 [[!inline pagenames="gf_reference/gfpadd.py" raw="yes"]]
1073 the addition happens on infinite-precision integers
1075 ## `gfpsub` Prime Galois Field `GF(p)` Subtraction
1082 [[!inline pagenames="gf_reference/gfpsub.py" raw="yes"]]
1085 the subtraction happens on infinite-precision integers
1087 ## `gfpmul` Prime Galois Field `GF(p)` Multiplication
1094 [[!inline pagenames="gf_reference/gfpmul.py" raw="yes"]]
1097 the multiplication happens on infinite-precision integers
1099 ## `gfpinv` Prime Galois Field `GF(p)` Invert
1105 Some potential hardware implementations are found in:
1106 <https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.90.5233&rep=rep1&type=pdf>
1109 [[!inline pagenames="gf_reference/gfpinv.py" raw="yes"]]
1112 ## `gfpmadd` Prime Galois Field `GF(p)` Multiply-Add
1115 gfpmadd RT, RA, RB, RC
1119 [[!inline pagenames="gf_reference/gfpmadd.py" raw="yes"]]
1122 the multiplication and addition happens on infinite-precision integers
1124 ## `gfpmsub` Prime Galois Field `GF(p)` Multiply-Subtract
1127 gfpmsub RT, RA, RB, RC
1131 [[!inline pagenames="gf_reference/gfpmsub.py" raw="yes"]]
1134 the multiplication and subtraction happens on infinite-precision integers
1136 ## `gfpmsubr` Prime Galois Field `GF(p)` Multiply-Subtract-Reversed
1139 gfpmsubr RT, RA, RB, RC
1143 [[!inline pagenames="gf_reference/gfpmsubr.py" raw="yes"]]
1146 the multiplication and subtraction happens on infinite-precision integers
1148 ## `gfpmaddsubr` Prime Galois Field `GF(p)` Multiply-Add and Multiply-Sub-Reversed (for FFT)
1150 Used in combination with SV FFT REMAP to perform
1151 a full Number-Theoretic-Transform in-place. Possible by having 3-in 2-out,
1152 to avoid the need for a temp register. RS is written
1156 gfpmaddsubr RT, RA, RB, RC
1159 TODO: add link to explanation for where `RS` comes from.
1165 # read all inputs before writing to any outputs in case
1166 # an input overlaps with an output register.
1167 (RT) = gfpmadd(factor1, factor2, term)
1168 (RS) = gfpmsubr(factor1, factor2, term)
1171 # Already in POWER ISA or subsumed
1173 Lists operations either included as part of
1174 other bitmanip operations, or are already in
1179 based on RV bitmanip, covered by ternlog bitops
1182 uint_xlen_t cmix(uint_xlen_t RA, uint_xlen_t RB, uint_xlen_t RC) {
1183 return (RA & RB) | (RC & ~RB);
1187 ## count leading/trailing zeros with mask
1193 do i = 0 to 63 if((RB)i=1) then do
1194 if((RS)i=1) then break end end count ← count + 1
1200 pdepd VRT,VRA,VRB, identical to RV bitmamip bdep, found already in v3.1 p106
1203 if VSR[VRB+32].dword[i].bit[63-m]=1 then do
1204 result = VSR[VRA+32].dword[i].bit[63-k]
1205 VSR[VRT+32].dword[i].bit[63-m] = result
1211 uint_xlen_t bdep(uint_xlen_t RA, uint_xlen_t RB)
1214 for (int i = 0, j = 0; i < XLEN; i++)
1215 if ((RB >> i) & 1) {
1217 r |= uint_xlen_t(1) << i;
1227 other way round: identical to RV bext: pextd, found in v3.1 p196
1230 uint_xlen_t bext(uint_xlen_t RA, uint_xlen_t RB)
1233 for (int i = 0, j = 0; i < XLEN; i++)
1234 if ((RB >> i) & 1) {
1236 r |= uint_xlen_t(1) << j;
1245 found in v3.1 p106 so not to be added here
1255 if((RB)63-i==1) then do
1256 result63-ptr1 = (RS)63-i
1262 ## bit to byte permute
1264 similar to matrix permute in RV bitmanip, which has XOR and OR variants,
1265 these perform a transpose (bmatflip).
1266 TODO this looks VSX is there a scalar variant
1271 b = VSR[VRB+32].dword[i].byte[k].bit[j]
1272 VSR[VRT+32].dword[i].byte[j].bit[k] = b
1276 see [[bitmanip/appendix]]