7 * ternlogi <https://bugs.libre-soc.org/show_bug.cgi?id=745>
8 * grev <https://bugs.libre-soc.org/show_bug.cgi?id=755>
9 * GF2^M <https://bugs.libre-soc.org/show_bug.cgi?id=782>
16 pseudocode: [[openpower/isa/bitmanip]]
18 this extension amalgamates bitmanipulation primitives from many sources,
19 including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX.
20 Also included are DSP/Multimedia operations suitable for Audio/Video.
21 Vectorisation and SIMD are removed: these are straight scalar (element)
22 operations making them suitable for embedded applications. Vectorisation
23 Context is provided by [[openpower/sv]].
25 When combined with SV, scalar variants of bitmanip operations found in
26 VSX are added so that the Packed SIMD aspects of VSX may be retired as
27 "legacy" in the far future (10 to 20 years). Also, VSX is hundreds of
28 opcodes, requires 128 bit pathways, and is wholly unsuited to low power
29 or embedded scenarios.
31 ternlogv is experimental and is the only operation that may be considered
32 a "Packed SIMD". It is added as a variant of the already well-justified
33 ternlog operation (done in AVX512 as an immediate only) "because it
34 looks fun". As it is based on the LUT4 concept it will allow accelerated
35 emulation of FPGAs. Other vendors of ISAs are buying FPGA companies to
36 achieve similar objectives.
38 general-purpose Galois Field 2^M operations are added so as to avoid
39 huge custom opcode proliferation across many areas of Computer Science.
40 however for convenience and also to avoid setup costs, some of the more
41 common operations (clmul, crc32) are also added. The expectation is
42 that these operations would all be covered by the same pipeline.
44 note that there are brownfield spaces below that could incorporate
45 some of the set-before-first and other scalar operations listed in
47 [[sv/vector_ops]], [[sv/int_fp_mv]] and the [[sv/av_opcodes]] as well as
48 [[sv/setvl]], [[sv/svstep]], [[sv/remap]]
52 * <https://en.wikiversity.org/wiki/Reed%E2%80%93Solomon_codes_for_coders>
53 * <https://maths-people.anu.edu.au/~brent/pd/rpb232tr.pdf>
55 [[!inline quick="yes" raw="yes" pages="openpower/sv/bmask.py"]]
58 # binary and ternary bitops
60 Similar to FPGA LUTs: for two (binary) or three (ternary) inputs take
61 bits from each input, concatenate them and perform a lookup into a
62 table using an 8-8-bit immediate (for the ternary instructions), or in
63 another register (4-bit for the binary instructions). The binary lookup
64 instructions have CR Field lookup variants due to CR Fields being 4 bit.
67 [vpternlogd/vpternlogq](https://www.felixcloutier.com/x86/vpternlogd:vpternlogq)
72 | 0.5|6.10|11.15|16.20| 21..28|29.30|31|
73 | -- | -- | --- | --- | ----- | --- |--|
74 | NN | RT | RA | RB | im0-7 | 00 |Rc|
77 idx = c << 2 | b << 1 | a
78 return imm[idx] # idx by LSB0 order
81 RT[i] = lut3(imm, RB[i], RA[i], RT[i])
85 Binary lookup is a dynamic LUT2 version of ternlogi. Firstly, the
86 lookup table is 4 bits wide not 8 bits, and secondly the lookup
87 table comes from a register not an immediate.
89 | 0.5|6.10|11.15|16.20| 21..25|26..31 | Form |
90 | -- | -- | --- | --- | ----- |--------|---------|
91 | NN | RT | RA | RB | RC |nh 00001| VA-Form |
92 | NN | RT | RA | RB | /BFA/ |0 01001| VA-Form |
94 For binlut, the 4-bit LUT may be selected from either the high nibble
95 or the low nibble of the first byte of RC:
99 return imm[idx] # idx by LSB0 order
101 imm = (RC>>(nh*4))&0b1111
103 RT[i] = lut2(imm, RB[i], RA[i])
105 For bincrlut, `BFA` selects the 4-bit CR Field as the LUT2:
108 RT[i] = lut2(CRs{BFA}, RB[i], RA[i])
110 When Vectorised with SVP64, as usual both source and destination may be
113 *Programmer's note: a dynamic ternary lookup may be synthesised from
114 a pair of `binlut` instructions followed by a `ternlogi` to select which
115 to merge. Use `nh` to select which nibble to use as the lookup table
116 from the RC source register (`nh=1` nibble high), i.e. keeping
117 an 8-bit LUT3 in RC, the first `binlut` instruction may set nh=0 and
122 another mode selection would be CRs not Ints.
124 | 0.5|6.8 | 9.11|12.14|15.17|18.20|21.28 | 29.30|31|
125 | -- | -- | --- | --- | --- |-----|----- | -----|--|
126 | NN | BT | BA | BB | BC |m0-2 | imm | 01 |m3|
130 a,b,c = CRs[BA][i], CRs[BB][i], CRs[BC][i])
131 if mask[i] CRs[BT][i] = lut3(imm, a, b, c)
133 This instruction is remarkably similar to the existing crops, `crand` etc.
134 which have been noted to be a 4-bit (binary) LUT. In effect `crternlogi`
135 is the ternary LUT version of crops, having an 8-bit LUT.
139 With ternary (LUT3) dynamic instructions being very costly,
140 and CR Fields being only 4 bit, a binary (LUT2) variant is better
142 | 0.5|6.8 | 9.11|12.14|15.17|18.21|22...30 |31|
143 | -- | -- | --- | --- | --- |-----| -------- |--|
144 | NN | BT | BA | BB | BC |m0-m3|000101110 |0 |
148 a,b = CRs[BA][i], CRs[BB][i])
149 if mask[i] CRs[BT][i] = lut2(CRs[BC], a, b)
151 When SVP64 Vectorised any of the 4 operands may be Scalar or
152 Vector, including `BC` meaning that multiple different dynamic
153 lookups may be performed with a single instruction.
155 *Programmer's note: just as with binlut and ternlogi, a pair
156 of crbinlog instructions followed by a merging crternlogi may
157 be deployed to synthesise dynamic ternary (LUT3) CR Field
164 required for the [[sv/av_opcodes]]
166 signed and unsigned min/max for integer. this is sort-of partly
167 synthesiseable in [[sv/svp64]] with pred-result as long as the dest reg
168 is one of the sources, but not both signed and unsigned. when the dest
169 is also one of the srces and the mv fails due to the CR bittest failing
170 this will only overwrite the dest where the src is greater (or less).
172 signed/unsigned min/max gives more flexibility.
176 * XO=0001001110, itype=0b00 min, unsigned
177 * XO=0101001110, itype=0b01 min, signed
178 * XO=0011001110, itype=0b10 max, unsigned
179 * XO=0111001110, itype=0b11 max, signed
183 uint_xlen_t mins(uint_xlen_t rs1, uint_xlen_t rs2)
184 { return (int_xlen_t)rs1 < (int_xlen_t)rs2 ? rs1 : rs2;
186 uint_xlen_t maxs(uint_xlen_t rs1, uint_xlen_t rs2)
187 { return (int_xlen_t)rs1 > (int_xlen_t)rs2 ? rs1 : rs2;
189 uint_xlen_t minu(uint_xlen_t rs1, uint_xlen_t rs2)
190 { return rs1 < rs2 ? rs1 : rs2;
192 uint_xlen_t maxu(uint_xlen_t rs1, uint_xlen_t rs2)
193 { return rs1 > rs2 ? rs1 : rs2;
199 required for the [[sv/av_opcodes]], these exist in Packed SIMD (VSX)
203 uint_xlen_t intavg(uint_xlen_t rs1, uint_xlen_t rs2) {
204 return (rs1 + rs2 + 1) >> 1:
210 required for the [[sv/av_opcodes]], these exist in Packed SIMD (VSX)
214 uint_xlen_t absdu(uint_xlen_t rs1, uint_xlen_t rs2) {
215 return (src1 > src2) ? (src1-src2) : (src2-src1)
221 required for the [[sv/av_opcodes]], these are needed for motion estimation.
222 both are overwrite on RS.
225 uint_xlen_t uintabsacc(uint_xlen_t rs, uint_xlen_t ra, uint_xlen_t rb) {
226 return rs + (src1 > src2) ? (src1-src2) : (src2-src1)
228 uint_xlen_t intabsacc(uint_xlen_t rs, int_xlen_t ra, int_xlen_t rb) {
229 return rs + (src1 > src2) ? (src1-src2) : (src2-src1)
233 For SVP64, the twin Elwidths allows e.g. a 16 bit accumulator for 8 bit
234 differences. Form is `RM-1P-3S1D` where RS-as-source has a separate
235 SVP64 designation from RS-as-dest. This gives a limited range of
236 non-overwrite capability.
240 Power ISA is missing LD/ST with shift, which is present in both ARM and x86.
241 Too complex to add more LD/ST, a compromise is to add shift-and-add.
242 Replaces a pair of explicit instructions in hot-loops.
245 uint_xlen_t shadd(uint_xlen_t rs1, uint_xlen_t rs2, uint8_t sh) {
246 return (rs1 << (sh+1)) + rs2;
249 uint_xlen_t shadduw(uint_xlen_t rs1, uint_xlen_t rs2, uint8_t sh) {
250 uint_xlen_t rs1z = rs1 & 0xFFFFFFFF;
251 return (rs1z << (sh+1)) + rs2;
257 based on RV bitmanip singlebit set, instruction format similar to shift
258 [[isa/fixedshift]]. bmext is actually covered already (shift-with-mask
259 rldicl but only immediate version). however bitmask-invert is not,
260 and set/clr are not covered, although they can use the same Shift ALU.
262 bmext (RB) version is not the same as rldicl because bmext is a right
263 shift by RC, where rldicl is a left rotate. for the immediate version
264 this does not matter, so a bmexti is not required. bmrev however there
265 is no direct equivalent and consequently a bmrevi is required.
267 bmset (register for mask amount) is particularly useful for creating
268 predicate masks where the length is a dynamic runtime quantity.
269 bmset(RA=0, RB=0, RC=mask) will produce a run of ones of length "mask"
270 in a single instruction without needing to initialise or depend on any
273 | 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name |
274 | -- | -- | --- | --- | --- | ------- |--| ----- |
275 | NN | RS | RA | RB | RC | mode 010 |Rc| bm\* |
277 Immediate-variant is an overwrite form:
279 | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name |
280 | -- | -- | --- | --- | -- | ----- | -------- |--| ---- |
281 | NN | RS | RB | sh | SH | itype | 1000 110 |Rc| bm\*i |
287 mask_a = ((1 << x) - 1) & ((1 << 64) - 1)
288 mask_b = ((1 << y) - 1) & ((1 << 64) - 1)
293 mask_a = ((1 << x) - 1) & ((1 << 64) - 1)
294 mask_b = (~((1 << y) - 1)) & ((1 << 64) - 1)
295 return mask_a ^ mask_b
298 uint_xlen_t bmset(RS, RB, sh)
300 int shamt = RB & (XLEN - 1);
302 return RS | (mask << shamt);
305 uint_xlen_t bmclr(RS, RB, sh)
307 int shamt = RB & (XLEN - 1);
309 return RS & ~(mask << shamt);
312 uint_xlen_t bminv(RS, RB, sh)
314 int shamt = RB & (XLEN - 1);
316 return RS ^ (mask << shamt);
319 uint_xlen_t bmext(RS, RB, sh)
321 int shamt = RB & (XLEN - 1);
323 return mask & (RS >> shamt);
327 bitmask extract with reverse. can be done by bit-order-inverting all
328 of RB and getting bits of RB from the opposite end.
330 when RA is zero, no shift occurs. this makes bmextrev useful for
331 simply reversing all bits of a register.
335 rev[0:msb] = rb[msb:0];
338 uint_xlen_t bmrevi(RA, RB, sh)
341 if (RA != 0) shamt = (GPR(RA) & (XLEN - 1));
342 shamt = (XLEN-1)-shamt; # shift other end
343 brb = bitreverse(GPR(RB)) # swap LSB-MSB
345 return mask & (brb >> shamt);
348 uint_xlen_t bmrev(RA, RB, RC) {
349 return bmrevi(RA, RB, GPR(RC) & 0b111111);
353 | 0.5|6.10|11.15|16.20|21.26| 27..30 |31| name | Form |
354 | -- | -- | --- | --- | --- | ------- |--| ------ | -------- |
355 | NN | RT | RA | RB | sh | 1111 |Rc| bmrevi | MDS-Form |
357 | 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name | Form |
358 | -- | -- | --- | --- | --- | ------- |--| ------ | -------- |
359 | NN | RT | RA | RB | RC | 11110 |Rc| bmrev | VA2-Form |
361 # grevlut <a name="grevlut"> </a>
363 ([3x lower latency alternative](grev_gorc_design/) which is
364 not equivalent and has limited constant-generation capability)
366 generalised reverse combined with a pair of LUT2s and allowing
367 a constant `0b0101...0101` when RA=0, and an option to invert
368 (including when RA=0, giving a constant 0b1010...1010 as the
369 initial value) provides a wide range of instructions
370 and a means to set hundreds of regular 64 bit patterns with one
371 single 32 bit instruction.
373 the two LUT2s are applied left-half (when not swapping)
374 and right-half (when swapping) so as to allow a wider
377 <img src="/openpower/sv/grevlut2x2.jpg" width=700 />
379 * A value of `0b11001010` for the immediate provides
380 the functionality of a standard "grev".
381 * `0b11101110` provides gorc
383 grevlut should be arranged so as to produce the constants
384 needed to put into bext (bitextract) so as in turn to
385 be able to emulate x86 pmovmask instructions
386 <https://www.felixcloutier.com/x86/pmovmskb>.
387 This only requires 2 instructions (grevlut, bext).
389 Note that if the mask is required to be placed
390 directly into CR Fields (for use as CR Predicate
391 masks rather than a integer mask) then sv.cmpi or sv.ori
392 may be used instead, bearing in mind that sv.ori
393 is a 64-bit instruction, and `VL` must have been
394 set to the required length:
396 sv.ori./elwid=8 r10.v, r10.v, 0
398 The following settings provide the required mask constants:
400 | RA=0 | RB | imm | iv | result |
401 | ------- | ------- | ---------- | -- | ---------- |
402 | 0x555.. | 0b10 | 0b01101100 | 0 | 0x111111... |
403 | 0x555.. | 0b110 | 0b01101100 | 0 | 0x010101... |
404 | 0x555.. | 0b1110 | 0b01101100 | 0 | 0x00010001... |
405 | 0x555.. | 0b10 | 0b11000110 | 1 | 0x88888... |
406 | 0x555.. | 0b110 | 0b11000110 | 1 | 0x808080... |
407 | 0x555.. | 0b1110 | 0b11000110 | 1 | 0x80008000... |
409 Better diagram showing the correct ordering of shamt (RB). A LUT2
410 is applied to all locations marked in red using the first 4
411 bits of the immediate, and a separate LUT2 applied to all
412 locations in green using the upper 4 bits of the immediate.
414 <img src="/openpower/sv/grevlut.png" width=700 />
416 demo code [[openpower/sv/grevlut.py]]
421 return imm[idx] # idx by LSB0 order
423 dorow(imm8, step_i, chunksize, us32b):
424 for j in 0 to 31 if is32b else 63:
425 if (j&chunk_size) == 0
429 step_o[j] = lut2(imm, step_i[j], step_i[j ^ chunk_size])
432 uint64_t grevlut(uint64_t RA, uint64_t RB, uint8 imm, bool iv, bool is32b)
434 uint64_t x = 0x5555_5555_5555_5555;
435 if (RA != 0) x = GPR(RA);
437 int shamt = RB & 31 if is32b else 63
438 for i in 0 to (6-is32b)
440 if (shamt & step) x = dorow(imm, x, step, is32b)
445 A variant may specify different LUT-pairs per row,
446 using one byte of RB for each. If it is desired that
447 a particular row-crossover shall not be applied it is
448 a simple matter to set the appropriate LUT-pair in RB
449 to effect an identity transform for that row (`0b11001010`).
452 uint64_t grevlutr(uint64_t RA, uint64_t RB, bool iv, bool is32b)
454 uint64_t x = 0x5555_5555_5555_5555;
455 if (RA != 0) x = GPR(RA);
457 for i in 0 to (6-is32b)
459 imm = (RB>>(i*8))&0xff
460 x = dorow(imm, x, step, is32b)
466 | 0.5|6.10|11.15|16.20 |21..28 | 29.30|31| name | Form |
467 | -- | -- | --- | --- | ----- | -----|--| ------ | ----- |
468 | NN | RT | RA | s0-4 | im0-7 | 1 iv |s5| grevlogi | |
469 | NN | RT | RA | RB | im0-7 | 01 |0 | grevlog | |
470 | NN | RT | RA | RB | im0-7 | 01 |1 | grevlogw | |
474 based on RV bitmanip.
476 RA contains a vector of indices to select parts of RB to be
477 copied to RT. The immediate-variant allows up to an 8 bit
478 pattern (repeated) to be targetted at different parts of RT.
480 xperm shares some similarity with one of the uses of bmator
481 in that xperm indices are binary addressing where bitmator
482 may be considered to be unary addressing.
485 uint_xlen_t xpermi(uint8_t imm8, uint_xlen_t RB, int sz_log2)
488 uint_xlen_t sz = 1LL << sz_log2;
489 uint_xlen_t mask = (1LL << sz) - 1;
490 uint_xlen_t RA = imm8 | imm8<<8 | ... | imm8<<56;
491 for (int i = 0; i < XLEN; i += sz) {
492 uint_xlen_t pos = ((RA >> i) & mask) << sz_log2;
494 r |= ((RB >> pos) & mask) << i;
498 uint_xlen_t xperm(uint_xlen_t RA, uint_xlen_t RB, int sz_log2)
501 uint_xlen_t sz = 1LL << sz_log2;
502 uint_xlen_t mask = (1LL << sz) - 1;
503 for (int i = 0; i < XLEN; i += sz) {
504 uint_xlen_t pos = ((RA >> i) & mask) << sz_log2;
506 r |= ((RB >> pos) & mask) << i;
510 uint_xlen_t xperm_n (uint_xlen_t RA, uint_xlen_t RB)
511 { return xperm(RA, RB, 2); }
512 uint_xlen_t xperm_b (uint_xlen_t RA, uint_xlen_t RB)
513 { return xperm(RA, RB, 3); }
514 uint_xlen_t xperm_h (uint_xlen_t RA, uint_xlen_t RB)
515 { return xperm(RA, RB, 4); }
516 uint_xlen_t xperm_w (uint_xlen_t RA, uint_xlen_t RB)
517 { return xperm(RA, RB, 5); }
522 bmatflip and bmatxor is found in the Cray XMT, and in x86 is known
523 as GF2P8AFFINEQB. uses:
525 * <https://gist.github.com/animetosho/d3ca95da2131b5813e16b5bb1b137ca0>
526 * SM4, Reed Solomon, RAID6
527 <https://stackoverflow.com/questions/59124720/what-are-the-avx-512-galois-field-related-instructions-for>
528 * Vector bit-reverse <https://reviews.llvm.org/D91515?id=305411>
529 * Affine Inverse <https://github.com/HJLebbink/asm-dude/wiki/GF2P8AFFINEINVQB>
531 | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name | Form |
532 | -- | -- | --- | --- | -- | ----- | -------- |--| ---- | ------- |
533 | NN | RS | RA |im04 | im5| 1 1 | im67 00 110 |Rc| bmatxori | TODO |
537 uint64_t bmatflip(uint64_t RA)
546 uint64_t bmatxori(uint64_t RS, uint64_t RA, uint8_t imm) {
548 uint64_t RAt = bmatflip(RA);
549 uint8_t u[8]; // rows of RS
550 uint8_t v[8]; // cols of RA
551 for (int i = 0; i < 8; i++) {
556 for (int i = 0; i < 64; i++) {
557 bit = (imm >> (i%8)) & 1;
558 bit ^= pcnt(u[i / 8] & v[i % 8]) & 1;
564 uint64_t bmatxor(uint64_t RA, uint64_t RB) {
565 return bmatxori(RA, RB, 0xff)
568 uint64_t bmator(uint64_t RA, uint64_t RB) {
570 uint64_t RBt = bmatflip(RB);
571 uint8_t u[8]; // rows of RA
572 uint8_t v[8]; // cols of RB
573 for (int i = 0; i < 8; i++) {
578 for (int i = 0; i < 64; i++) {
579 if ((u[i / 8] & v[i % 8]) != 0)
585 uint64_t bmatand(uint64_t RA, uint64_t RB) {
587 uint64_t RBt = bmatflip(RB);
588 uint8_t u[8]; // rows of RA
589 uint8_t v[8]; // cols of RB
590 for (int i = 0; i < 8; i++) {
595 for (int i = 0; i < 64; i++) {
596 if ((u[i / 8] & v[i % 8]) == 0xff)
603 # Introduction to Carry-less and GF arithmetic
605 * obligatory xkcd <https://xkcd.com/2595/>
607 There are three completely separate types of Galois-Field-based arithmetic
608 that we implement which are not well explained even in introductory
609 literature. A slightly oversimplified explanation is followed by more
610 accurate descriptions:
612 * `GF(2)` carry-less binary arithmetic. this is not actually a Galois Field,
613 but is accidentally referred to as GF(2) - see below as to why.
614 * `GF(p)` modulo arithmetic with a Prime number, these are "proper"
616 * `GF(2^N)` carry-less binary arithmetic with two limits: modulo a power-of-2
617 (2^N) and a second "reducing" polynomial (similar to a prime number), these
618 are said to be GF(2^N) arithmetic.
620 further detailed and more precise explanations are provided below
622 * **Polynomials with coefficients in `GF(2)`**
623 (aka. Carry-less arithmetic -- the `cl*` instructions).
624 This isn't actually a Galois Field, but its coefficients are. This is
625 basically binary integer addition, subtraction, and multiplication like
626 usual, except that carries aren't propagated at all, effectively turning
627 both addition and subtraction into the bitwise xor operation. Division and
628 remainder are defined to match how addition and multiplication works.
629 * **Galois Fields with a prime size**
630 (aka. `GF(p)` or Prime Galois Fields -- the `gfp*` instructions).
631 This is basically just the integers mod `p`.
632 * **Galois Fields with a power-of-a-prime size**
633 (aka. `GF(p^n)` or `GF(q)` where `q == p^n` for prime `p` and
635 We only implement these for `p == 2`, called Binary Galois Fields
636 (`GF(2^n)` -- the `gfb*` instructions).
637 For any prime `p`, `GF(p^n)` is implemented as polynomials with
638 coefficients in `GF(p)` and degree `< n`, where the polynomials are the
639 remainders of dividing by a specificly chosen polynomial in `GF(p)` called
640 the Reducing Polynomial (we will denote that by `red_poly`). The Reducing
641 Polynomial must be an irreducable polynomial (like primes, but for
642 polynomials), as well as have degree `n`. All `GF(p^n)` for the same `p`
643 and `n` are isomorphic to each other -- the choice of `red_poly` doesn't
644 affect `GF(p^n)`'s mathematical shape, all that changes is the specific
645 polynomials used to implement `GF(p^n)`.
647 Many implementations and much of the literature do not make a clear
648 distinction between these three categories, which makes it confusing
649 to understand what their purpose and value is.
651 * carry-less multiply is extremely common and is used for the ubiquitous
652 CRC32 algorithm. [TODO add many others, helps justify to ISA WG]
653 * GF(2^N) forms the basis of Rijndael (the current AES standard) and
654 has significant uses throughout cryptography
655 * GF(p) is the basis again of a significant quantity of algorithms
656 (TODO, list them, jacob knows what they are), even though the
657 modulo is limited to be below 64-bit (size of a scalar int)
659 # Instructions for Carry-less Operations
661 aka. Polynomials with coefficients in `GF(2)`
663 Carry-less addition/subtraction is simply XOR, so a `cladd`
664 instruction is not provided since the `xor[i]` instruction can be used instead.
666 These are operations on polynomials with coefficients in `GF(2)`, with the
667 polynomial's coefficients packed into integers with the following algorithm:
670 [[!inline pagenames="gf_reference/pack_poly.py" raw="yes"]]
673 ## Carry-less Multiply Instructions
676 see <https://en.wikipedia.org/wiki/CLMUL_instruction_set> and
677 <https://www.felixcloutier.com/x86/pclmulqdq> and
678 <https://en.m.wikipedia.org/wiki/Carry-less_product>
680 They are worth adding as their own non-overwrite operations
681 (in the same pipeline).
683 ### `clmul` Carry-less Multiply
686 [[!inline pagenames="gf_reference/clmul.py" raw="yes"]]
689 ### `clmulh` Carry-less Multiply High
692 [[!inline pagenames="gf_reference/clmulh.py" raw="yes"]]
695 ### `clmulr` Carry-less Multiply (Reversed)
697 Useful for CRCs. Equivalent to bit-reversing the result of `clmul` on
701 [[!inline pagenames="gf_reference/clmulr.py" raw="yes"]]
704 ## `clmadd` Carry-less Multiply-Add
707 clmadd RT, RA, RB, RC
711 (RT) = clmul((RA), (RB)) ^ (RC)
714 ## `cltmadd` Twin Carry-less Multiply-Add (for FFTs)
716 Used in combination with SV FFT REMAP to perform a full Discrete Fourier
717 Transform of Polynomials over GF(2) in-place. Possible by having 3-in 2-out,
718 to avoid the need for a temp register. RS is written to as well as RT.
720 Note: Polynomials over GF(2) are a Ring rather than a Field, so, because the
721 definition of the Inverse Discrete Fourier Transform involves calculating a
722 multiplicative inverse, which may not exist in every Ring, therefore the
723 Inverse Discrete Fourier Transform may not exist. (AFAICT the number of inputs
724 to the IDFT must be odd for the IDFT to be defined for Polynomials over GF(2).
725 TODO: check with someone who knows for sure if that's correct.)
728 cltmadd RT, RA, RB, RC
731 TODO: add link to explanation for where `RS` comes from.
736 # read all inputs before writing to any outputs in case
737 # an input overlaps with an output register.
738 (RT) = clmul(a, (RB)) ^ c
742 ## `cldivrem` Carry-less Division and Remainder
744 `cldivrem` isn't an actual instruction, but is just used in the pseudo-code
745 for other instructions.
748 [[!inline pagenames="gf_reference/cldivrem.py" raw="yes"]]
751 ## `cldiv` Carry-less Division
760 q, r = cldivrem(n, d, width=XLEN)
764 ## `clrem` Carry-less Remainder
773 q, r = cldivrem(n, d, width=XLEN)
777 # Instructions for Binary Galois Fields `GF(2^m)`
781 * <https://courses.csail.mit.edu/6.857/2016/files/ffield.py>
782 * <https://engineering.purdue.edu/kak/compsec/NewLectures/Lecture7.pdf>
783 * <https://foss.heptapod.net/math/libgf2/-/blob/branch/default/src/libgf2/gf2.py>
785 Binary Galois Field addition/subtraction is simply XOR, so a `gfbadd`
786 instruction is not provided since the `xor[i]` instruction can be used instead.
788 ## `GFBREDPOLY` SPR -- Reducing Polynomial
790 In order to save registers and to make operations orthogonal with standard
791 arithmetic, the reducing polynomial is stored in a dedicated SPR `GFBREDPOLY`.
792 This also allows hardware to pre-compute useful parameters (such as the
793 degree, or look-up tables) based on the reducing polynomial, and store them
794 alongside the SPR in hidden registers, only recomputing them whenever the SPR
795 is written to, rather than having to recompute those values for every
798 Because Galois Fields require the reducing polynomial to be an irreducible
799 polynomial, that guarantees that any polynomial of `degree > 1` must have
800 the LSB set, since otherwise it would be divisible by the polynomial `x`,
801 making it reducible, making whatever we're working on no longer a Field.
802 Therefore, we can reuse the LSB to indicate `degree == XLEN`.
805 [[!inline pagenames="gf_reference/decode_reducing_polynomial.py" raw="yes"]]
808 ## `gfbredpoly` -- Set the Reducing Polynomial SPR `GFBREDPOLY`
810 unless this is an immediate op, `mtspr` is completely sufficient.
813 [[!inline pagenames="gf_reference/gfbredpoly.py" raw="yes"]]
816 ## `gfbmul` -- Binary Galois Field `GF(2^m)` Multiplication
823 [[!inline pagenames="gf_reference/gfbmul.py" raw="yes"]]
826 ## `gfbmadd` -- Binary Galois Field `GF(2^m)` Multiply-Add
829 gfbmadd RT, RA, RB, RC
833 [[!inline pagenames="gf_reference/gfbmadd.py" raw="yes"]]
836 ## `gfbtmadd` -- Binary Galois Field `GF(2^m)` Twin Multiply-Add (for FFT)
838 Used in combination with SV FFT REMAP to perform a full `GF(2^m)` Discrete
839 Fourier Transform in-place. Possible by having 3-in 2-out, to avoid the need
840 for a temp register. RS is written to as well as RT.
843 gfbtmadd RT, RA, RB, RC
846 TODO: add link to explanation for where `RS` comes from.
851 # read all inputs before writing to any outputs in case
852 # an input overlaps with an output register.
853 (RT) = gfbmadd(a, (RB), c)
854 # use gfbmadd again since it reduces the result
855 (RS) = gfbmadd(a, 1, c) # "a * 1 + c"
858 ## `gfbinv` -- Binary Galois Field `GF(2^m)` Inverse
865 [[!inline pagenames="gf_reference/gfbinv.py" raw="yes"]]
868 # Instructions for Prime Galois Fields `GF(p)`
870 ## `GFPRIME` SPR -- Prime Modulus For `gfp*` Instructions
872 ## `gfpadd` Prime Galois Field `GF(p)` Addition
879 [[!inline pagenames="gf_reference/gfpadd.py" raw="yes"]]
882 the addition happens on infinite-precision integers
884 ## `gfpsub` Prime Galois Field `GF(p)` Subtraction
891 [[!inline pagenames="gf_reference/gfpsub.py" raw="yes"]]
894 the subtraction happens on infinite-precision integers
896 ## `gfpmul` Prime Galois Field `GF(p)` Multiplication
903 [[!inline pagenames="gf_reference/gfpmul.py" raw="yes"]]
906 the multiplication happens on infinite-precision integers
908 ## `gfpinv` Prime Galois Field `GF(p)` Invert
914 Some potential hardware implementations are found in:
915 <https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.90.5233&rep=rep1&type=pdf>
918 [[!inline pagenames="gf_reference/gfpinv.py" raw="yes"]]
921 ## `gfpmadd` Prime Galois Field `GF(p)` Multiply-Add
924 gfpmadd RT, RA, RB, RC
928 [[!inline pagenames="gf_reference/gfpmadd.py" raw="yes"]]
931 the multiplication and addition happens on infinite-precision integers
933 ## `gfpmsub` Prime Galois Field `GF(p)` Multiply-Subtract
936 gfpmsub RT, RA, RB, RC
940 [[!inline pagenames="gf_reference/gfpmsub.py" raw="yes"]]
943 the multiplication and subtraction happens on infinite-precision integers
945 ## `gfpmsubr` Prime Galois Field `GF(p)` Multiply-Subtract-Reversed
948 gfpmsubr RT, RA, RB, RC
952 [[!inline pagenames="gf_reference/gfpmsubr.py" raw="yes"]]
955 the multiplication and subtraction happens on infinite-precision integers
957 ## `gfpmaddsubr` Prime Galois Field `GF(p)` Multiply-Add and Multiply-Sub-Reversed (for FFT)
959 Used in combination with SV FFT REMAP to perform
960 a full Number-Theoretic-Transform in-place. Possible by having 3-in 2-out,
961 to avoid the need for a temp register. RS is written
965 gfpmaddsubr RT, RA, RB, RC
968 TODO: add link to explanation for where `RS` comes from.
974 # read all inputs before writing to any outputs in case
975 # an input overlaps with an output register.
976 (RT) = gfpmadd(factor1, factor2, term)
977 (RS) = gfpmsubr(factor1, factor2, term)
980 # Already in POWER ISA or subsumed
982 Lists operations either included as part of
983 other bitmanip operations, or are already in
988 based on RV bitmanip, covered by ternlog bitops
991 uint_xlen_t cmix(uint_xlen_t RA, uint_xlen_t RB, uint_xlen_t RC) {
992 return (RA & RB) | (RC & ~RB);
996 ## count leading/trailing zeros with mask
1002 do i = 0 to 63 if((RB)i=1) then do
1003 if((RS)i=1) then break end end count ← count + 1
1009 pdepd VRT,VRA,VRB, identical to RV bitmamip bdep, found already in v3.1 p106
1012 if VSR[VRB+32].dword[i].bit[63-m]=1 then do
1013 result = VSR[VRA+32].dword[i].bit[63-k]
1014 VSR[VRT+32].dword[i].bit[63-m] = result
1020 uint_xlen_t bdep(uint_xlen_t RA, uint_xlen_t RB)
1023 for (int i = 0, j = 0; i < XLEN; i++)
1024 if ((RB >> i) & 1) {
1026 r |= uint_xlen_t(1) << i;
1036 other way round: identical to RV bext: pextd, found in v3.1 p196
1039 uint_xlen_t bext(uint_xlen_t RA, uint_xlen_t RB)
1042 for (int i = 0, j = 0; i < XLEN; i++)
1043 if ((RB >> i) & 1) {
1045 r |= uint_xlen_t(1) << j;
1054 found in v3.1 p106 so not to be added here
1064 if((RB)63-i==1) then do
1065 result63-ptr1 = (RS)63-i
1071 ## bit to byte permute
1073 similar to matrix permute in RV bitmanip, which has XOR and OR variants,
1074 these perform a transpose (bmatflip).
1075 TODO this looks VSX is there a scalar variant
1080 b = VSR[VRB+32].dword[i].byte[k].bit[j]
1081 VSR[VRT+32].dword[i].byte[j].bit[k] = b
1085 superceded by grevlut
1087 based on RV bitmanip, this is also known as a butterfly network. however
1088 where a butterfly network allows setting of every crossbar setting in
1089 every row and every column, generalised-reverse (grev) only allows
1090 a per-row decision: every entry in the same row must either switch or
1093 <img src="https://upload.wikimedia.org/wikipedia/commons/thumb/8/8c/Butterfly_Network.jpg/474px-Butterfly_Network.jpg" />
1096 uint64_t grev64(uint64_t RA, uint64_t RB)
1099 int shamt = RB & 63;
1100 if (shamt & 1) x = ((x & 0x5555555555555555LL) << 1) |
1101 ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
1102 if (shamt & 2) x = ((x & 0x3333333333333333LL) << 2) |
1103 ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
1104 if (shamt & 4) x = ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
1105 ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
1106 if (shamt & 8) x = ((x & 0x00FF00FF00FF00FFLL) << 8) |
1107 ((x & 0xFF00FF00FF00FF00LL) >> 8);
1108 if (shamt & 16) x = ((x & 0x0000FFFF0000FFFFLL) << 16) |
1109 ((x & 0xFFFF0000FFFF0000LL) >> 16);
1110 if (shamt & 32) x = ((x & 0x00000000FFFFFFFFLL) << 32) |
1111 ((x & 0xFFFFFFFF00000000LL) >> 32);
1119 based on RV bitmanip, gorc is superceded by grevlut
1122 uint32_t gorc32(uint32_t RA, uint32_t RB)
1125 int shamt = RB & 31;
1126 if (shamt & 1) x |= ((x & 0x55555555) << 1) | ((x & 0xAAAAAAAA) >> 1);
1127 if (shamt & 2) x |= ((x & 0x33333333) << 2) | ((x & 0xCCCCCCCC) >> 2);
1128 if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4) | ((x & 0xF0F0F0F0) >> 4);
1129 if (shamt & 8) x |= ((x & 0x00FF00FF) << 8) | ((x & 0xFF00FF00) >> 8);
1130 if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16);
1133 uint64_t gorc64(uint64_t RA, uint64_t RB)
1136 int shamt = RB & 63;
1137 if (shamt & 1) x |= ((x & 0x5555555555555555LL) << 1) |
1138 ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
1139 if (shamt & 2) x |= ((x & 0x3333333333333333LL) << 2) |
1140 ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
1141 if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
1142 ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
1143 if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL) << 8) |
1144 ((x & 0xFF00FF00FF00FF00LL) >> 8);
1145 if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL) << 16) |
1146 ((x & 0xFFFF0000FFFF0000LL) >> 16);
1147 if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL) << 32) |
1148 ((x & 0xFFFFFFFF00000000LL) >> 32);
1157 see [[bitmanip/appendix]]