openpower/sv/bitmanip.mdwn

   1 [[!tag standards]]
   2
   3 # bitmanipulation
   4
   5 **DRAFT STATUS**
   6
   7 this extension amalgamates bitmanipulation primitives from many sources, including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX.  Vectorisation and SIMD are removed: these are straight scalar (element) operations making them suitable for embedded applications.
   8 Vectorisation Context is provided by [[openpower/sv]].
   9
  10 When combined with SV, scalar variants of bitmanip operations found in VSX are added so that VSX may be retired as "legacy" in the far future (10 to 20 years).  Also, VSX is hundreds of opcodes, requires 128 bit pathways, and is wholly unsuited to low power or embedded scenarios.
  11
  12 ternaryv is experimental and is the only operation that may be considered a "Packed SIMD".  It is added as a variant of the already well-justified ternary operation (done in AVX512 as an immediate only) "because it looks fun". As it is based on the LUT4 concept it will allow accelerated emulation of FPGAs.  Other vendors of ISAs are buying FPGA companies to achieve similar objectives.
  13
  14 general-purpose Galois Field operations are added so as to avoid huge custom opcode proliferation across many areas of Computer Science.  however for convenience and also to avoid setup costs, some of the more common operations (clmul, crc32) are also added.  The expectation is that these operations would all be covered by the same pipeline.
  15
  16 note that there are brownfield spaces below that could incorporate some of the set-before-first and other scalar operations listed in [[sv/vector_ops]], and
  17 the [[sv/av_opcodes]] as well as [[sv/setvl]]
  18
  19 Useful resource:
  20
  21 * <https://en.wikiversity.org/wiki/Reed%E2%80%93Solomon_codes_for_coders>
  22 * <https://maths-people.anu.edu.au/~brent/pd/rpb232tr.pdf>
  23
  24 # summary
  25
  26 minor opcode allocation
  27
  28     |  28.30 |31| name      |
  29     | ------ |--| --------- |
  30     |   00   |Rc| ternaryi  |
  31     |  001   |Rc| ternary   |
  32     |  010   |Rc| bitmask   |
  33     |  011   |Rc| gf*       |
  34     |  101   |1 | ternaryv  |
  35     |  101   |0 | ternarycr |
  36     |  110   |Rc| 1/2-op    |
  37     |  111   |Rc| 3-op      |
  38
  39 1-op and variants
  40
  41 | dest | src1 | subop | op       |
  42 | ---- | ---- | ----- | -------- |
  43 | RT   | RA   | ..    | bmatflip |
  44
  45 2-op and variants
  46
  47 | dest | src1 | src2 | subop | op       |
  48 | ---- | ---- | ---- | ----- | -------- |
  49 | RT   | RA   | RB   | or    | bmatflip |
  50 | RT   | RA   | RB   | xor   | bmatflip |
  51 | RT   | RA   | RB   |       | grev  |
  52 | RT   | RA   | RB   |       | clmul*  |
  53 | RT   | RA   | RB   |       | gorc |
  54 | RT   | RA   | RB   | shuf  | shuffle |
  55 | RT   | RA   | RB   | unshuf| shuffle |
  56 | RT   | RA   | RB   | width | xperm  |
  57 | RT   | RA   | RB   | type | minmax |
  58 | RT   | RA   | RB   |      | av abs avgadd  |
  59 | RT   | RA   | RB   | type | vmask ops |
  60 | RT   | RA   | RB   |  |  |
  61
  62 3 ops
  63
  64 * bitmask set/extract
  65 * ternary bitops
  66 * GF
  67
  68 | 0.5|6.10|11.15|16.20|21..25 | 26....30 |31| name |
  69 | -- | -- | --- | --- | ----- | -------- |--| ------ |
  70 | NN | RT | RA  | RB  | RC    | mode 001 |Rc| ternary |
  71 | NN | RT | RA  | RB  | im0-4 | im5-7 00 |Rc| ternaryi |
  72 | NN | RS | RA  | RB  | RC    | 00  011  |Rc| gfmul |
  73 | NN | RS | RA  | RB  | RC    | 01  011  |Rc| gfadd |
  74 | NN | RT | RA  | RB  | deg   | 10  011  |Rc| gfinv |
  75 | NN | RS | RA  | RB  | deg   | 11  011  |Rc| gfmuli |
  76 | NN | RS | RA  | RB  | deg   | 11  111  |Rc| gfaddi |
  77
  78 | 0.5|6.10|11.15| 16.23 |24.27 | 28.30 |31| name |
  79 | -- | -- | --- | ----- | ---- | ----- |--| ------ |
  80 | NN | RT | RA  | imm   | mask | 101   |1 | ternaryv |
  81
  82 | 0.5|6.8 | 9.11|12.14|15|16.23|24.27 | 28.30|31| name |
  83 | -- | -- | --- | --- |- |-----|----- | -----|--| -------|
  84 | NN | BA | BB  | BC  |0 |imm  | mask | 101  |0 | ternarycr |
  85
  86 ops (note that av avg and abs as well as vec scalar mask
  87 are included here)
  88
  89 | 0.5|6.10|11.15|16.20| 21.22 | 23 | 24....30 |31| name |
  90 | -- | -- | --- | --- | ----- | -- | -------- |--| ---- |
  91 | NN | RA | RB  |     |       | 0  | 0000 110 |Rc| rsvd   |
  92 | NN | RA | RB  | RC  | itype | 1  | 0000 110 |Rc| xperm |
  93 | NN | RA | RB  | RC  | itype | 0  | 0100 110 |Rc| minmax |
  94 | NN | RA | RB  | RC  |   00  | 1  | 0100 110 |Rc| av avgadd |
  95 | NN | RA | RB  | RC  |   01  | 1  | 0100 110 |Rc| av abs |
  96 | NN | RA | RB  |     |   10  | 1  | 0100 110 |Rc| rsvd |
  97 | NN | RA | RB  |     |   11  | 1  | 0100 110 |Rc| rsvd |
  98 | NN | RA | RB  | sh  | itype | SH | 1000 110 |Rc| bmopsi |
  99 | NN | RA | RB  |     |       |    | 1100 110 |Rc| rsvd |
 100 | NN | RA | RB  |     |       | 1  | 0001 110 |Rc| rsvd |
 101 | NN | RA | RB  | RC  |   00  | 0  | 0001 110 |Rc| vec sbfm |
 102 | NN | RA | RB  | RC  |   01  | 0  | 0001 110 |Rc| vec sofm |
 103 | NN | RA | RB  | RC  |   10  | 0  | 0001 110 |Rc| vec sifm |
 104 | NN | RA | RB  | RC  |   11  | 0  | 0001 110 |Rc| vec cprop |
 105 | NN | RA | RB  |     |       | 0  | 0101 110 |Rc| rsvd |
 106 | NN | RA | RB  | RC  | 00    | 0  | 0010 110 |Rc| gorc |
 107 | NN | RA | RB  | sh  | 00    | SH | 1010 110 |Rc| gorci |
 108 | NN | RA | RB  | RC  | 00    | 0  | 0110 110 |Rc| gorcw |
 109 | NN | RA | RB  | sh  | 00    | 0  | 1110 110 |Rc| gorcwi |
 110 | NN | RA | RB  | RC  | 00    | 1  | 1110 110 |Rc| bmator  |
 111 | NN | RA | RB  | RC  | 01    | 0  | 0010 110 |Rc| grev |
 112 | NN | RA | RB  | RC  | 01    | 1  | 0010 110 |Rc| clmul |
 113 | NN | RA | RB  | sh  | 01    | SH | 1010 110 |Rc| grevi |
 114 | NN | RA | RB  | RC  | 01    | 0  | 0110 110 |Rc| grevw |
 115 | NN | RA | RB  | sh  | 01    | 0  | 1110 110 |Rc| grevwi |
 116 | NN | RA | RB  | RC  | 01    | 1  | 1110 110 |Rc| bmatxor   |
 117 | NN | RA | RB  | RC  | 10    | 0  | 0010 110 |Rc| shfl |
 118 | NN | RA | RB  | sh  | 10    | SH | 1010 110 |Rc| shfli |
 119 | NN | RA | RB  | RC  | 10    | 0  | 0110 110 |Rc| shflw |
 120 | NN | RA | RB  | RC  | 10    |    | 1110 110 |Rc| rsvd   |
 121 | NN | RA | RB  | RC  | 11    | 0  | 1110 110 |Rc| clmulr  |
 122 | NN | RA | RB  | RC  | 11    | 1  | 1110 110 |Rc| clmulh  |
 123 | NN |    |     |     |       |    | --11 110 |Rc| setvl  |
 124
 125 # count leading/trailing zeros with mask
 126
 127 in v3.1 p105
 128
 129 ```
 130 count = 0
 131 do i = 0 to 63 if((RB)i=1) then do
 132 if((RS)i=1) then break end end count ← count + 1
 133 RA ← EXTZ64(count)
 134 ```
 135
 136 # bit to byte permute
 137
 138 similar to matrix permute in RV bitmanip, which has XOR and OR variants
 139
 140     do j = 0 to 7
 141       do k = 0 to 7
 142          b = VSR[VRB+32].dword[i].byte[k].bit[j]
 143          VSR[VRT+32].dword[i].byte[j].bit[k] = b
 144
 145 #  bit deposit
 146
 147 vpdepd VRT,VRA,VRB, identical to RV bitmamip bdep, found already in v3.1 p106
 148
 149     do while(m < 64)
 150        if VSR[VRB+32].dword[i].bit[63-m]=1 then do
 151           result = VSR[VRA+32].dword[i].bit[63-k]
 152           VSR[VRT+32].dword[i].bit[63-m] = result
 153           k = k + 1
 154        m = m + 1
 155
 156 ```
 157
 158 uint_xlen_t bdep(uint_xlen_t RA, uint_xlen_t RB)
 159 {
 160     uint_xlen_t r = 0;
 161     for (int i = 0, j = 0; i < XLEN; i++)
 162         if ((RB >> i) & 1) {
 163             if ((RA >> j) & 1)
 164                 r |= uint_xlen_t(1) << i;
 165             j++;
 166         }
 167     return r;
 168 }
 169
 170 ```
 171
 172 # bit extract
 173
 174 other way round: identical to RV bext, found in v3.1 p196
 175
 176 ```
 177 uint_xlen_t bext(uint_xlen_t RA, uint_xlen_t RB)
 178 {
 179     uint_xlen_t r = 0;
 180     for (int i = 0, j = 0; i < XLEN; i++)
 181         if ((RB >> i) & 1) {
 182             if ((RA >> i) & 1)
 183                 r |= uint_xlen_t(1) << j;
 184             j++;
 185         }
 186     return r;
 187 }
 188 ```
 189
 190 # centrifuge
 191
 192 found in v3.1 p106 so not to be added here
 193
 194 ```
 195 ptr0 = 0
 196 ptr1 = 0
 197 do i = 0 to 63
 198     if((RB)i=0) then do
 199        resultptr0 = (RS)i
 200     end
 201     ptr0 = ptr0 + 1
 202     if((RB)63-i==1) then do
 203         result63-ptr1 = (RS)63-i
 204     end
 205     ptr1 = ptr1 + 1
 206 RA = result
 207 ```
 208
 209 # int min/max
 210
 211 signed and unsigned min/max for integer.  this is sort-of partly synthesiseable in [[sv/svp64]] with pred-result as long as the dest reg is one of the sources, but not both signed and unsigned.  when the dest is also one of the srces and the mv fails due to the CR bittest failing this will only overwrite the dest where the src is greater (or less).
 212
 213 signed/unsigned min/max gives more flexibility.
 214
 215 ```
 216 uint_xlen_t min(uint_xlen_t rs1, uint_xlen_t rs2)
 217 { return (int_xlen_t)rs1 < (int_xlen_t)rs2 ? rs1 : rs2;
 218 }
 219 uint_xlen_t max(uint_xlen_t rs1, uint_xlen_t rs2)
 220 { return (int_xlen_t)rs1 > (int_xlen_t)rs2 ? rs1 : rs2;
 221 }
 222 uint_xlen_t minu(uint_xlen_t rs1, uint_xlen_t rs2)
 223 { return rs1 < rs2 ? rs1 : rs2;
 224 }
 225 uint_xlen_t maxu(uint_xlen_t rs1, uint_xlen_t rs2)
 226 { return rs1 > rs2 ? rs1 : rs2;
 227 }
 228 ```
 229
 230
 231 # ternary bitops
 232
 233 Similar to FPGA LUTs: for every bit perform a lookup into a table using an 8bit immediate, or in another register
 234
 235 | 0.5|6.10|11.15|16.20| 21..25| 26..30   |31|
 236 | -- | -- | --- | --- | ----- | -------- |--|
 237 | NN | RT | RA  | RB  | im0-4 | im5-7 00 |Rc|
 238
 239     for i in range(64):
 240         idx = RT[i] << 2 | RA[i] << 1 | RB[i]
 241         RT[i] = (imm & (1<<idx)) != 0
 242
 243 bits 21..22 may be used to specify a mode, such as treating the whole integer zero/nonzero and putting 1/0 in the result, rather than bitwise test.
 244
 245 a 4 operand variant which becomes more along the lines of an FPGA:
 246
 247 | 0.5|6.10|11.15|16.20|21.25| 26...30  |31|
 248 | -- | -- | --- | --- | --- | -------- |--|
 249 | NN | RT | RA  | RB  | RC  | mode 001 |Rc|
 250
 251     for i in range(64):
 252         idx = RT[i] << 2 | RA[i] << 1 | RB[i]
 253         RT[i] = (RC & (1<<idx)) != 0
 254
 255 mode (2 bit) may be used to do inversion of ordering, similar to carryless mul,
 256 3 modes.
 257
 258 also, another possible variant involving swizzle and vec4:
 259
 260 | 0.5|6.10|11.15| 16.23 |24.27 | 28.30 |31|
 261 | -- | -- | --- | ----- | ---- | ----- |--|
 262 | NN | RT | RA  | imm   | mask | 101   |1 |
 263
 264     for i in range(8):
 265         idx = RA.x[i] << 2 | RA.y[i] << 1 | RA.z[i]
 266         res = (imm & (1<<idx)) != 0
 267         for j in range(3):
 268              if mask[j]: RT[i+j*8] = res
 269
 270 another mode selection would be CRs not Ints.
 271
 272 | 0.5|6.8 | 9.11|12.14|15|16.23|24.27 | 28.30|31|
 273 | -- | -- | --- | --- |- |-----|----- | -----|--|
 274 | NN | BA | BB  | BC  |0 |imm  | mask | 101  |0 |
 275
 276     for i in range(4):
 277         if not mask[i] continue
 278         idx = crregs[BA][i] << 2 |
 279               crregs[BB][i] << 1 |
 280               crregs[BC][i]
 281         crregs[BA][i] = (imm & (1<<idx)) != 0
 282
 283 # bitmask set
 284
 285 based on RV bitmanip singlebit set, instruction format similar to shift
 286 [[isa/fixedshift]].  bmext is actually covered already (shift-with-mask rldicl but only immediate version).
 287 however bitmask-invert is not, and set/clr are not covered, although they can use the same Shift ALU.
 288
 289 bmext (RB) version is not the same as rldicl because bmext is a right shift by RC, where rldicl is a left rotate.  for the immediate version this does not matter, so a bmexti is not required.
 290 bmrev however there is no direct equivalent and consequently a bmrevi is required.
 291
 292 bmset (register for mask amount) is particularly useful for creating
 293 predicate masks where the length is a dynamic runtime quantity.
 294 bmset(RA=0, RB=0, RC=mask) will produce a run of ones of length "mask" in a single instruction without needing to initialise or depend on any other registers.
 295
 296 | 0.5|6.10|11.15|16.20|21.25| 26..30  |31| name  |
 297 | -- | -- | --- | --- | --- | ------- |--| ----- |
 298 | NN | RT | RA  | RB  | RC  | mode 010 |Rc| bm*   |
 299 | NN | RT | RA  | RB  | RC  | 0 1  111 |Rc| bmrev |
 300
 301
 302 ```
 303 uint_xlen_t bmset(RA, RB, sh)
 304 {
 305     int shamt = RB & (XLEN - 1);
 306     mask = (2<<sh)-1;
 307     return RA | (mask << shamt);
 308 }
 309
 310 uint_xlen_t bmclr(RA, RB, sh)
 311 {
 312     int shamt = RB & (XLEN - 1);
 313     mask = (2<<sh)-1;
 314     return RA & ~(mask << shamt);
 315 }
 316
 317 uint_xlen_t bminv(RA, RB, sh)
 318 {
 319     int shamt = RB & (XLEN - 1);
 320     mask = (2<<sh)-1;
 321     return RA ^ (mask << shamt);
 322 }
 323
 324 uint_xlen_t bmext(RA, RB, sh)
 325 {
 326     int shamt = RB & (XLEN - 1);
 327     mask = (2<<sh)-1;
 328     return mask & (RA >> shamt);
 329 }
 330 ```
 331
 332 bitmask extract with reverse.  can be done by bitinverting all of RA and getting bits of RA from the opposite end.
 333
 334 ```
 335 msb = rb[5:0];
 336 rev[0:msb] = ra[msb:0];
 337 rt = ZE(rev[msb:0]);
 338
 339 uint_xlen_t bmextrev(RA, RB, sh)
 340 {
 341     int shamt = (RB & (XLEN - 1));
 342     shamt = (XLEN-1)-shamt;  # shift other end
 343     bra = bitreverse(RA)     # swap LSB-MSB
 344     mask = (2<<sh)-1;
 345     return mask & (bra >> shamt);
 346 }
 347 ```
 348
 349 | 0.5|6.10|11.15|16.20|21.26| 27..30  |31| name   |
 350 | -- | -- | --- | --- | --- | ------- |--| ------ |
 351 | NN | RT | RA  | RB  | sh  | 0   111 |Rc| bmrevi |
 352
 353
 354
 355 # grev
 356
 357 based on RV bitmanip
 358
 359 ```
 360 uint64_t grev64(uint64_t RA, uint64_t RB)
 361 {
 362     uint64_t x = RA;
 363     int shamt = RB & 63;
 364     if (shamt & 1) x = ((x &  0x5555555555555555LL) <<  1) |
 365                         ((x & 0xAAAAAAAAAAAAAAAALL) >>  1);
 366     if (shamt & 2) x = ((x &  0x3333333333333333LL) <<  2) |
 367                         ((x & 0xCCCCCCCCCCCCCCCCLL) >>  2);
 368     if (shamt & 4) x = ((x &  0x0F0F0F0F0F0F0F0FLL) <<  4) |
 369                         ((x & 0xF0F0F0F0F0F0F0F0LL) >>  4);
 370     if (shamt & 8) x = ((x &  0x00FF00FF00FF00FFLL) <<  8) |
 371                         ((x & 0xFF00FF00FF00FF00LL) >>  8);
 372     if (shamt & 16) x = ((x & 0x0000FFFF0000FFFFLL) << 16) |
 373                         ((x & 0xFFFF0000FFFF0000LL) >> 16);
 374     if (shamt & 32) x = ((x & 0x00000000FFFFFFFFLL) << 32) |
 375                         ((x & 0xFFFFFFFF00000000LL) >> 32);
 376     return x;
 377 }
 378
 379 ```
 380
 381 # shuffle / unshuffle
 382
 383 based on RV bitmanip
 384
 385 ```
 386 uint32_t shfl32(uint32_t RA, uint32_t RB)
 387 {
 388     uint32_t x = RA;
 389     int shamt = RB & 15;
 390     if (shamt & 8) x  = shuffle32_stage(x, 0x00ff0000, 0x0000ff00, 8);
 391     if (shamt & 4) x  = shuffle32_stage(x, 0x0f000f00, 0x00f000f0, 4);
 392     if (shamt & 2) x  = shuffle32_stage(x, 0x30303030, 0x0c0c0c0c, 2);
 393     if (shamt & 1) x  = shuffle32_stage(x, 0x44444444, 0x22222222, 1);
 394     return x;
 395 }
 396 uint32_t unshfl32(uint32_t RA, uint32_t RB)
 397 {
 398     uint32_t x = RA;
 399     int shamt = RB & 15;
 400     if (shamt & 1) x  = shuffle32_stage(x, 0x44444444, 0x22222222, 1);
 401     if (shamt & 2) x  = shuffle32_stage(x, 0x30303030, 0x0c0c0c0c, 2);
 402     if (shamt & 4) x  = shuffle32_stage(x, 0x0f000f00, 0x00f000f0, 4);
 403     if (shamt & 8) x  = shuffle32_stage(x, 0x00ff0000, 0x0000ff00, 8);
 404     return x;
 405 }
 406
 407 uint64_t shuffle64_stage(uint64_t src, uint64_t maskL, uint64_t maskR, int N)
 408 {
 409     uint64_t x = src & ~(maskL | maskR);
 410     x |= ((src << N) & maskL) | ((src >> N) & maskR);
 411     return x;
 412 }
 413 uint64_t shfl64(uint64_t RA, uint64_t RB)
 414 {
 415     uint64_t x = RA;
 416     int shamt = RB & 31;
 417     if (shamt & 16) x = shuffle64_stage(x, 0x0000ffff00000000LL,
 418                                            0x00000000ffff0000LL, 16);
 419     if (shamt & 8) x = shuffle64_stage(x, 0x00ff000000ff0000LL,
 420                                            0x0000ff000000ff00LL, 8);
 421     if (shamt & 4) x = shuffle64_stage(x, 0x0f000f000f000f00LL,
 422                                            0x00f000f000f000f0LL, 4);
 423     if (shamt & 2) x = shuffle64_stage(x, 0x3030303030303030LL,
 424                                            0x0c0c0c0c0c0c0c0cLL, 2);
 425     if (shamt & 1) x = shuffle64_stage(x, 0x4444444444444444LL,
 426                                            0x2222222222222222LL, 1);
 427     return x;
 428 }
 429 uint64_t unshfl64(uint64_t RA, uint64_t RB)
 430 {
 431     uint64_t x = RA;
 432     int shamt = RB & 31;
 433     if (shamt &  1) x = shuffle64_stage(x, 0x4444444444444444LL,
 434                                            0x2222222222222222LL, 1);
 435     if (shamt &  2) x = shuffle64_stage(x, 0x3030303030303030LL,
 436                                            0x0c0c0c0c0c0c0c0cLL, 2);
 437     if (shamt &  4) x = shuffle64_stage(x, 0x0f000f000f000f00LL,
 438                                            0x00f000f000f000f0LL, 4);
 439     if (shamt &  8) x = shuffle64_stage(x, 0x00ff000000ff0000LL,
 440                                            0x0000ff000000ff00LL, 8);
 441     if (shamt & 16) x = shuffle64_stage(x, 0x0000ffff00000000LL,
 442                                            0x00000000ffff0000LL, 16);
 443     return x;
 444 }
 445 ```
 446
 447 # xperm
 448
 449 based on RV bitmanip
 450
 451 ```
 452 uint_xlen_t xperm(uint_xlen_t RA, uint_xlen_t RB, int sz_log2)
 453 {
 454     uint_xlen_t r = 0;
 455     uint_xlen_t sz = 1LL << sz_log2;
 456     uint_xlen_t mask = (1LL << sz) - 1;
 457     for (int i = 0; i < XLEN; i += sz) {
 458         uint_xlen_t pos = ((RB >> i) & mask) << sz_log2;
 459         if (pos < XLEN)
 460             r |= ((RA >> pos) & mask) << i;
 461     }
 462     return r;
 463 }
 464 uint_xlen_t xperm_n (uint_xlen_t RA, uint_xlen_t RB)
 465 {  return xperm(RA, RB, 2); }
 466 uint_xlen_t xperm_b (uint_xlen_t RA, uint_xlen_t RB)
 467 {  return xperm(RA, RB, 3); }
 468 uint_xlen_t xperm_h (uint_xlen_t RA, uint_xlen_t RB)
 469 {  return xperm(RA, RB, 4); }
 470 uint_xlen_t xperm_w (uint_xlen_t RA, uint_xlen_t RB)
 471 {  return xperm(RA, RB, 5); }
 472 ```
 473
 474 # gorc
 475
 476 based on RV bitmanip
 477
 478 ```
 479 uint32_t gorc32(uint32_t RA, uint32_t RB)
 480 {
 481     uint32_t x = RA;
 482     int shamt = RB & 31;
 483     if (shamt & 1) x |= ((x & 0x55555555) << 1)   |  ((x &  0xAAAAAAAA) >> 1);
 484     if (shamt & 2) x |= ((x & 0x33333333) << 2)   |  ((x &  0xCCCCCCCC) >> 2);
 485     if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4)   |  ((x &  0xF0F0F0F0) >> 4);
 486     if (shamt & 8) x |= ((x & 0x00FF00FF) << 8)   |  ((x &  0xFF00FF00) >> 8);
 487     if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) |  ((x &  0xFFFF0000) >> 16);
 488     return x;
 489 }
 490 uint64_t gorc64(uint64_t RA, uint64_t RB)
 491 {
 492     uint64_t x = RA;
 493     int shamt = RB & 63;
 494     if (shamt & 1) x |= ((x & 0x5555555555555555LL)   <<   1) |
 495                          ((x & 0xAAAAAAAAAAAAAAAALL)  >>  1);
 496     if (shamt & 2) x |= ((x & 0x3333333333333333LL)   <<   2) |
 497                          ((x & 0xCCCCCCCCCCCCCCCCLL)  >>  2);
 498     if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL)   <<   4) |
 499                          ((x & 0xF0F0F0F0F0F0F0F0LL)  >>  4);
 500     if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL)   <<   8) |
 501                          ((x & 0xFF00FF00FF00FF00LL)  >>  8);
 502     if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL)  << 16) |
 503                          ((x & 0xFFFF0000FFFF0000LL)  >> 16);
 504     if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL)  << 32) |
 505                          ((x & 0xFFFFFFFF00000000LL)  >> 32);
 506     return x;
 507 }
 508
 509 ```
 510
 511 # cmix
 512
 513 based on RV bitmanip, covered by ternary bitops
 514
 515 ```
 516 uint_xlen_t cmix(uint_xlen_t RA, uint_xlen_t RB, uint_xlen_t RC) {
 517     return (RA & RB) | (RC & ~RB);
 518 }
 519 ```
 520
 521 # carryless mul
 522
 523 based on RV bitmanip
 524 see https://en.wikipedia.org/wiki/CLMUL_instruction_set
 525
 526 ```
 527 uint_xlen_t clmul(uint_xlen_t RA, uint_xlen_t RB)
 528 {
 529     uint_xlen_t x = 0;
 530     for (int i = 0; i < XLEN; i++)
 531         if ((RB >> i) & 1)
 532             x ^= RA << i;
 533     return x;
 534 }
 535 uint_xlen_t clmulh(uint_xlen_t RA, uint_xlen_t RB)
 536 {
 537     uint_xlen_t x = 0;
 538     for (int i = 1; i < XLEN; i++)
 539         if ((RB >> i) & 1)
 540             x ^= RA >> (XLEN-i);
 541     return x;
 542 }
 543 uint_xlen_t clmulr(uint_xlen_t RA, uint_xlen_t RB)
 544 {
 545     uint_xlen_t x = 0;
 546     for (int i = 0; i < XLEN; i++)
 547         if ((RB >> i) & 1)
 548             x ^= RA >> (XLEN-i-1);
 549     return x;
 550 }
 551 ```
 552 # Galois Field
 553
 554 see <https://courses.csail.mit.edu/6.857/2016/files/ffield.py>
 555
 556 ## Multiply
 557
 558 this requires 3 parameters and a "degree"
 559
 560     RT = GFMUL(RA, RB, gfdegree, modulo=RC)
 561
 562 realistically with the degree also needing to be an immediate it should be brought down to an overwrite version:
 563
 564     RS = GFMUL(RS, RA, gfdegree, modulo=RB)
 565     RS = GFMUL(RS, RA, gfdegree=RC, modulo=RB)
 566
 567 | 0.5|6.10|11.15|16.20|21.25| 26..30  |31|
 568 | -- | -- | --- | --- | --- | ------- |--|
 569 | NN | RS | RA  | RB  | deg | 00  011 |Rc|
 570 | NN | RS | RA  | RB  | RC  | 11  011 |Rc|
 571
 572 where the SimpleV variant may override RS-as-src differently from RS-as-dest
 573
 574
 575
 576 ```
 577 from functools import reduce
 578
 579 # constants used in the multGF2 function
 580 mask1 = mask2 = polyred = None
 581
 582 def setGF2(degree, irPoly):
 583     """Define parameters of binary finite field GF(2^m)/g(x)
 584        - degree: extension degree of binary field
 585        - irPoly: coefficients of irreducible polynomial g(x)
 586     """
 587     def i2P(sInt):
 588         """Convert an integer into a polynomial"""
 589         return [(sInt >> i) & 1
 590                 for i in reversed(range(sInt.bit_length()))]
 591
 592     global mask1, mask2, polyred
 593     mask1 = mask2 = 1 << degree
 594     mask2 -= 1
 595     polyred = reduce(lambda x, y: (x << 1) + y, i2P(irPoly)[1:])
 596
 597 def multGF2(p1, p2):
 598     """Multiply two polynomials in GF(2^m)/g(x)"""
 599     p = 0
 600     while p2:
 601         if p2 & 1:
 602             p ^= p1
 603         p1 <<= 1
 604         if p1 & mask1:
 605             p1 ^= polyred
 606         p2 >>= 1
 607     return p & mask2
 608
 609 if __name__ == "__main__":
 610
 611     # Define binary field GF(2^3)/x^3 + x + 1
 612     setGF2(3, 0b1011)
 613
 614     # Evaluate the product (x^2 + x + 1)(x^2 + 1)
 615     print("{:02x}".format(multGF2(0b111, 0b101)))
 616
 617     # Define binary field GF(2^8)/x^8 + x^4 + x^3 + x + 1
 618     # (used in the Advanced Encryption Standard-AES)
 619     setGF2(8, 0b100011011)
 620
 621     # Evaluate the product (x^7)(x^7 + x + 1)
 622     print("{:02x}".format(multGF2(0b10000000, 0b10000011)))
 623 ```
 624 ## GF add
 625
 626     RS = GFADDI(RS, RA|0, gfdegree, modulo=RB)
 627     RS = GFADD(RS, RA|0, gfdegree=RC, modulo=RB)
 628
 629 | 0.5|6.10|11.15|16.20|21.25| 26..30  |31| name  |
 630 | -- | -- | --- | --- | --- | ------- |--| ----- |
 631 | NN | RS | RA  | RB  | deg | 0 1  011 |Rc| gfaddi |
 632 | NN | RS | RA  | RB  | RC  | 1 1  111 |Rc| gfadd |
 633
 634 GFMOD is a pseudo-op where RA=0
 635
 636 ## gf invert
 637
 638 ```
 639 def gf_degree(a) :
 640   res = 0
 641   a >>= 1
 642   while (a != 0) :
 643     a >>= 1;
 644     res += 1;
 645   return res
 646
 647 def gf_invert(a, mod=0x1B) :
 648   v = mod
 649   g1 = 1
 650   g2 = 0
 651   j = gf_degree(a) - 8
 652
 653   while (a != 1) :
 654     if (j < 0) :
 655       a, v = v, a
 656       g1, g2 = g2, g1
 657       j = -j
 658
 659     a ^= v << j
 660     g1 ^= g2 << j
 661
 662     a %= 256  # Emulating 8-bit overflow
 663     g1 %= 256 # Emulating 8-bit overflow
 664
 665     j = gf_degree(a) - gf_degree(v)
 666
 667   return g1
 668 ```
 669
 670 # bitmatrix
 671
 672 ```
 673 uint64_t bmatflip(uint64_t RA)
 674 {
 675     uint64_t x = RA;
 676     x = shfl64(x, 31);
 677     x = shfl64(x, 31);
 678     x = shfl64(x, 31);
 679     return x;
 680 }
 681 uint64_t bmatxor(uint64_t RA, uint64_t RB)
 682 {
 683     // transpose of RB
 684     uint64_t RBt = bmatflip(RB);
 685     uint8_t u[8]; // rows of RA
 686     uint8_t v[8]; // cols of RB
 687     for (int i = 0; i < 8; i++) {
 688         u[i] = RA >> (i*8);
 689         v[i] = RBt >> (i*8);
 690     }
 691     uint64_t x = 0;
 692     for (int i = 0; i < 64; i++) {
 693         if (pcnt(u[i / 8] & v[i % 8]) & 1)
 694             x |= 1LL << i;
 695     }
 696     return x;
 697 }
 698 uint64_t bmator(uint64_t RA, uint64_t RB)
 699 {
 700     // transpose of RB
 701     uint64_t RBt = bmatflip(RB);
 702     uint8_t u[8]; // rows of RA
 703     uint8_t v[8]; // cols of RB
 704     for (int i = 0; i < 8; i++) {
 705         u[i] = RA >> (i*8);
 706         v[i] = RBt >> (i*8);
 707     }
 708     uint64_t x = 0;
 709     for (int i = 0; i < 64; i++) {
 710         if ((u[i / 8] & v[i % 8]) != 0)
 711             x |= 1LL << i;
 712     }
 713     return x;
 714 }
 715
 716 ```