7 this extension amalgamates bitmanipulation primitives from many sources, including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX. Vectorisation and SIMD are removed: these are straight scalar (element) operations making them suitable for embedded applications.
8 Vectorisation Context is provided by [[openpower/sv]].
10 When combined with SV, scalar variants of bitmanip operations found in VSX are added so that VSX may be retired as "legacy" in the far future (10 to 20 years). Also, VSX is hundreds of opcodes, requires 128 bit pathways, and is wholly unsuited to low power or embedded scenarios.
12 ternaryv is experimental and is the only operation that may be considered a "Packed SIMD". It is added as a variant of the already well-justified ternary operation (done in AVX512 as an immediate only) "because it looks fun". As it is based on the LUT4 concept it will allow accelerated emulation of FPGAs. Other vendors of ISAs are buying FPGA companies to achieve similar objectives.
14 general-purpose Galois Field operations are added so as to avoid huge custom opcode proliferation across many areas of Computer Science. however for convenience and also to avoid setup costs, some of the more common operations (clmul, crc32) are also added. The expectation is that these operations would all be covered by the same pipeline.
16 note that there are brownfield spaces below that could incorporate some of the set-before-first and other scalar operations listed in [[sv/vector_ops]], and
17 the [[sv/av_opcodes]] as well as [[sv/setvl]]
21 * <https://en.wikiversity.org/wiki/Reed%E2%80%93Solomon_codes_for_coders>
22 * <https://maths-people.anu.edu.au/~brent/pd/rpb232tr.pdf>
26 minor opcode allocation
29 | ------ |--| --------- |
35 | 101 |0 | ternarycr |
41 | dest | src1 | subop | op |
42 | ---- | ---- | ----- | -------- |
43 | RT | RA | .. | bmatflip |
47 | dest | src1 | src2 | subop | op |
48 | ---- | ---- | ---- | ----- | -------- |
49 | RT | RA | RB | or | bmatflip |
50 | RT | RA | RB | xor | bmatflip |
51 | RT | RA | RB | | grev |
52 | RT | RA | RB | | clmul* |
53 | RT | RA | RB | | gorc |
54 | RT | RA | RB | shuf | shuffle |
55 | RT | RA | RB | unshuf| shuffle |
56 | RT | RA | RB | width | xperm |
57 | RT | RA | RB | type | minmax |
58 | RT | RA | RB | | av abs avgadd |
59 | RT | RA | RB | type | vmask ops |
68 | 0.5|6.10|11.15|16.20|21..25 | 26....30 |31| name |
69 | -- | -- | --- | --- | ----- | -------- |--| ------ |
70 | NN | RT | RA | RB | RC | mode 001 |Rc| ternary |
71 | NN | RT | RA | RB | im0-4 | im5-7 00 |Rc| ternaryi |
72 | NN | RS | RA | RB | RC | 00 011 |Rc| gfmul |
73 | NN | RS | RA | RB | RC | 01 011 |Rc| gfadd |
74 | NN | RT | RA | RB | deg | 10 011 |Rc| gfinv |
75 | NN | RS | RA | RB | deg | 11 011 |Rc| gfmuli |
76 | NN | RS | RA | RB | deg | 11 111 |Rc| gfaddi |
78 | 0.5|6.10|11.15| 16.23 |24.27 | 28.30 |31| name |
79 | -- | -- | --- | ----- | ---- | ----- |--| ------ |
80 | NN | RT | RA | imm | mask | 101 |1 | ternaryv |
82 | 0.5|6.8 | 9.11|12.14|15|16.23|24.27 | 28.30|31| name |
83 | -- | -- | --- | --- |- |-----|----- | -----|--| -------|
84 | NN | BA | BB | BC |0 |imm | mask | 101 |0 | ternarycr |
86 ops (note that av avg and abs as well as vec scalar mask
89 | 0.5|6.10|11.15|16.20| 21.22 | 23 | 24....30 |31| name |
90 | -- | -- | --- | --- | ----- | -- | -------- |--| ---- |
91 | NN | RA | RB | | | 0 | 0000 110 |Rc| rsvd |
92 | NN | RA | RB | RC | itype | 1 | 0000 110 |Rc| xperm |
93 | NN | RA | RB | RC | itype | 0 | 0100 110 |Rc| minmax |
94 | NN | RA | RB | RC | 00 | 1 | 0100 110 |Rc| av avgadd |
95 | NN | RA | RB | RC | 01 | 1 | 0100 110 |Rc| av abs |
96 | NN | RA | RB | | 10 | 1 | 0100 110 |Rc| rsvd |
97 | NN | RA | RB | | 11 | 1 | 0100 110 |Rc| rsvd |
98 | NN | RA | RB | sh | itype | SH | 1000 110 |Rc| bmopsi |
99 | NN | RA | RB | | | | 1100 110 |Rc| rsvd |
100 | NN | RA | RB | | | 1 | 0001 110 |Rc| rsvd |
101 | NN | RA | RB | RC | 00 | 0 | 0001 110 |Rc| vec sbfm |
102 | NN | RA | RB | RC | 01 | 0 | 0001 110 |Rc| vec sofm |
103 | NN | RA | RB | RC | 10 | 0 | 0001 110 |Rc| vec sifm |
104 | NN | RA | RB | RC | 11 | 0 | 0001 110 |Rc| vec cprop |
105 | NN | RA | RB | | | 0 | 0101 110 |Rc| rsvd |
106 | NN | RA | RB | RC | 00 | 0 | 0010 110 |Rc| gorc |
107 | NN | RA | RB | sh | 00 | SH | 1010 110 |Rc| gorci |
108 | NN | RA | RB | RC | 00 | 0 | 0110 110 |Rc| gorcw |
109 | NN | RA | RB | sh | 00 | 0 | 1110 110 |Rc| gorcwi |
110 | NN | RA | RB | RC | 00 | 1 | 1110 110 |Rc| bmator |
111 | NN | RA | RB | RC | 01 | 0 | 0010 110 |Rc| grev |
112 | NN | RA | RB | RC | 01 | 1 | 0010 110 |Rc| clmul |
113 | NN | RA | RB | sh | 01 | SH | 1010 110 |Rc| grevi |
114 | NN | RA | RB | RC | 01 | 0 | 0110 110 |Rc| grevw |
115 | NN | RA | RB | sh | 01 | 0 | 1110 110 |Rc| grevwi |
116 | NN | RA | RB | RC | 01 | 1 | 1110 110 |Rc| bmatxor |
117 | NN | RA | RB | RC | 10 | 0 | 0010 110 |Rc| shfl |
118 | NN | RA | RB | sh | 10 | SH | 1010 110 |Rc| shfli |
119 | NN | RA | RB | RC | 10 | 0 | 0110 110 |Rc| shflw |
120 | NN | RA | RB | RC | 10 | | 1110 110 |Rc| rsvd |
121 | NN | RA | RB | RC | 11 | 0 | 1110 110 |Rc| clmulr |
122 | NN | RA | RB | RC | 11 | 1 | 1110 110 |Rc| clmulh |
123 | NN | | | | | | --11 110 |Rc| setvl |
125 # count leading/trailing zeros with mask
131 do i = 0 to 63 if((RB)i=1) then do
132 if((RS)i=1) then break end end count ← count + 1
136 # bit to byte permute
138 similar to matrix permute in RV bitmanip, which has XOR and OR variants
142 b = VSR[VRB+32].dword[i].byte[k].bit[j]
143 VSR[VRT+32].dword[i].byte[j].bit[k] = b
147 vpdepd VRT,VRA,VRB, identical to RV bitmamip bdep, found already in v3.1 p106
150 if VSR[VRB+32].dword[i].bit[63-m]=1 then do
151 result = VSR[VRA+32].dword[i].bit[63-k]
152 VSR[VRT+32].dword[i].bit[63-m] = result
158 uint_xlen_t bdep(uint_xlen_t RA, uint_xlen_t RB)
161 for (int i = 0, j = 0; i < XLEN; i++)
164 r |= uint_xlen_t(1) << i;
174 other way round: identical to RV bext, found in v3.1 p196
177 uint_xlen_t bext(uint_xlen_t RA, uint_xlen_t RB)
180 for (int i = 0, j = 0; i < XLEN; i++)
183 r |= uint_xlen_t(1) << j;
192 found in v3.1 p106 so not to be added here
202 if((RB)63-i==1) then do
203 result63-ptr1 = (RS)63-i
211 signed and unsigned min/max for integer. this is sort-of partly synthesiseable in [[sv/svp64]] with pred-result as long as the dest reg is one of the sources, but not both signed and unsigned. when the dest is also one of the srces and the mv fails due to the CR bittest failing this will only overwrite the dest where the src is greater (or less).
213 signed/unsigned min/max gives more flexibility.
216 uint_xlen_t min(uint_xlen_t rs1, uint_xlen_t rs2)
217 { return (int_xlen_t)rs1 < (int_xlen_t)rs2 ? rs1 : rs2;
219 uint_xlen_t max(uint_xlen_t rs1, uint_xlen_t rs2)
220 { return (int_xlen_t)rs1 > (int_xlen_t)rs2 ? rs1 : rs2;
222 uint_xlen_t minu(uint_xlen_t rs1, uint_xlen_t rs2)
223 { return rs1 < rs2 ? rs1 : rs2;
225 uint_xlen_t maxu(uint_xlen_t rs1, uint_xlen_t rs2)
226 { return rs1 > rs2 ? rs1 : rs2;
233 Similar to FPGA LUTs: for every bit perform a lookup into a table using an 8bit immediate, or in another register
235 | 0.5|6.10|11.15|16.20| 21..25| 26..30 |31|
236 | -- | -- | --- | --- | ----- | -------- |--|
237 | NN | RT | RA | RB | im0-4 | im5-7 00 |Rc|
240 idx = RT[i] << 2 | RA[i] << 1 | RB[i]
241 RT[i] = (imm & (1<<idx)) != 0
243 bits 21..22 may be used to specify a mode, such as treating the whole integer zero/nonzero and putting 1/0 in the result, rather than bitwise test.
245 a 4 operand variant which becomes more along the lines of an FPGA:
247 | 0.5|6.10|11.15|16.20|21.25| 26...30 |31|
248 | -- | -- | --- | --- | --- | -------- |--|
249 | NN | RT | RA | RB | RC | mode 001 |Rc|
252 idx = RT[i] << 2 | RA[i] << 1 | RB[i]
253 RT[i] = (RC & (1<<idx)) != 0
255 mode (2 bit) may be used to do inversion of ordering, similar to carryless mul,
258 also, another possible variant involving swizzle and vec4:
260 | 0.5|6.10|11.15| 16.23 |24.27 | 28.30 |31|
261 | -- | -- | --- | ----- | ---- | ----- |--|
262 | NN | RT | RA | imm | mask | 101 |1 |
265 idx = RA.x[i] << 2 | RA.y[i] << 1 | RA.z[i]
266 res = (imm & (1<<idx)) != 0
268 if mask[j]: RT[i+j*8] = res
270 another mode selection would be CRs not Ints.
272 | 0.5|6.8 | 9.11|12.14|15|16.23|24.27 | 28.30|31|
273 | -- | -- | --- | --- |- |-----|----- | -----|--|
274 | NN | BA | BB | BC |0 |imm | mask | 101 |0 |
277 if not mask[i] continue
278 idx = crregs[BA][i] << 2 |
281 crregs[BA][i] = (imm & (1<<idx)) != 0
285 based on RV bitmanip singlebit set, instruction format similar to shift
286 [[isa/fixedshift]]. bmext is actually covered already (shift-with-mask rldicl but only immediate version).
287 however bitmask-invert is not, and set/clr are not covered, although they can use the same Shift ALU.
289 bmext (RB) version is not the same as rldicl because bmext is a right shift by RC, where rldicl is a left rotate. for the immediate version this does not matter, so a bmexti is not required.
290 bmrev however there is no direct equivalent and consequently a bmrevi is required.
292 bmset (register for mask amount) is particularly useful for creating
293 predicate masks where the length is a dynamic runtime quantity.
294 bmset(RA=0, RB=0, RC=mask) will produce a run of ones of length "mask" in a single instruction without needing to initialise or depend on any other registers.
296 | 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name |
297 | -- | -- | --- | --- | --- | ------- |--| ----- |
298 | NN | RT | RA | RB | RC | mode 010 |Rc| bm* |
299 | NN | RT | RA | RB | RC | 0 1 111 |Rc| bmrev |
303 uint_xlen_t bmset(RA, RB, sh)
305 int shamt = RB & (XLEN - 1);
307 return RA | (mask << shamt);
310 uint_xlen_t bmclr(RA, RB, sh)
312 int shamt = RB & (XLEN - 1);
314 return RA & ~(mask << shamt);
317 uint_xlen_t bminv(RA, RB, sh)
319 int shamt = RB & (XLEN - 1);
321 return RA ^ (mask << shamt);
324 uint_xlen_t bmext(RA, RB, sh)
326 int shamt = RB & (XLEN - 1);
328 return mask & (RA >> shamt);
332 bitmask extract with reverse. can be done by bitinverting all of RA and getting bits of RA from the opposite end.
336 rev[0:msb] = ra[msb:0];
339 uint_xlen_t bmextrev(RA, RB, sh)
341 int shamt = (RB & (XLEN - 1));
342 shamt = (XLEN-1)-shamt; # shift other end
343 bra = bitreverse(RA) # swap LSB-MSB
345 return mask & (bra >> shamt);
349 | 0.5|6.10|11.15|16.20|21.26| 27..30 |31| name |
350 | -- | -- | --- | --- | --- | ------- |--| ------ |
351 | NN | RT | RA | RB | sh | 0 111 |Rc| bmrevi |
360 uint64_t grev64(uint64_t RA, uint64_t RB)
364 if (shamt & 1) x = ((x & 0x5555555555555555LL) << 1) |
365 ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
366 if (shamt & 2) x = ((x & 0x3333333333333333LL) << 2) |
367 ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
368 if (shamt & 4) x = ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
369 ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
370 if (shamt & 8) x = ((x & 0x00FF00FF00FF00FFLL) << 8) |
371 ((x & 0xFF00FF00FF00FF00LL) >> 8);
372 if (shamt & 16) x = ((x & 0x0000FFFF0000FFFFLL) << 16) |
373 ((x & 0xFFFF0000FFFF0000LL) >> 16);
374 if (shamt & 32) x = ((x & 0x00000000FFFFFFFFLL) << 32) |
375 ((x & 0xFFFFFFFF00000000LL) >> 32);
381 # shuffle / unshuffle
386 uint32_t shfl32(uint32_t RA, uint32_t RB)
390 if (shamt & 8) x = shuffle32_stage(x, 0x00ff0000, 0x0000ff00, 8);
391 if (shamt & 4) x = shuffle32_stage(x, 0x0f000f00, 0x00f000f0, 4);
392 if (shamt & 2) x = shuffle32_stage(x, 0x30303030, 0x0c0c0c0c, 2);
393 if (shamt & 1) x = shuffle32_stage(x, 0x44444444, 0x22222222, 1);
396 uint32_t unshfl32(uint32_t RA, uint32_t RB)
400 if (shamt & 1) x = shuffle32_stage(x, 0x44444444, 0x22222222, 1);
401 if (shamt & 2) x = shuffle32_stage(x, 0x30303030, 0x0c0c0c0c, 2);
402 if (shamt & 4) x = shuffle32_stage(x, 0x0f000f00, 0x00f000f0, 4);
403 if (shamt & 8) x = shuffle32_stage(x, 0x00ff0000, 0x0000ff00, 8);
407 uint64_t shuffle64_stage(uint64_t src, uint64_t maskL, uint64_t maskR, int N)
409 uint64_t x = src & ~(maskL | maskR);
410 x |= ((src << N) & maskL) | ((src >> N) & maskR);
413 uint64_t shfl64(uint64_t RA, uint64_t RB)
417 if (shamt & 16) x = shuffle64_stage(x, 0x0000ffff00000000LL,
418 0x00000000ffff0000LL, 16);
419 if (shamt & 8) x = shuffle64_stage(x, 0x00ff000000ff0000LL,
420 0x0000ff000000ff00LL, 8);
421 if (shamt & 4) x = shuffle64_stage(x, 0x0f000f000f000f00LL,
422 0x00f000f000f000f0LL, 4);
423 if (shamt & 2) x = shuffle64_stage(x, 0x3030303030303030LL,
424 0x0c0c0c0c0c0c0c0cLL, 2);
425 if (shamt & 1) x = shuffle64_stage(x, 0x4444444444444444LL,
426 0x2222222222222222LL, 1);
429 uint64_t unshfl64(uint64_t RA, uint64_t RB)
433 if (shamt & 1) x = shuffle64_stage(x, 0x4444444444444444LL,
434 0x2222222222222222LL, 1);
435 if (shamt & 2) x = shuffle64_stage(x, 0x3030303030303030LL,
436 0x0c0c0c0c0c0c0c0cLL, 2);
437 if (shamt & 4) x = shuffle64_stage(x, 0x0f000f000f000f00LL,
438 0x00f000f000f000f0LL, 4);
439 if (shamt & 8) x = shuffle64_stage(x, 0x00ff000000ff0000LL,
440 0x0000ff000000ff00LL, 8);
441 if (shamt & 16) x = shuffle64_stage(x, 0x0000ffff00000000LL,
442 0x00000000ffff0000LL, 16);
452 uint_xlen_t xperm(uint_xlen_t RA, uint_xlen_t RB, int sz_log2)
455 uint_xlen_t sz = 1LL << sz_log2;
456 uint_xlen_t mask = (1LL << sz) - 1;
457 for (int i = 0; i < XLEN; i += sz) {
458 uint_xlen_t pos = ((RB >> i) & mask) << sz_log2;
460 r |= ((RA >> pos) & mask) << i;
464 uint_xlen_t xperm_n (uint_xlen_t RA, uint_xlen_t RB)
465 { return xperm(RA, RB, 2); }
466 uint_xlen_t xperm_b (uint_xlen_t RA, uint_xlen_t RB)
467 { return xperm(RA, RB, 3); }
468 uint_xlen_t xperm_h (uint_xlen_t RA, uint_xlen_t RB)
469 { return xperm(RA, RB, 4); }
470 uint_xlen_t xperm_w (uint_xlen_t RA, uint_xlen_t RB)
471 { return xperm(RA, RB, 5); }
479 uint32_t gorc32(uint32_t RA, uint32_t RB)
483 if (shamt & 1) x |= ((x & 0x55555555) << 1) | ((x & 0xAAAAAAAA) >> 1);
484 if (shamt & 2) x |= ((x & 0x33333333) << 2) | ((x & 0xCCCCCCCC) >> 2);
485 if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4) | ((x & 0xF0F0F0F0) >> 4);
486 if (shamt & 8) x |= ((x & 0x00FF00FF) << 8) | ((x & 0xFF00FF00) >> 8);
487 if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16);
490 uint64_t gorc64(uint64_t RA, uint64_t RB)
494 if (shamt & 1) x |= ((x & 0x5555555555555555LL) << 1) |
495 ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
496 if (shamt & 2) x |= ((x & 0x3333333333333333LL) << 2) |
497 ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
498 if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
499 ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
500 if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL) << 8) |
501 ((x & 0xFF00FF00FF00FF00LL) >> 8);
502 if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL) << 16) |
503 ((x & 0xFFFF0000FFFF0000LL) >> 16);
504 if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL) << 32) |
505 ((x & 0xFFFFFFFF00000000LL) >> 32);
513 based on RV bitmanip, covered by ternary bitops
516 uint_xlen_t cmix(uint_xlen_t RA, uint_xlen_t RB, uint_xlen_t RC) {
517 return (RA & RB) | (RC & ~RB);
524 see https://en.wikipedia.org/wiki/CLMUL_instruction_set
527 uint_xlen_t clmul(uint_xlen_t RA, uint_xlen_t RB)
530 for (int i = 0; i < XLEN; i++)
535 uint_xlen_t clmulh(uint_xlen_t RA, uint_xlen_t RB)
538 for (int i = 1; i < XLEN; i++)
543 uint_xlen_t clmulr(uint_xlen_t RA, uint_xlen_t RB)
546 for (int i = 0; i < XLEN; i++)
548 x ^= RA >> (XLEN-i-1);
554 see <https://courses.csail.mit.edu/6.857/2016/files/ffield.py>
558 this requires 3 parameters and a "degree"
560 RT = GFMUL(RA, RB, gfdegree, modulo=RC)
562 realistically with the degree also needing to be an immediate it should be brought down to an overwrite version:
564 RS = GFMUL(RS, RA, gfdegree, modulo=RB)
565 RS = GFMUL(RS, RA, gfdegree=RC, modulo=RB)
567 | 0.5|6.10|11.15|16.20|21.25| 26..30 |31|
568 | -- | -- | --- | --- | --- | ------- |--|
569 | NN | RS | RA | RB | deg | 00 011 |Rc|
570 | NN | RS | RA | RB | RC | 11 011 |Rc|
572 where the SimpleV variant may override RS-as-src differently from RS-as-dest
577 from functools import reduce
579 # constants used in the multGF2 function
580 mask1 = mask2 = polyred = None
582 def setGF2(degree, irPoly):
583 """Define parameters of binary finite field GF(2^m)/g(x)
584 - degree: extension degree of binary field
585 - irPoly: coefficients of irreducible polynomial g(x)
588 """Convert an integer into a polynomial"""
589 return [(sInt >> i) & 1
590 for i in reversed(range(sInt.bit_length()))]
592 global mask1, mask2, polyred
593 mask1 = mask2 = 1 << degree
595 polyred = reduce(lambda x, y: (x << 1) + y, i2P(irPoly)[1:])
598 """Multiply two polynomials in GF(2^m)/g(x)"""
609 if __name__ == "__main__":
611 # Define binary field GF(2^3)/x^3 + x + 1
614 # Evaluate the product (x^2 + x + 1)(x^2 + 1)
615 print("{:02x}".format(multGF2(0b111, 0b101)))
617 # Define binary field GF(2^8)/x^8 + x^4 + x^3 + x + 1
618 # (used in the Advanced Encryption Standard-AES)
619 setGF2(8, 0b100011011)
621 # Evaluate the product (x^7)(x^7 + x + 1)
622 print("{:02x}".format(multGF2(0b10000000, 0b10000011)))
626 RS = GFADDI(RS, RA|0, gfdegree, modulo=RB)
627 RS = GFADD(RS, RA|0, gfdegree=RC, modulo=RB)
629 | 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name |
630 | -- | -- | --- | --- | --- | ------- |--| ----- |
631 | NN | RS | RA | RB | deg | 0 1 011 |Rc| gfaddi |
632 | NN | RS | RA | RB | RC | 1 1 111 |Rc| gfadd |
634 GFMOD is a pseudo-op where RA=0
647 def gf_invert(a, mod=0x1B) :
662 a %= 256 # Emulating 8-bit overflow
663 g1 %= 256 # Emulating 8-bit overflow
665 j = gf_degree(a) - gf_degree(v)
673 uint64_t bmatflip(uint64_t RA)
681 uint64_t bmatxor(uint64_t RA, uint64_t RB)
684 uint64_t RBt = bmatflip(RB);
685 uint8_t u[8]; // rows of RA
686 uint8_t v[8]; // cols of RB
687 for (int i = 0; i < 8; i++) {
692 for (int i = 0; i < 64; i++) {
693 if (pcnt(u[i / 8] & v[i % 8]) & 1)
698 uint64_t bmator(uint64_t RA, uint64_t RB)
701 uint64_t RBt = bmatflip(RB);
702 uint8_t u[8]; // rows of RA
703 uint8_t v[8]; // cols of RB
704 for (int i = 0; i < 8; i++) {
709 for (int i = 0; i < 64; i++) {
710 if ((u[i / 8] & v[i % 8]) != 0)