7 * ternlogi <https://bugs.libre-soc.org/show_bug.cgi?id=745>
8 * grev <https://bugs.libre-soc.org/show_bug.cgi?id=755>
9 * GF2^M <https://bugs.libre-soc.org/show_bug.cgi?id=782>
16 pseudocode: [[openpower/isa/bitmanip]]
18 this extension amalgamates bitmanipulation primitives from many sources,
19 including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX.
20 Also included are DSP/Multimedia operations suitable for Audio/Video.
21 Vectorisation and SIMD are removed: these are straight scalar (element)
22 operations making them suitable for embedded applications. Vectorisation
23 Context is provided by [[openpower/sv]].
25 When combined with SV, scalar variants of bitmanip operations found in
26 VSX are added so that the Packed SIMD aspects of VSX may be retired as
27 "legacy" in the far future (10 to 20 years). Also, VSX is hundreds of
28 opcodes, requires 128 bit pathways, and is wholly unsuited to low power
29 or embedded scenarios.
31 ternlogv is experimental and is the only operation that may be considered
32 a "Packed SIMD". It is added as a variant of the already well-justified
33 ternlog operation (done in AVX512 as an immediate only) "because it
34 looks fun". As it is based on the LUT4 concept it will allow accelerated
35 emulation of FPGAs. Other vendors of ISAs are buying FPGA companies to
36 achieve similar objectives.
38 general-purpose Galois Field 2^M operations are added so as to avoid
39 huge custom opcode proliferation across many areas of Computer Science.
40 however for convenience and also to avoid setup costs, some of the more
41 common operations (clmul, crc32) are also added. The expectation is
42 that these operations would all be covered by the same pipeline.
44 note that there are brownfield spaces below that could incorporate
45 some of the set-before-first and other scalar operations listed in
47 [[sv/vector_ops]], [[sv/int_fp_mv]] and the [[sv/av_opcodes]] as well as
48 [[sv/setvl]], [[sv/svstep]], [[sv/remap]]
52 * <https://en.wikiversity.org/wiki/Reed%E2%80%93Solomon_codes_for_coders>
53 * <https://maths-people.anu.edu.au/~brent/pd/rpb232tr.pdf>
57 two major opcodes are needed
59 ternlog has its own major opcode
61 | 29.30 |31| name | Form |
62 | ------ |--| --------- | ---- |
63 | 0 0 |Rc| ternlogi | TLI-Form |
64 | 0 1 | | crternlogi | TLI-Form |
65 | 1 iv | | grevlogi | TLI-Form |
67 2nd major opcode for other bitmanip: minor opcode allocation
70 | ------ |--| --------- |
72 | -00 |1 | binary lut |
74 | -01 |1 | swizzle mv/fmv |
83 | dest | src1 | subop | op |
84 | ---- | ---- | ----- | -------- |
85 | RT | RA | .. | bmatflip |
89 | dest | src1 | src2 | subop | op |
90 | ---- | ---- | ---- | ----- | -------- |
91 | RT | RA | RB | or | bmatflip |
92 | RT | RA | RB | xor | bmatflip |
93 | RT | RA | RB | | grev |
94 | RT | RA | RB | | clmul\* |
95 | RT | RA | RB | | gorc |
96 | RT | RA | RB | shuf | shuffle |
97 | RT | RA | RB | unshuf| shuffle |
98 | RT | RA | RB | width | xperm |
99 | RT | RA | RB | type | av minmax |
100 | RT | RA | RB | | av abs avgadd |
101 | RT | RA | RB | type | vmask ops |
102 | RT | RA | RB | type | abs accumulate (overwrite) |
110 TODO: convert all instructions to use RT and not RS
112 | 0.5|6.10|11.15|16.20 |21..25 | 26....30 |31| name | Form |
113 | -- | -- | --- | --- | ----- | -------- |--| ------ | -------- |
114 | NN | RT | RA |itype/| im0-4 | im5-7 00 |0 | xpermi | TLI-Form |
115 | NN | RT | RA | RB | RC | nh 00 00 |1 | binlut | VA-Form |
116 | NN | RT | RA | RB | /BFA/ | 0 01 00 |1 | bincrflut | VA-Form |
117 | NN | | | | | 1 01 00 |1 | svindex | SVI-Form |
118 | NN | RT | RA | RB | mode | L 10 00 |1 | bmask | BM2-Form |
119 | NN | | | | | 0 11 00 |1 | svshape | SVM-Form |
120 | NN | | | | | 1 11 00 |1 | svremap | SVRM-Form |
121 | NN | RT | RA | RB | im0-4 | im5-7 01 |0 | grevlog | TLI-Form |
122 | NN | RT | RA | RB | im0-4 | im5-7 01 |1 | grevlogw | TLI-Form |
123 | NN | RT | RA | RB | RC | mode 010 |Rc| bitmask\* | VA2-Form |
124 | NN |FRS | d1 | d0 | d0 | 00 011 |d2| fmvis | DX-Form |
125 | NN |FRS | d1 | d0 | d0 | 01 011 |d2| fishmv | DX-Form |
126 | NN | | | | | 10 011 |Rc| svstep | SVL-Form |
127 | NN | | | | | 11 011 |Rc| setvl | SVL-Form |
128 | NN | | | | | ---- 110 | | 1/2 ops | other table [1] |
129 | NN | RT | RA | RB | RC | 11 110 |Rc| bmrev | VA2-Form |
130 | NN | RT | RA | RB | sh0-4 | sh5 1 111 |Rc| bmrevi | MDS-Form |
134 ops (note that av avg and abs as well as vec scalar mask
135 are included here [[sv/vector_ops]], and
136 the [[sv/av_opcodes]])
138 | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name | Form |
139 | -- | -- | --- | --- | -- | ----- | -------- |--| ---- | ------- |
140 | NN | RS | me | sh | SH | ME 0 | nn00 110 |Rc| bmopsi | BM-Form |
141 | NN | RS | RA | sh | SH | 0 1 | nn00 110 |Rc| bmopsi | XB-Form |
142 | NN | RS | RA |im04 | im5| 1 1 | im67 00 110 |Rc| bmatxori | TODO |
143 | NN | RT | RA | RB | 1 | 00 | 0001 110 |Rc| cldiv | X-Form |
144 | NN | RT | RA | RB | 1 | 01 | 0001 110 |Rc| clmod | X-Form |
145 | NN | RT | RA | | 1 | 10 | 0001 110 |Rc| clmulh | X-Form |
146 | NN | RT | RA | RB | 1 | 11 | 0001 110 |Rc| clmul | X-Form |
147 | NN | RT | RA | RB | 0 | 00 | 0001 110 |Rc| rsvd | |
148 | NN | RT | RA | RB | 0 | 01 | 0001 110 |Rc| rsvd | |
149 | NN | RT | RA | RB | 0 | 10 | 0001 110 |Rc| rsvd | |
150 | NN | RT | RA | RB | 0 | 11 | 0001 110 |Rc| vec cprop | X-Form |
151 | NN | | | | | 00 | 0101 110 |0 | crfbinlog | {TODO} |
152 | NN | | | | | 00 | 0101 110 |1 | rsvd | |
153 | NN | | | | | 10 | 0101 110 |Rc| rsvd | |
154 | NN | | | | | -1 | 0101 110 |Rc| rsvd | |
155 | NN | RT | RA | RB | 0 | itype | 1001 110 |Rc| av minmax | X-Form |
156 | NN | RT | RA | RB | 1 | 00 | 1001 110 |Rc| av abss | X-Form |
157 | NN | RT | RA | RB | 1 | 01 | 1001 110 |Rc| av absu | X-Form |
158 | NN | RT | RA | RB | 1 | 10 | 1001 110 |Rc| av avgadd | X-Form |
159 | NN | RT | RA | RB | 1 | 11 | 1001 110 |Rc| grevlutr | X-Form |
160 | NN | RT | RA | RB | 0 | itype | 1101 110 |Rc| shadd | X-Form |
161 | NN | RT | RA | RB | 1 | itype | 1101 110 |Rc| shadduw | X-Form |
162 | NN | RT | RA | RB | 0 | 00 | 0010 110 |Rc| rsvd | |
163 | NN | RS | RA | sh | SH | 00 | 1010 110 |Rc| rsvd | |
164 | NN | RT | RA | RB | 0 | 00 | 0110 110 |Rc| rsvd | |
165 | NN | RS | RA | SH | 0 | 00 | 1110 110 |Rc| rsvd | |
166 | NN | RT | RA | RB | 1 | 00 | 1110 110 |Rc| absds | X-Form |
167 | NN | RT | RA | RB | 0 | 01 | 0010 110 |Rc| rsvd | |
168 | NN | RT | RA | RB | 1 | 01 | 0010 110 |Rc| clmulr | X-Form |
169 | NN | RS | RA | sh | SH | 01 | 1010 110 |Rc| rsvd | |
170 | NN | RT | RA | RB | 0 | 01 | 0110 110 |Rc| rsvd | |
171 | NN | RS | RA | SH | 0 | 01 | 1110 110 |Rc| rsvd | |
172 | NN | RT | RA | RB | 1 | 01 | 1110 110 |Rc| absdu | X-Form |
173 | NN | RS | RA | RB | 0 | 10 | 0010 110 |Rc| bmator | X-Form |
174 | NN | RS | RA | RB | 0 | 10 | 0110 110 |Rc| bmatand | X-Form |
175 | NN | RS | RA | RB | 0 | 10 | 1010 110 |Rc| bmatxor | X-Form |
176 | NN | RS | RA | RB | 0 | 10 | 1110 110 |Rc| bmatflip | X-Form |
177 | NN | RT | RA | RB | 1 | 10 | 0010 110 |Rc| xpermn | X-Form |
178 | NN | RT | RA | RB | 1 | 10 | 0110 110 |Rc| xpermb | X-Form |
179 | NN | RT | RA | RB | 1 | 10 | 1010 110 |Rc| xpermh | X-Form |
180 | NN | RT | RA | RB | 1 | 10 | 1110 110 |Rc| xpermw | X-Form |
181 | NN | RT | RA | RB | 0 | 11 | 1110 110 |Rc| absdacs | X-Form |
182 | NN | RT | RA | RB | 1 | 11 | 1110 110 |Rc| absdacu | X-Form |
183 | NN | | | | | | --11 110 |Rc| bmrev | VA2-Form |
185 # binary and ternary bitops
187 Similar to FPGA LUTs: for two (binary) or three (ternary) inputs take
188 bits from each input, concatenate them and perform a lookup into a
189 table using an 8-8-bit immediate (for the ternary instructions), or in
190 another register (4-bit for the binary instructions). The binary lookup
191 instructions have CR Field lookup variants due to CR Fields being 4 bit.
194 [vpternlogd/vpternlogq](https://www.felixcloutier.com/x86/vpternlogd:vpternlogq)
199 | 0.5|6.10|11.15|16.20| 21..28|29.30|31|
200 | -- | -- | --- | --- | ----- | --- |--|
201 | NN | RT | RA | RB | im0-7 | 00 |Rc|
204 idx = c << 2 | b << 1 | a
205 return imm[idx] # idx by LSB0 order
208 RT[i] = lut3(imm, RB[i], RA[i], RT[i])
212 Binary lookup is a dynamic LUT2 version of ternlogi. Firstly, the
213 lookup table is 4 bits wide not 8 bits, and secondly the lookup
214 table comes from a register not an immediate.
216 | 0.5|6.10|11.15|16.20| 21..25|26..31 | Form |
217 | -- | -- | --- | --- | ----- |--------|---------|
218 | NN | RT | RA | RB | RC |nh 00001| VA-Form |
219 | NN | RT | RA | RB | /BFA/ |0 01001| VA-Form |
221 For binlut, the 4-bit LUT may be selected from either the high nibble
222 or the low nibble of the first byte of RC:
226 return imm[idx] # idx by LSB0 order
228 imm = (RC>>(nh*4))&0b1111
230 RT[i] = lut2(imm, RB[i], RA[i])
232 For bincrlut, `BFA` selects the 4-bit CR Field as the LUT2:
235 RT[i] = lut2(CRs{BFA}, RB[i], RA[i])
237 When Vectorised with SVP64, as usual both source and destination may be
240 *Programmer's note: a dynamic ternary lookup may be synthesised from
241 a pair of `binlut` instructions followed by a `ternlogi` to select which
242 to merge. Use `nh` to select which nibble to use as the lookup table
243 from the RC source register (`nh=1` nibble high), i.e. keeping
244 an 8-bit LUT3 in RC, the first `binlut` instruction may set nh=0 and
249 another mode selection would be CRs not Ints.
251 | 0.5|6.8 | 9.11|12.14|15.17|18.20|21.28 | 29.30|31|
252 | -- | -- | --- | --- | --- |-----|----- | -----|--|
253 | NN | BT | BA | BB | BC |m0-2 | imm | 01 |m3|
257 a,b,c = CRs[BA][i], CRs[BB][i], CRs[BC][i])
258 if mask[i] CRs[BT][i] = lut3(imm, a, b, c)
260 This instruction is remarkably similar to the existing crops, `crand` etc.
261 which have been noted to be a 4-bit (binary) LUT. In effect `crternlogi`
262 is the ternary LUT version of crops, having an 8-bit LUT.
266 With ternary (LUT3) dynamic instructions being very costly,
267 and CR Fields being only 4 bit, a binary (LUT2) variant is better
269 | 0.5|6.8 | 9.11|12.14|15.17|18.21|22...30 |31|
270 | -- | -- | --- | --- | --- |-----| -------- |--|
271 | NN | BT | BA | BB | BC |m0-m3|000101110 |0 |
275 a,b = CRs[BA][i], CRs[BB][i])
276 if mask[i] CRs[BT][i] = lut2(CRs[BC], a, b)
278 When SVP64 Vectorised any of the 4 operands may be Scalar or
279 Vector, including `BC` meaning that multiple different dynamic
280 lookups may be performed with a single instruction.
282 *Programmer's note: just as with binlut and ternlogi, a pair
283 of crbinlog instructions followed by a merging crternlogi may
284 be deployed to synthesise dynamic ternary (LUT3) CR Field
291 required for the [[sv/av_opcodes]]
293 signed and unsigned min/max for integer. this is sort-of partly
294 synthesiseable in [[sv/svp64]] with pred-result as long as the dest reg
295 is one of the sources, but not both signed and unsigned. when the dest
296 is also one of the srces and the mv fails due to the CR bittest failing
297 this will only overwrite the dest where the src is greater (or less).
299 signed/unsigned min/max gives more flexibility.
303 * XO=0001001110, itype=0b00 min, unsigned
304 * XO=0101001110, itype=0b01 min, signed
305 * XO=0011001110, itype=0b10 max, unsigned
306 * XO=0111001110, itype=0b11 max, signed
310 uint_xlen_t mins(uint_xlen_t rs1, uint_xlen_t rs2)
311 { return (int_xlen_t)rs1 < (int_xlen_t)rs2 ? rs1 : rs2;
313 uint_xlen_t maxs(uint_xlen_t rs1, uint_xlen_t rs2)
314 { return (int_xlen_t)rs1 > (int_xlen_t)rs2 ? rs1 : rs2;
316 uint_xlen_t minu(uint_xlen_t rs1, uint_xlen_t rs2)
317 { return rs1 < rs2 ? rs1 : rs2;
319 uint_xlen_t maxu(uint_xlen_t rs1, uint_xlen_t rs2)
320 { return rs1 > rs2 ? rs1 : rs2;
326 required for the [[sv/av_opcodes]], these exist in Packed SIMD (VSX)
330 uint_xlen_t intavg(uint_xlen_t rs1, uint_xlen_t rs2) {
331 return (rs1 + rs2 + 1) >> 1:
337 required for the [[sv/av_opcodes]], these exist in Packed SIMD (VSX)
341 uint_xlen_t absdu(uint_xlen_t rs1, uint_xlen_t rs2) {
342 return (src1 > src2) ? (src1-src2) : (src2-src1)
348 required for the [[sv/av_opcodes]], these are needed for motion estimation.
349 both are overwrite on RS.
352 uint_xlen_t uintabsacc(uint_xlen_t rs, uint_xlen_t ra, uint_xlen_t rb) {
353 return rs + (src1 > src2) ? (src1-src2) : (src2-src1)
355 uint_xlen_t intabsacc(uint_xlen_t rs, int_xlen_t ra, int_xlen_t rb) {
356 return rs + (src1 > src2) ? (src1-src2) : (src2-src1)
360 For SVP64, the twin Elwidths allows e.g. a 16 bit accumulator for 8 bit
361 differences. Form is `RM-1P-3S1D` where RS-as-source has a separate
362 SVP64 designation from RS-as-dest. This gives a limited range of
363 non-overwrite capability.
367 Power ISA is missing LD/ST with shift, which is present in both ARM and x86.
368 Too complex to add more LD/ST, a compromise is to add shift-and-add.
369 Replaces a pair of explicit instructions in hot-loops.
372 uint_xlen_t shadd(uint_xlen_t rs1, uint_xlen_t rs2, uint8_t sh) {
373 return (rs1 << (sh+1)) + rs2;
376 uint_xlen_t shadduw(uint_xlen_t rs1, uint_xlen_t rs2, uint8_t sh) {
377 uint_xlen_t rs1z = rs1 & 0xFFFFFFFF;
378 return (rs1z << (sh+1)) + rs2;
384 based on RV bitmanip singlebit set, instruction format similar to shift
385 [[isa/fixedshift]]. bmext is actually covered already (shift-with-mask
386 rldicl but only immediate version). however bitmask-invert is not,
387 and set/clr are not covered, although they can use the same Shift ALU.
389 bmext (RB) version is not the same as rldicl because bmext is a right
390 shift by RC, where rldicl is a left rotate. for the immediate version
391 this does not matter, so a bmexti is not required. bmrev however there
392 is no direct equivalent and consequently a bmrevi is required.
394 bmset (register for mask amount) is particularly useful for creating
395 predicate masks where the length is a dynamic runtime quantity.
396 bmset(RA=0, RB=0, RC=mask) will produce a run of ones of length "mask"
397 in a single instruction without needing to initialise or depend on any
400 | 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name |
401 | -- | -- | --- | --- | --- | ------- |--| ----- |
402 | NN | RS | RA | RB | RC | mode 010 |Rc| bm\* |
404 Immediate-variant is an overwrite form:
406 | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name |
407 | -- | -- | --- | --- | -- | ----- | -------- |--| ---- |
408 | NN | RS | RB | sh | SH | itype | 1000 110 |Rc| bm\*i |
414 mask_a = ((1 << x) - 1) & ((1 << 64) - 1)
415 mask_b = ((1 << y) - 1) & ((1 << 64) - 1)
420 mask_a = ((1 << x) - 1) & ((1 << 64) - 1)
421 mask_b = (~((1 << y) - 1)) & ((1 << 64) - 1)
422 return mask_a ^ mask_b
425 uint_xlen_t bmset(RS, RB, sh)
427 int shamt = RB & (XLEN - 1);
429 return RS | (mask << shamt);
432 uint_xlen_t bmclr(RS, RB, sh)
434 int shamt = RB & (XLEN - 1);
436 return RS & ~(mask << shamt);
439 uint_xlen_t bminv(RS, RB, sh)
441 int shamt = RB & (XLEN - 1);
443 return RS ^ (mask << shamt);
446 uint_xlen_t bmext(RS, RB, sh)
448 int shamt = RB & (XLEN - 1);
450 return mask & (RS >> shamt);
454 bitmask extract with reverse. can be done by bit-order-inverting all
455 of RB and getting bits of RB from the opposite end.
457 when RA is zero, no shift occurs. this makes bmextrev useful for
458 simply reversing all bits of a register.
462 rev[0:msb] = rb[msb:0];
465 uint_xlen_t bmrevi(RA, RB, sh)
468 if (RA != 0) shamt = (GPR(RA) & (XLEN - 1));
469 shamt = (XLEN-1)-shamt; # shift other end
470 brb = bitreverse(GPR(RB)) # swap LSB-MSB
472 return mask & (brb >> shamt);
475 uint_xlen_t bmrev(RA, RB, RC) {
476 return bmrevi(RA, RB, GPR(RC) & 0b111111);
480 | 0.5|6.10|11.15|16.20|21.26| 27..30 |31| name | Form |
481 | -- | -- | --- | --- | --- | ------- |--| ------ | -------- |
482 | NN | RT | RA | RB | sh | 1111 |Rc| bmrevi | MDS-Form |
484 | 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name | Form |
485 | -- | -- | --- | --- | --- | ------- |--| ------ | -------- |
486 | NN | RT | RA | RB | RC | 11110 |Rc| bmrev | VA2-Form |
488 # grevlut <a name="grevlut"> </a>
490 ([3x lower latency alternative](grev_gorc_design/) which is
491 not equivalent and has limited constant-generation capability)
493 generalised reverse combined with a pair of LUT2s and allowing
494 a constant `0b0101...0101` when RA=0, and an option to invert
495 (including when RA=0, giving a constant 0b1010...1010 as the
496 initial value) provides a wide range of instructions
497 and a means to set hundreds of regular 64 bit patterns with one
498 single 32 bit instruction.
500 the two LUT2s are applied left-half (when not swapping)
501 and right-half (when swapping) so as to allow a wider
504 <img src="/openpower/sv/grevlut2x2.jpg" width=700 />
506 * A value of `0b11001010` for the immediate provides
507 the functionality of a standard "grev".
508 * `0b11101110` provides gorc
510 grevlut should be arranged so as to produce the constants
511 needed to put into bext (bitextract) so as in turn to
512 be able to emulate x86 pmovmask instructions
513 <https://www.felixcloutier.com/x86/pmovmskb>.
514 This only requires 2 instructions (grevlut, bext).
516 Note that if the mask is required to be placed
517 directly into CR Fields (for use as CR Predicate
518 masks rather than a integer mask) then sv.cmpi or sv.ori
519 may be used instead, bearing in mind that sv.ori
520 is a 64-bit instruction, and `VL` must have been
521 set to the required length:
523 sv.ori./elwid=8 r10.v, r10.v, 0
525 The following settings provide the required mask constants:
527 | RA=0 | RB | imm | iv | result |
528 | ------- | ------- | ---------- | -- | ---------- |
529 | 0x555.. | 0b10 | 0b01101100 | 0 | 0x111111... |
530 | 0x555.. | 0b110 | 0b01101100 | 0 | 0x010101... |
531 | 0x555.. | 0b1110 | 0b01101100 | 0 | 0x00010001... |
532 | 0x555.. | 0b10 | 0b11000110 | 1 | 0x88888... |
533 | 0x555.. | 0b110 | 0b11000110 | 1 | 0x808080... |
534 | 0x555.. | 0b1110 | 0b11000110 | 1 | 0x80008000... |
536 Better diagram showing the correct ordering of shamt (RB). A LUT2
537 is applied to all locations marked in red using the first 4
538 bits of the immediate, and a separate LUT2 applied to all
539 locations in green using the upper 4 bits of the immediate.
541 <img src="/openpower/sv/grevlut.png" width=700 />
543 demo code [[openpower/sv/grevlut.py]]
548 return imm[idx] # idx by LSB0 order
550 dorow(imm8, step_i, chunksize, us32b):
551 for j in 0 to 31 if is32b else 63:
552 if (j&chunk_size) == 0
556 step_o[j] = lut2(imm, step_i[j], step_i[j ^ chunk_size])
559 uint64_t grevlut(uint64_t RA, uint64_t RB, uint8 imm, bool iv, bool is32b)
561 uint64_t x = 0x5555_5555_5555_5555;
562 if (RA != 0) x = GPR(RA);
564 int shamt = RB & 31 if is32b else 63
565 for i in 0 to (6-is32b)
567 if (shamt & step) x = dorow(imm, x, step, is32b)
572 A variant may specify different LUT-pairs per row,
573 using one byte of RB for each. If it is desired that
574 a particular row-crossover shall not be applied it is
575 a simple matter to set the appropriate LUT-pair in RB
576 to effect an identity transform for that row (`0b11001010`).
579 uint64_t grevlutr(uint64_t RA, uint64_t RB, bool iv, bool is32b)
581 uint64_t x = 0x5555_5555_5555_5555;
582 if (RA != 0) x = GPR(RA);
584 for i in 0 to (6-is32b)
586 imm = (RB>>(i*8))&0xff
587 x = dorow(imm, x, step, is32b)
593 | 0.5|6.10|11.15|16.20 |21..28 | 29.30|31| name | Form |
594 | -- | -- | --- | --- | ----- | -----|--| ------ | ----- |
595 | NN | RT | RA | s0-4 | im0-7 | 1 iv |s5| grevlogi | |
596 | NN | RT | RA | RB | im0-7 | 01 |0 | grevlog | |
597 | NN | RT | RA | RB | im0-7 | 01 |1 | grevlogw | |
601 based on RV bitmanip.
603 RA contains a vector of indices to select parts of RB to be
604 copied to RT. The immediate-variant allows up to an 8 bit
605 pattern (repeated) to be targetted at different parts of RT.
607 xperm shares some similarity with one of the uses of bmator
608 in that xperm indices are binary addressing where bitmator
609 may be considered to be unary addressing.
612 uint_xlen_t xpermi(uint8_t imm8, uint_xlen_t RB, int sz_log2)
615 uint_xlen_t sz = 1LL << sz_log2;
616 uint_xlen_t mask = (1LL << sz) - 1;
617 uint_xlen_t RA = imm8 | imm8<<8 | ... | imm8<<56;
618 for (int i = 0; i < XLEN; i += sz) {
619 uint_xlen_t pos = ((RA >> i) & mask) << sz_log2;
621 r |= ((RB >> pos) & mask) << i;
625 uint_xlen_t xperm(uint_xlen_t RA, uint_xlen_t RB, int sz_log2)
628 uint_xlen_t sz = 1LL << sz_log2;
629 uint_xlen_t mask = (1LL << sz) - 1;
630 for (int i = 0; i < XLEN; i += sz) {
631 uint_xlen_t pos = ((RA >> i) & mask) << sz_log2;
633 r |= ((RB >> pos) & mask) << i;
637 uint_xlen_t xperm_n (uint_xlen_t RA, uint_xlen_t RB)
638 { return xperm(RA, RB, 2); }
639 uint_xlen_t xperm_b (uint_xlen_t RA, uint_xlen_t RB)
640 { return xperm(RA, RB, 3); }
641 uint_xlen_t xperm_h (uint_xlen_t RA, uint_xlen_t RB)
642 { return xperm(RA, RB, 4); }
643 uint_xlen_t xperm_w (uint_xlen_t RA, uint_xlen_t RB)
644 { return xperm(RA, RB, 5); }
649 bmatflip and bmatxor is found in the Cray XMT, and in x86 is known
650 as GF2P8AFFINEQB. uses:
652 * <https://gist.github.com/animetosho/d3ca95da2131b5813e16b5bb1b137ca0>
653 * SM4, Reed Solomon, RAID6
654 <https://stackoverflow.com/questions/59124720/what-are-the-avx-512-galois-field-related-instructions-for>
655 * Vector bit-reverse <https://reviews.llvm.org/D91515?id=305411>
656 * Affine Inverse <https://github.com/HJLebbink/asm-dude/wiki/GF2P8AFFINEINVQB>
658 | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name | Form |
659 | -- | -- | --- | --- | -- | ----- | -------- |--| ---- | ------- |
660 | NN | RS | RA |im04 | im5| 1 1 | im67 00 110 |Rc| bmatxori | TODO |
664 uint64_t bmatflip(uint64_t RA)
673 uint64_t bmatxori(uint64_t RS, uint64_t RA, uint8_t imm) {
675 uint64_t RAt = bmatflip(RA);
676 uint8_t u[8]; // rows of RS
677 uint8_t v[8]; // cols of RA
678 for (int i = 0; i < 8; i++) {
683 for (int i = 0; i < 64; i++) {
684 bit = (imm >> (i%8)) & 1;
685 bit ^= pcnt(u[i / 8] & v[i % 8]) & 1;
691 uint64_t bmatxor(uint64_t RA, uint64_t RB) {
692 return bmatxori(RA, RB, 0xff)
695 uint64_t bmator(uint64_t RA, uint64_t RB) {
697 uint64_t RBt = bmatflip(RB);
698 uint8_t u[8]; // rows of RA
699 uint8_t v[8]; // cols of RB
700 for (int i = 0; i < 8; i++) {
705 for (int i = 0; i < 64; i++) {
706 if ((u[i / 8] & v[i % 8]) != 0)
712 uint64_t bmatand(uint64_t RA, uint64_t RB) {
714 uint64_t RBt = bmatflip(RB);
715 uint8_t u[8]; // rows of RA
716 uint8_t v[8]; // cols of RB
717 for (int i = 0; i < 8; i++) {
722 for (int i = 0; i < 64; i++) {
723 if ((u[i / 8] & v[i % 8]) == 0xff)
730 # Introduction to Carry-less and GF arithmetic
732 * obligatory xkcd <https://xkcd.com/2595/>
734 There are three completely separate types of Galois-Field-based arithmetic
735 that we implement which are not well explained even in introductory
736 literature. A slightly oversimplified explanation is followed by more
737 accurate descriptions:
739 * `GF(2)` carry-less binary arithmetic. this is not actually a Galois Field,
740 but is accidentally referred to as GF(2) - see below as to why.
741 * `GF(p)` modulo arithmetic with a Prime number, these are "proper"
743 * `GF(2^N)` carry-less binary arithmetic with two limits: modulo a power-of-2
744 (2^N) and a second "reducing" polynomial (similar to a prime number), these
745 are said to be GF(2^N) arithmetic.
747 further detailed and more precise explanations are provided below
749 * **Polynomials with coefficients in `GF(2)`**
750 (aka. Carry-less arithmetic -- the `cl*` instructions).
751 This isn't actually a Galois Field, but its coefficients are. This is
752 basically binary integer addition, subtraction, and multiplication like
753 usual, except that carries aren't propagated at all, effectively turning
754 both addition and subtraction into the bitwise xor operation. Division and
755 remainder are defined to match how addition and multiplication works.
756 * **Galois Fields with a prime size**
757 (aka. `GF(p)` or Prime Galois Fields -- the `gfp*` instructions).
758 This is basically just the integers mod `p`.
759 * **Galois Fields with a power-of-a-prime size**
760 (aka. `GF(p^n)` or `GF(q)` where `q == p^n` for prime `p` and
762 We only implement these for `p == 2`, called Binary Galois Fields
763 (`GF(2^n)` -- the `gfb*` instructions).
764 For any prime `p`, `GF(p^n)` is implemented as polynomials with
765 coefficients in `GF(p)` and degree `< n`, where the polynomials are the
766 remainders of dividing by a specificly chosen polynomial in `GF(p)` called
767 the Reducing Polynomial (we will denote that by `red_poly`). The Reducing
768 Polynomial must be an irreducable polynomial (like primes, but for
769 polynomials), as well as have degree `n`. All `GF(p^n)` for the same `p`
770 and `n` are isomorphic to each other -- the choice of `red_poly` doesn't
771 affect `GF(p^n)`'s mathematical shape, all that changes is the specific
772 polynomials used to implement `GF(p^n)`.
774 Many implementations and much of the literature do not make a clear
775 distinction between these three categories, which makes it confusing
776 to understand what their purpose and value is.
778 * carry-less multiply is extremely common and is used for the ubiquitous
779 CRC32 algorithm. [TODO add many others, helps justify to ISA WG]
780 * GF(2^N) forms the basis of Rijndael (the current AES standard) and
781 has significant uses throughout cryptography
782 * GF(p) is the basis again of a significant quantity of algorithms
783 (TODO, list them, jacob knows what they are), even though the
784 modulo is limited to be below 64-bit (size of a scalar int)
786 # Instructions for Carry-less Operations
788 aka. Polynomials with coefficients in `GF(2)`
790 Carry-less addition/subtraction is simply XOR, so a `cladd`
791 instruction is not provided since the `xor[i]` instruction can be used instead.
793 These are operations on polynomials with coefficients in `GF(2)`, with the
794 polynomial's coefficients packed into integers with the following algorithm:
797 [[!inline pagenames="gf_reference/pack_poly.py" raw="yes"]]
800 ## Carry-less Multiply Instructions
803 see <https://en.wikipedia.org/wiki/CLMUL_instruction_set> and
804 <https://www.felixcloutier.com/x86/pclmulqdq> and
805 <https://en.m.wikipedia.org/wiki/Carry-less_product>
807 They are worth adding as their own non-overwrite operations
808 (in the same pipeline).
810 ### `clmul` Carry-less Multiply
813 [[!inline pagenames="gf_reference/clmul.py" raw="yes"]]
816 ### `clmulh` Carry-less Multiply High
819 [[!inline pagenames="gf_reference/clmulh.py" raw="yes"]]
822 ### `clmulr` Carry-less Multiply (Reversed)
824 Useful for CRCs. Equivalent to bit-reversing the result of `clmul` on
828 [[!inline pagenames="gf_reference/clmulr.py" raw="yes"]]
831 ## `clmadd` Carry-less Multiply-Add
834 clmadd RT, RA, RB, RC
838 (RT) = clmul((RA), (RB)) ^ (RC)
841 ## `cltmadd` Twin Carry-less Multiply-Add (for FFTs)
843 Used in combination with SV FFT REMAP to perform a full Discrete Fourier
844 Transform of Polynomials over GF(2) in-place. Possible by having 3-in 2-out,
845 to avoid the need for a temp register. RS is written to as well as RT.
847 Note: Polynomials over GF(2) are a Ring rather than a Field, so, because the
848 definition of the Inverse Discrete Fourier Transform involves calculating a
849 multiplicative inverse, which may not exist in every Ring, therefore the
850 Inverse Discrete Fourier Transform may not exist. (AFAICT the number of inputs
851 to the IDFT must be odd for the IDFT to be defined for Polynomials over GF(2).
852 TODO: check with someone who knows for sure if that's correct.)
855 cltmadd RT, RA, RB, RC
858 TODO: add link to explanation for where `RS` comes from.
863 # read all inputs before writing to any outputs in case
864 # an input overlaps with an output register.
865 (RT) = clmul(a, (RB)) ^ c
869 ## `cldivrem` Carry-less Division and Remainder
871 `cldivrem` isn't an actual instruction, but is just used in the pseudo-code
872 for other instructions.
875 [[!inline pagenames="gf_reference/cldivrem.py" raw="yes"]]
878 ## `cldiv` Carry-less Division
887 q, r = cldivrem(n, d, width=XLEN)
891 ## `clrem` Carry-less Remainder
900 q, r = cldivrem(n, d, width=XLEN)
904 # Instructions for Binary Galois Fields `GF(2^m)`
908 * <https://courses.csail.mit.edu/6.857/2016/files/ffield.py>
909 * <https://engineering.purdue.edu/kak/compsec/NewLectures/Lecture7.pdf>
910 * <https://foss.heptapod.net/math/libgf2/-/blob/branch/default/src/libgf2/gf2.py>
912 Binary Galois Field addition/subtraction is simply XOR, so a `gfbadd`
913 instruction is not provided since the `xor[i]` instruction can be used instead.
915 ## `GFBREDPOLY` SPR -- Reducing Polynomial
917 In order to save registers and to make operations orthogonal with standard
918 arithmetic, the reducing polynomial is stored in a dedicated SPR `GFBREDPOLY`.
919 This also allows hardware to pre-compute useful parameters (such as the
920 degree, or look-up tables) based on the reducing polynomial, and store them
921 alongside the SPR in hidden registers, only recomputing them whenever the SPR
922 is written to, rather than having to recompute those values for every
925 Because Galois Fields require the reducing polynomial to be an irreducible
926 polynomial, that guarantees that any polynomial of `degree > 1` must have
927 the LSB set, since otherwise it would be divisible by the polynomial `x`,
928 making it reducible, making whatever we're working on no longer a Field.
929 Therefore, we can reuse the LSB to indicate `degree == XLEN`.
932 [[!inline pagenames="gf_reference/decode_reducing_polynomial.py" raw="yes"]]
935 ## `gfbredpoly` -- Set the Reducing Polynomial SPR `GFBREDPOLY`
937 unless this is an immediate op, `mtspr` is completely sufficient.
940 [[!inline pagenames="gf_reference/gfbredpoly.py" raw="yes"]]
943 ## `gfbmul` -- Binary Galois Field `GF(2^m)` Multiplication
950 [[!inline pagenames="gf_reference/gfbmul.py" raw="yes"]]
953 ## `gfbmadd` -- Binary Galois Field `GF(2^m)` Multiply-Add
956 gfbmadd RT, RA, RB, RC
960 [[!inline pagenames="gf_reference/gfbmadd.py" raw="yes"]]
963 ## `gfbtmadd` -- Binary Galois Field `GF(2^m)` Twin Multiply-Add (for FFT)
965 Used in combination with SV FFT REMAP to perform a full `GF(2^m)` Discrete
966 Fourier Transform in-place. Possible by having 3-in 2-out, to avoid the need
967 for a temp register. RS is written to as well as RT.
970 gfbtmadd RT, RA, RB, RC
973 TODO: add link to explanation for where `RS` comes from.
978 # read all inputs before writing to any outputs in case
979 # an input overlaps with an output register.
980 (RT) = gfbmadd(a, (RB), c)
981 # use gfbmadd again since it reduces the result
982 (RS) = gfbmadd(a, 1, c) # "a * 1 + c"
985 ## `gfbinv` -- Binary Galois Field `GF(2^m)` Inverse
992 [[!inline pagenames="gf_reference/gfbinv.py" raw="yes"]]
995 # Instructions for Prime Galois Fields `GF(p)`
997 ## `GFPRIME` SPR -- Prime Modulus For `gfp*` Instructions
999 ## `gfpadd` Prime Galois Field `GF(p)` Addition
1006 [[!inline pagenames="gf_reference/gfpadd.py" raw="yes"]]
1009 the addition happens on infinite-precision integers
1011 ## `gfpsub` Prime Galois Field `GF(p)` Subtraction
1018 [[!inline pagenames="gf_reference/gfpsub.py" raw="yes"]]
1021 the subtraction happens on infinite-precision integers
1023 ## `gfpmul` Prime Galois Field `GF(p)` Multiplication
1030 [[!inline pagenames="gf_reference/gfpmul.py" raw="yes"]]
1033 the multiplication happens on infinite-precision integers
1035 ## `gfpinv` Prime Galois Field `GF(p)` Invert
1041 Some potential hardware implementations are found in:
1042 <https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.90.5233&rep=rep1&type=pdf>
1045 [[!inline pagenames="gf_reference/gfpinv.py" raw="yes"]]
1048 ## `gfpmadd` Prime Galois Field `GF(p)` Multiply-Add
1051 gfpmadd RT, RA, RB, RC
1055 [[!inline pagenames="gf_reference/gfpmadd.py" raw="yes"]]
1058 the multiplication and addition happens on infinite-precision integers
1060 ## `gfpmsub` Prime Galois Field `GF(p)` Multiply-Subtract
1063 gfpmsub RT, RA, RB, RC
1067 [[!inline pagenames="gf_reference/gfpmsub.py" raw="yes"]]
1070 the multiplication and subtraction happens on infinite-precision integers
1072 ## `gfpmsubr` Prime Galois Field `GF(p)` Multiply-Subtract-Reversed
1075 gfpmsubr RT, RA, RB, RC
1079 [[!inline pagenames="gf_reference/gfpmsubr.py" raw="yes"]]
1082 the multiplication and subtraction happens on infinite-precision integers
1084 ## `gfpmaddsubr` Prime Galois Field `GF(p)` Multiply-Add and Multiply-Sub-Reversed (for FFT)
1086 Used in combination with SV FFT REMAP to perform
1087 a full Number-Theoretic-Transform in-place. Possible by having 3-in 2-out,
1088 to avoid the need for a temp register. RS is written
1092 gfpmaddsubr RT, RA, RB, RC
1095 TODO: add link to explanation for where `RS` comes from.
1101 # read all inputs before writing to any outputs in case
1102 # an input overlaps with an output register.
1103 (RT) = gfpmadd(factor1, factor2, term)
1104 (RS) = gfpmsubr(factor1, factor2, term)
1107 # Already in POWER ISA or subsumed
1109 Lists operations either included as part of
1110 other bitmanip operations, or are already in
1115 based on RV bitmanip, covered by ternlog bitops
1118 uint_xlen_t cmix(uint_xlen_t RA, uint_xlen_t RB, uint_xlen_t RC) {
1119 return (RA & RB) | (RC & ~RB);
1123 ## count leading/trailing zeros with mask
1129 do i = 0 to 63 if((RB)i=1) then do
1130 if((RS)i=1) then break end end count ← count + 1
1136 pdepd VRT,VRA,VRB, identical to RV bitmamip bdep, found already in v3.1 p106
1139 if VSR[VRB+32].dword[i].bit[63-m]=1 then do
1140 result = VSR[VRA+32].dword[i].bit[63-k]
1141 VSR[VRT+32].dword[i].bit[63-m] = result
1147 uint_xlen_t bdep(uint_xlen_t RA, uint_xlen_t RB)
1150 for (int i = 0, j = 0; i < XLEN; i++)
1151 if ((RB >> i) & 1) {
1153 r |= uint_xlen_t(1) << i;
1163 other way round: identical to RV bext: pextd, found in v3.1 p196
1166 uint_xlen_t bext(uint_xlen_t RA, uint_xlen_t RB)
1169 for (int i = 0, j = 0; i < XLEN; i++)
1170 if ((RB >> i) & 1) {
1172 r |= uint_xlen_t(1) << j;
1181 found in v3.1 p106 so not to be added here
1191 if((RB)63-i==1) then do
1192 result63-ptr1 = (RS)63-i
1198 ## bit to byte permute
1200 similar to matrix permute in RV bitmanip, which has XOR and OR variants,
1201 these perform a transpose (bmatflip).
1202 TODO this looks VSX is there a scalar variant
1207 b = VSR[VRB+32].dword[i].byte[k].bit[j]
1208 VSR[VRT+32].dword[i].byte[j].bit[k] = b
1212 superceded by grevlut
1214 based on RV bitmanip, this is also known as a butterfly network. however
1215 where a butterfly network allows setting of every crossbar setting in
1216 every row and every column, generalised-reverse (grev) only allows
1217 a per-row decision: every entry in the same row must either switch or
1220 <img src="https://upload.wikimedia.org/wikipedia/commons/thumb/8/8c/Butterfly_Network.jpg/474px-Butterfly_Network.jpg" />
1223 uint64_t grev64(uint64_t RA, uint64_t RB)
1226 int shamt = RB & 63;
1227 if (shamt & 1) x = ((x & 0x5555555555555555LL) << 1) |
1228 ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
1229 if (shamt & 2) x = ((x & 0x3333333333333333LL) << 2) |
1230 ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
1231 if (shamt & 4) x = ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
1232 ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
1233 if (shamt & 8) x = ((x & 0x00FF00FF00FF00FFLL) << 8) |
1234 ((x & 0xFF00FF00FF00FF00LL) >> 8);
1235 if (shamt & 16) x = ((x & 0x0000FFFF0000FFFFLL) << 16) |
1236 ((x & 0xFFFF0000FFFF0000LL) >> 16);
1237 if (shamt & 32) x = ((x & 0x00000000FFFFFFFFLL) << 32) |
1238 ((x & 0xFFFFFFFF00000000LL) >> 32);
1246 based on RV bitmanip, gorc is superceded by grevlut
1249 uint32_t gorc32(uint32_t RA, uint32_t RB)
1252 int shamt = RB & 31;
1253 if (shamt & 1) x |= ((x & 0x55555555) << 1) | ((x & 0xAAAAAAAA) >> 1);
1254 if (shamt & 2) x |= ((x & 0x33333333) << 2) | ((x & 0xCCCCCCCC) >> 2);
1255 if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4) | ((x & 0xF0F0F0F0) >> 4);
1256 if (shamt & 8) x |= ((x & 0x00FF00FF) << 8) | ((x & 0xFF00FF00) >> 8);
1257 if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16);
1260 uint64_t gorc64(uint64_t RA, uint64_t RB)
1263 int shamt = RB & 63;
1264 if (shamt & 1) x |= ((x & 0x5555555555555555LL) << 1) |
1265 ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
1266 if (shamt & 2) x |= ((x & 0x3333333333333333LL) << 2) |
1267 ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
1268 if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
1269 ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
1270 if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL) << 8) |
1271 ((x & 0xFF00FF00FF00FF00LL) >> 8);
1272 if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL) << 16) |
1273 ((x & 0xFFFF0000FFFF0000LL) >> 16);
1274 if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL) << 32) |
1275 ((x & 0xFFFFFFFF00000000LL) >> 32);
1284 see [[bitmanip/appendix]]