1 # SVP64 Branch Conditional behaviour
5 Please note: SVP64 Branch instructions should be
6 considered completely separate and distinct from
7 standard scalar OpenPOWER-approved v3.0B branches.
8 **v3.0B branches are in no way impacted, altered,
9 changed or modified in any way, shape or form by
10 the SVP64 Vectorised Variants**.
14 * <https://bugs.libre-soc.org/show_bug.cgi?id=664>
15 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-August/003416.html>
16 * [[openpower/isa/branch]]
18 Scalar 3.0B Branch Conditional operations, `bc`, `bctar` etc. test a
19 Condition Register. When doing so in a Vector Context, it is quite
20 reasonable and logical to test and Branch on a *Vector* of CR Fields
21 which have just been calculated from a *Vector* of results. In 3D Shader
22 binaries, which are inherently parallelised and predicated, testing all or
23 some results and branching based on multiple tests is extremely common,
24 and a fundamental part of Shader Compilers. Therefore, `sv.bc` and
25 other Vector-aware Branch Conditional instructions are a high priority
28 The `BI` field of Branch Conditional operations is five bits, in scalar
29 v3.0B this would select one bit of the 32 bit CR. In SVP64 there are
30 16 32 bit CRs, containing 128 4-bit CR Fields. Therefore, the 2 LSBs of
31 `BI` select the bit from the CR Field (EQ LT GT SO), and the top 3 bits
32 are extended to either scalar or vector and to select CR Fields 0..127
33 as specified in SVP64 [[sv/svp64/appendix]]
35 When considering an "array" of branches, there are four useful modes:
36 AND, OR, NAND and NOR of all Conditions.
37 NAND and NOR may be synthesised by
38 inverting `BO[2]` which just leaves two modes:
40 * Branch takes place on the first CR test to succeed
41 (a Great Big OR of all condition tests)
42 * Branch takes place only if **all** CR tests succeed:
43 a Great Big AND of all condition tests
44 (including those where the predicate is masked out
45 and the corresponding CR Field is considered to be
48 In SVP64 Horizontal-First Mode, the first failure in ALL mode (Great Big
49 AND) results in early exit: no more updates to CTR occur (if requested);
50 no branch occurs, and LR is not updated (if requested). Likewise for
51 non-ALL mode (Great Big Or) on first success early exit also occurs,
52 however this time with the Branch proceeding. In both cases the testing
53 of the Vector of CRs should be done in linear sequential order (or in
54 REMAP re-sequenced order): such that tests that are sequentially beyond
55 the exit point are *not* carried out. (*Note: it is standard practice in
56 Programming languages to exit early from conditional tests, however
57 a little unusual to consider in an ISA that is designed for Parallel
58 Vector Processing. The reason is to have strictly-defined guaranteed
61 In Vertical-First Mode, the `ALL` bit should not be used. If set,
62 behaviour is `UNDEFINED`. (*The reason is that Vertical-First hints may
63 permit multiple elements up to hint length to be executed in parallel,
64 however the number is entirely up to implementors. Attempting to test
65 an arbitrary indeterminate number of Conditional tests is impossible
66 to define, and efforts to enforce such defined behaviour interfere with
67 Vertical-First mode parallel opportunistic behaviour.*)
69 In `svstep` mode, srcstep and dststep are incremented, and then
70 tested exactly as in [[sv/svstep]]. When Rc=1 the test results
71 are wtitten into the whole CR Field (the exact same one
72 about to be tested by the Branch Condition). Following the svstep
74 Branch Conditional instruction proceeds as normal (reading and testing
75 the CR bit just updated, if the relevant `BO` bit is set). Note that
76 the SVSTATE srcstep and dststep fields are still updated
77 and the CR field still updated, even if `BO[0]` is set.
79 Predication in both INT and CR modes may be applied to `sv.bc` and other
80 SVP64 Branch Conditional operations, exactly as they may be applied to
81 other SVP64 operations. When `sz` is zero, any masked-out Branch-element
82 operations are not executed, exactly like all other SVP64 operations.
84 However when `sz` is non-zero, this normally requests insertion of a zero
85 in place of the input data, when the relevant predicate mask bit is zero.
86 This would mean that a zero is inserted in place of `CR[BI+32]` for
87 testing against `BO`, which may not be desirable in all circumstances.
88 Therefore, an extra field is provided `SNZ`, which, if set, will insert
89 a **one** in place of a masked-out element instead of a zero.
91 (*Note: Both options are provided because it is useful to deliberately
92 cause the Branch-Conditional Vector testing to fail at a specific point,
93 controlled by the Predicate mask. This is particularly useful in `VLSET`
94 mode, which will truncate SVSTATE.VL at the point of the first failed
97 SVP64 RM `MODE` for Branch Conditional:
99 | 0-1 | 2 | 3 4 | description |
100 | --- | --- |---------|-------------------------- |
101 | 00 | SNZ | ALL sz | normal mode |
102 | 01 | VLI | ALL sz | VLSET mode |
103 | 10 | SNZ | ALL sz | svstep mode |
104 | 11 | VLI | ALL sz | svstep VLSET mode, in Horizontal-First |
105 | 11 | VLI | SNZ sz | svstep VLSET mode, in Vertical-First |
109 * **sz** if predication is enabled will put 4 copies of `SNZ` in place of
110 the src CR Field when the predicate bit is zero. otherwise the element
111 is ignored or skipped, depending on context.
112 * **ALL** when set, all branch conditional tests must pass in order for
113 the branch to succeed.
114 * **VLI** In VLSET mode, VL is set equal (truncated) to the first
115 branch which succeeds. If VLI (Vector Length Inclusive) is clear,
116 VL is truncated to *exclude* the current element, otherwise it is
117 included. SVSTATE.MVL is not changed.
119 svstep mode will run an increment of SVSTATE srcstep and dststep
120 (which is still useful in Horizontal First Mode). Unlike `svstep.`
121 however which updates only CR0 with the testing of REMAP loop progress,
122 the CR Field is taken from the branch `BI` field, and updated prior to
123 proceeding to each element branch conditional testing.
125 Note that, interestingly, due to the useful side-effects of `VLSET` mode
126 and `svstep` mode it is actually useful to use Branch Conditional even
127 to perform no actual branch operation, i.e to point to the instruction
130 In particular, svstep mode is still useful for Horizontal-First Mode
131 particularly in combination with REMAP. All "loop end" conditions
132 will be tested on a per-element basis and placed into a Vector of CRs
133 starting from the point specified by the Branch `BI` field. This Vector
134 of CR Fields may then be subsequently used as a Predicate Mask, and,
135 furthermore, if VLSET mode was requested, VL will have been set to the
136 length of one of the loop endpoints, again as specified by the bit from
137 the Branch `BI` field.
139 Also, the unconditional bit `BO[0]` is still relevant when Predication
140 is applied to the Branch because in `ALL` mode all nonmasked bits have
141 to be tested. Even when svstep mode or VLSET mode are not used, CTR
142 may still be decremented by the total number of nonmasked elements.
143 In short, Vectorised Branch becomes an extremely powerful tool.
145 Available options to combine:
147 * `BO[0]` to make an unconditional branch would seem irrelevant if
148 it were not for predication and for side-effects.
149 * `BO[1]` to select whether the CR bit being tested is zero or nonzero
150 * `R30` and `~R30` and other predicate mask options including CR and
151 inverted CR bit testing
152 * `sz` and `SNZ` to insert either zeros or ones in place of masked-out
154 * `ALL` or `ANY` behaviour corresponding to `AND` of all tests and
155 `OR` of all tests, respectively.
157 In addition to the above, it is necessary to select whether, in `svstep`
158 mode, the Vector CR Field is to be overwritten or not: in some cases
159 it is useful to know but in others all that is needed is the branch itself.
160 In the case of `sv.bc` there is no additional bitspace, so on the
161 basis that it is rarely used, the `AA`
162 field is re-interpreted instead to be `Rc`. For `sv.bclr`, there is free
163 bitspace and so bit 16 has been chosen as `Rc`.
165 **These interpretations are only available for sv.bc, they are NOT
166 available for Power ISA v3.0B** i.e. only when embedded in an SVP64
167 Prefix Context do these and all other parts of this specification
170 Form: B-Form (see [[isatables/fields.text]])
172 | 0.5|6.10|11.15|16..29| 30 |31| name |
173 | -- | -- | --- | ---- | -- |--| ------- |
174 |16 | BO | BI | BD | Rc |LK| sv.bc |
176 Form: XL-Form (see [[isatables/fields.text]])
178 | 0.5|6.10|11.15|16|17.18|19.20|21..30|31| name |
179 | -- | -- | --- |--|---- |-----|------|--| ------- |
180 |19 | BO | BI |Rc| // | BH | 19 |LK| sv.bclr |
182 Pseudocode for Rc in sv.bc
185 # Use bit 30 as Rc, disable AA
190 Pseudocode for Rc in sv.bclr
193 # use bit 16 of opcode as Rc
197 Pseudocode for Horizontal-First Mode:
200 cond_ok = not SVRMmode.ALL
201 for srcstep in range(VL):
202 # select predicate bit or zero/one
203 if predicate[srcstep]:
204 # get SVP64 extended CR field 0..127
205 SVCRf = SVP64EXTRA(BI>>2)
207 new_srcstep, CRbits = SVSTATE_NEXT(srcstep)
210 if Rc = 1 then # CR0 Vectorised
211 CR{0+srcstep} = CRbits
212 testbit = CRbits[BI & 0b11]
213 # testbit = CR[BI+32+srcstep*4]
214 else if not SVRMmode.sz:
217 testbit = SVRMmode.SNZ
218 # actual element test here
219 el_cond_ok <- BO[0] | ¬(testbit ^ BO[1])
222 cond_ok &= el_cond_ok
224 cond_ok |= el_cond_ok
225 # test for VL to be set (and exit)
226 if ~el_cond_ok and VLSET
228 SVSTATE.VL = srcstep+1
240 SVSTATE.srcstep = new_srcstep
243 Pseudocode for Vertical-First Mode:
246 # get SVP64 extended CR field 0..127
247 SVCRf = SVP64EXTRA(BI>>2)
249 new_srcstep, CRbits = SVSTATE_NEXT(srcstep)
252 # select predicate bit or zero/one
253 if predicate[srcstep]:
254 if Rc = 1 then # CR0 vectorised
255 CR{0+srcstep} = CRbits
256 testbit = CRbits[BI & 0b11]
257 else if not SVRMmode.sz:
258 SVSTATE.srcstep = new_srcstep
259 exit # no branch testing
261 testbit = SVRMmode.SNZ
262 # actual element test here
263 cond_ok <- BO[0] | ¬(testbit ^ BO[1])
264 # test for VL to be set (and exit)
265 if ~cond_ok and VLSET
267 SVSTATE.VL = new_srcstep+1
269 SVSTATE.VL = new_srcstep
271 SVSTATE.srcstep = new_srcstep
274 # Example Shader code
286 which compiles to something like:
291 pred loop_pred = a > 2;
292 while(loop_pred.any()) {
293 pred if_pred = loop_pred & (b < 5);
298 pred else_pred = loop_pred & ~if_pred;
299 if(else_pred.any()) {
306 which will end up as:
309 sv.cmpi CR60.v a.v, 2 # vector compare a into CR60 vector
310 sv.crweird r30, CR60.GT # transfer GT vector to r30
312 sv.cmpi CR80.v, b.v, 5 # vector compare b into CR64 Vector
313 sv.bc/m=r30/~ALL/sz CR80.v.LT skip_f # skip when none
314 # only calculate loop_pred & pred_b because needed in f()
315 sv.crand CR80.v.SO, CR60.v.GT, CR80.V.LT # if = loop & pred_b
318 # illustrate inversion of pred_b. invert r30, test ALL
319 # rather than SOME, but masked-out zero test would FAIL,
320 # therefore masked-out instead is tested against 1 not 0
321 sv.bc/m=~r30/ALL/SNZ CR80.v.LT skip_g
322 # else = loop & ~pred_b, need this because used in g()
323 sv.crternari(A&~B) CR80.v.SO, CR60.v.GT, CR80.V.LT
326 # conditionally call h(r30) if any loop pred set
327 sv.bclr/m=r30/~ALL/sz BO[1]=1 h()
328 sv.bc/m=r30/~ALL/sz BO[1]=1 while_loop