openpower/sv/branches.mdwn

   1 # SVP64 Branch Conditional behaviour
   2
   3 Links
   4
   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=664>
   6 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-August/003416.html>
   7
   8 TODO
   9
  10 | 0-1 |  2  |  3   4  |  description              |
  11 | --- | --- |---------|-------------------------- |
  12 | 00  |   0 |  ALL sz | normal mode                      |
  13 | 01  | VLI |  ALL sz | VLSET mode                      |
  14 | 10  |   0 |  ALL sz | svstep mode                      |
  15 | 11  | VLI |  ALL sz | svstep VLSET mode                      |
  16
  17 Fields:
  18
  19 * **sz**  if predication is enabled will put zeros into the src CR when the predicate bit is zero.  otherwise the element is ignored or skipped, depending on context.
  20 * **ALL** when set, all branch conditional tests must pass in order for
  21 the branch to succeed.
  22 * **VLI** In VLSET mode, VL is set equal (truncated) to the first branch
  23 which succeeds.  If VLI (Vector Length Inclusive) is clear, VL is truncated
  24 to *exclude* the current element, otherwise it is included. SVSTATE.MVL is not changed.
  25
  26 svstep mode will run an increment of SVSTATE srcstep and dststep
  27 (only meaningful in Vertical First Mode).  Unlike `svstep.` however
  28 which updates only CR0 with the testing of REMAP loop progress,
  29 the CR Field is taken from the branch `BI` field, and updated
  30 prior to proceeding to branch conditional testing.
  31