openpower/sv/branches.mdwn

   1 # SVP64 Branch Conditional behaviour
   2
   3 Links
   4
   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=664>
   6 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-August/003416.html>
   7
   8 TODO
   9 | 0-1 |  2  |  3   4  |  description              |
  10 | --- | --- |---------|-------------------------- |
  11 | 00  |   0 |  ALL sz | normal mode                      |
  12 | 01  | VLI |  ALL sz | VLSET mode                      |
  13
  14 Fields:
  15
  16 * **sz**  if predication is enabled will put zeros into the src CR when the predicate bit is zero.  otherwise the element is ignored or skipped, depending on context.
  17 * **ALL** when set, all branch conditional tests must pass in order for
  18 the branch to succeed.
  19 * **VLI** In VLSET mode, VL is set equal (truncated) to the first branch
  20 which succeeds.  If VLI (Vector Length Inclusive) is clear, VL is truncated
  21 to *exclude* the current element, otherwise it is included.