openpower/sv/branches.mdwn

   1 # SVP64 Branch Conditional behaviour
   2
   3 Links
   4
   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=664>
   6 * <http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-August/003416.html>
   7
   8 Branch Conditional operations, `bc`, `bctar` etc. test a Condition Register.
   9 When doing so, it is quite reasonable and logical to test a *Vector* of
  10 CR Fields. In 3D Shader binaries, which are inherently parallelised
  11 and predicated, testing all or some results and branching based on
  12 multiple tests is extremely common.
  13 Therefore, `sv.bc` and other Branch Conditional instructions are worth
  14 including.
  15
  16 The `BI` field of Branch Conditional operations is five bits,
  17 in scalar v3.0B this would select one bit of the 32 bit CR.
  18 In SVP64 there are 16 32 bit CRs, containing 128 4-bit CR Fields.
  19 Therefore, the 2 LSBs of `BI` select the bit from the CR, and the
  20 top 3 bits are extended to either scalar or vector and to
  21 select CR Fields 0..127 as specified
  22 in SVP64 [[sv/svp64/appendix]]
  23
  24 When considering an "array" of branches, there are two useful modes:
  25
  26 * Branch takes place on the first CR test to succeed.
  27 * Branch takes place only if **all** CR tests succeed
  28   (including those where the predicate is masked out
  29    and the corresponding CR Field is considered to be
  30    set to `SNZ`)
  31
  32 In Vertical-First Mode, the `ALL` bit should
  33 not be used.  If set, behaviour is `UNDEFINED`.
  34 (*The reason is that Vertical-First hints may permit
  35 multiple elements up to hint length to be executed
  36 in parallel, however the number is entirely up to
  37 implementors.  Attempting to test an arbitrary
  38 indeterminate number of Conditional tests is impossible
  39 to define, and efforts to enforce such defined behaviour
  40 interfere with Vertical-First mode parallel behaviour.*)
  41
  42 `svstep` mode is only meaningful in Vertical-First Mode.
  43 The CR Field selected by `BI` is updated based on
  44 incrementing srcstep and dststep, and performing the
  45 same tests as [[sv/svstep]], following which the Branch
  46 Conditional instruction proceeds as normal (reading
  47 and testing the CR bit just updated, if the relevant
  48 `BO` bit is set).  Note that the SVSTATE fields
  49 are still updated, and the CR field still updated,
  50 even if the `BO` bits do not require CR testing.
  51
  52 Predication in both INT and CR modes may be applied to
  53 `sv.bc` and other SVP64 Branch Conditional operations,
  54 exactly as they may be applied to other SVP64 operations.
  55 When `sz` is zero, any masked-out Branch-element operations
  56 are masked-out (not executed), exactly like all other SVP64
  57 operations.
  58
  59 However when `sz` is non-zero, this normally requests insertion
  60 of a zero in place of the input data, when the relevant predicate
  61 mask bit is zero.  This would mean that a zero is inserted in
  62 place of `CR[BI+32]` for testing against `BO`, which may not
  63 be desirable in all circumstances.  Therefore, an extra field
  64 is provided `SNZ`, which, if set, will insert a **one** in
  65 place of a masked-out element instead of a zero.
  66
  67 (*Note: Both options are provided because it is useful to
  68 deliberately cause the Branch-Conditional Vector testing
  69 to fail at a specific point, controlled by the Predicate
  70 mask. This is particularly useful in `VLSET` mode, which
  71 will truncate SVSTATE.VL at the point of the first failed
  72 test.*)
  73
  74 SVP64 RM `MODE` for Branch Conditional:
  75
  76 | 0-1 |  2  |  3   4  |  description              |
  77 | --- | --- |---------|-------------------------- |
  78 | 00  | SNZ |  ALL sz | normal mode                      |
  79 | 01  | VLI |  ALL sz | VLSET mode                      |
  80 | 10  | SNZ |  ALL sz | svstep mode                      |
  81 | 11  | VLI |  ALL sz | svstep VLSET mode                      |
  82
  83 Fields:
  84
  85 * **sz**  if predication is enabled will put 4 copies of `SNZ` in place of the src CR Field when the predicate bit is zero.  otherwise the element is ignored or skipped, depending on context.
  86 * **ALL** when set, all branch conditional tests must pass in order for
  87 the branch to succeed.
  88 * **VLI** In VLSET mode, VL is set equal (truncated) to the first branch
  89 which succeeds.  If VLI (Vector Length Inclusive) is clear, VL is truncated
  90 to *exclude* the current element, otherwise it is included. SVSTATE.MVL is not changed.
  91
  92 svstep mode will run an increment of SVSTATE srcstep and dststep
  93 (only meaningful in Vertical First Mode).  Unlike `svstep.` however
  94 which updates only CR0 with the testing of REMAP loop progress,
  95 the CR Field is taken from the branch `BI` field, and updated
  96 prior to proceeding to branch conditional testing.
  97
  98 Note that, interestingly, due to the useful side-effects of `VLSET` mode
  99 and `svstep` mode it is actually useful to use Branch Conditional even
 100 to perform no actual branch operation, i.e to point to the instruction
 101 after the branch.