openpower/sv/compliancy_levels.mdwn

   1 [[!tag standards]]
   2
   3 # Simple-V Compliancy Levels
   4
   5 The purpose of the Compliancy Levels is to provide a documented
   6 stable base for implementors to achieve software interoperability
   7 without requiring a high and unnecessary hardware cost unrelated
   8 to their needs. The bare
   9 minimum requirement, particularly suited for Ultra-embedded, requires
  10 just one instruction, reservation of SPRs, and the rest may entirely
  11 be Soft-emulated by raising Illegal Instruction traps.  At the other
  12 end of the spectrum is the full REMAP Structure Packing suitable
  13 for traditional Vector Processing workloads and High-performance
  14 energy-efficient DSP workloads.
  15
  16 To achieve full soft-emulated interoperability, all implementations
  17 **must**, at the bare minimum, raise Illegal Instruction traps for
  18 all SPRs including all reserved SPRs, all SVP64-related Context
  19 instructions (REMAP), as well as for the entire SVP64 Prefix space.
  20
  21 Summary of Compliancy Levels, each Level includes all lower levels:
  22
  23 * **Ultra-embedded**: `setvl` instruction and context-switching of SVSTATE
  24   to/from SVSRR1. Register Files as Standard Power ISA.
  25 * **Embedded**: `svstep` instruction,
  26   and support for Hardware for-looping
  27   in both Horizontal-First and Vertical-First Mode as well as Predication
  28   (Single and Twin) for the GPRs r3, r10 and r30.  CR-Field-based
  29   Predicates, if used, may still raise illegal instruction trap.
  30 * **DSP/AV**: 128 registers, all SV Branch instructions,
  31   crweird instructions, element-width
  32   overrides, and all Modes (Saturation, Fail-First, Predicate-Result,
  33   Mapreduce/Iteration)
  34 * **3D/Advanced/Supercomputing**: Matrix, DCT/FFT and Indexing
  35   REMAP capability
  36
  37 These requirements within each Level constitute the minimum mandatory
  38 capabilities.
  39 It is also permitted that any Level include any part of a higher Compliancy
  40 Level. For example:
  41 an Embedded Level is permitted to have 128 GPRs, FPRs and CR Fields,
  42 but the Compliance Tests for Embedded will only test for 32.  DSP/VPU Level
  43 is permitted to implement the DCT REMAP capability, but will not be
  44 permitted to declare meeting the 3D/Advanced Level unless implementing
  45 *all* REMAP Capabilities.
  46
  47 # Ultra-Embedded Level
  48
  49 This level exists as an entry-level into SVP64, most suited to resource
  50 constrained soft cores, or Hardware implementations where cost is a
  51 higher priority than execution speed.
  52
  53 This level sets the bare minimum requirements, where everything with the
  54 exception of the `setvl` instruction may be software-emulated through
  55 JIT Translation or Illegal Instruction traps.  SVSTATE joins MSR and PC
  56 as direct peers and must be switched on any context-switch (Trap or
  57 Exception)
  58
  59 * PC is saved/restored to/from SRR0
  60 * MSR is saved/restored to/from SRR1
  61 * SVSTATE **must** also be saved/restored to/from SVSRR1
  62
  63 Any implementation that implements Hypervisor Mode must also
  64 correspondingly follow the Power ISA Spec guidelines for HSRR0 and HSRR1,
  65 and must save/restore SVSTATE to/from HSVSRR1 in all circumstances
  66 involving save/restore to/from HSRR0 and HSRR1.
  67
  68 Illegal Instruction Trap **must** be raised on:
  69
  70 * Any SV instructions not implemented
  71 * any unimplemented SV Context SPRs read or written
  72 * all unimplemented uses of the SVP64 Prefix
  73
  74 Implementors are free and clear to implement any other features of
  75 SVP64 however only by meeting all of the mandatory requirements above
  76 will Compliance with the Ultra-Embedded Level be achieved.
  77
  78 # Embedded Level
  79
  80 This level is more suitable for Hardware implementations where performance and power saving begins to matter.  A second instruction, `svstep`, used
  81 by Vertical-First Mode, is required, as is hardware-level looping in
  82 Horizontal-First Mode. Illegal Instruction trap may not be called to
  83 emulate `svstep`.
  84
  85 At the bare minimum, Twin and Single Predication must be supported for
  86 at least the GPRs r3, r10 and r30.  CR Field Predication may also be
  87 supported in hardware but only by also increasing the number of CR Fields
  88 to 128.
  89
  90 Another important aspect is that when Rc=1 is set, CR Field Vector co-results
  91 are produced. Should these exceed CR7 (CR8-CR127) and the number of CR Fields
  92 has not been increased to 128 then an Illegal Instruction Trap must be
  93 raised.  In practical terms, to avoid this scenario, MAXVL should not
  94 exceed 8 for Arithmetic or Logical operations when Rc=1.
  95
  96 Zeroing on source and destination for Predicates
  97 must also be supported (sz, dz) however
  98 all other Modes (Saturation, Fail-First, Predicate-Result,
  99 Iteration/Reduction) are entirely optional. Implementation of Element-Width
 100 Overrides is also optional.