3 # New instructions for CR/INT predication
9 * main bugreport for crweirds
10 <https://bugs.libre-soc.org/show_bug.cgi?id=533>
11 * <https://bugs.libre-soc.org/show_bug.cgi?id=527>
12 * <https://bugs.libre-soc.org/show_bug.cgi?id=569>
13 * <https://bugs.libre-soc.org/show_bug.cgi?id=558#c47>
17 Condition Registers are conceptually perfect for use as predicate masks, the only problem being that typical Vector ISAs have quite comprehensive mask-based instructions: set-before-first, popcount and much more. In fact many Vector ISAs can use Vectors *as* masks, consequently the entire Vector ISA is available for use in creating masks. This is not practical for SV given the strategy of leveraging pre-existing Scalar instructions in a minimalist way.
19 With the scalar OpenPOWER v3.0B ISA having already popcnt, cntlz and others normally seen in Vector Mask operations it makes sense to allow *both* scalar integers *and* CR-Vectors to be predicate masks. That in turn means that much more comprehensive interaction between CRs and scalar Integers is required, because with the CR Predication Modes designating CR *Fields*
20 (not CR bits) as Predicate Elements, fast transfers between CR *Fields* and
21 the Integer Register File is needed.
23 The opportunity is therefore taken to also augment CR logical arithmetic as well, using a mask-based paradigm that takes into consideration multiple bits of each CR Field (eq/lt/gt/ov). By contrast
24 v3.0B Scalar CR instructions (crand, crxor) only allow a single bit calculation.
28 * CR-based instructions that perform simple AND/OR/XOR from any four bits
29 of a CR field to create a single bit value (0/1) in an integer register
30 * Inverse of the same, taking a single bit value (0/1) from an integer
31 register to selectively target any four bits of a given CR Field
32 * CR-to-CR version of the same, allowing multiple bits to be AND/OR/XORed
34 * Optional Vectorisation of the same when SVP64 is implemented
38 * To provide a merged version of what is currently a multi-sequence of
39 CR operations (crand, cror, crxor) with mfcr and mtcrf, reducing
41 * To provide a vectorised version of the same, suitable for advanced
46 * mtcrweird when RA=0 is a means to set or clear arbitrary CR bits
47 using immediates embedded within the instruction.
49 (Twin) Predication interactions:
51 * INT twin predication with zeroing is a way to copy an integer into CRs without necessarily needing the INT register (RA). if it is, it is effectively ANDed (or negate-and-ANDed) with the INT Predicate
52 * CR twin predication with zeroing is likewise a way to interact with the incoming integer
54 this gets particularly powerful if data-dependent predication is also enabled. further explanation is below.
58 Please see [[svp64/appendix]] regarding CR bit ordering and for
59 the definition of `CR{n}`
61 # Instruction form and pseudocode
63 **DRAFT** Instruction format (use of MAJOR 19 not approved by
66 |0-5|6-10 |11|12-15|16-18|19-20|21-25 |26-30 |31|name |
67 |---|---- |--|-----|-----|-----|----- |----- |--|---- |
68 |19 |RT | |mask |BFA | |XO[0:4]|XO[5:9]|/ | |
69 |19 |RT |M |mask |BFA | 0 0 |XO[0:4]|0 mode |Rc|crrweird |
70 |19 |RA |M |mask |BF | 0 1 |XO[0:4]|0 mode |/ |mtcrweird |
71 |19 |BT |M |mask |BFA | 1 0 |XO[0:4]|0 mode |/ |crweirder |
72 |19 |BF //|M |mask |BFA | 1 1 |XO[0:4]|0 mode |/ |crweird |
76 mode is encoded in XO and is 4 bits
80 crrweird: RT, BFA, M, mask.mode
83 n0 = mask[0] & (mode[0] == creg[0])
84 n1 = mask[1] & (mode[1] == creg[1])
85 n2 = mask[2] & (mode[2] == creg[2])
86 n3 = mask[3] & (mode[3] == creg[3])
87 result = n0|n1|n2|n3 if M else n0&n1&n2&n3
88 RT[63] = result # MSB0 numbering, 63 is LSB
92 When used with SVP64 Prefixing this is a [[openpower/sv/normal]] SVP64 type operation and as
93 such can use Rc=1 and RC1 Data-dependent Mode capability
99 mtcrweird: BF, RA, M, mask.mode
102 lsb = reg[63] # MSB0 numbering
103 n0 = mask[0] & (mode[0] == lsb)
104 n1 = mask[1] & (mode[1] == lsb)
105 n2 = mask[2] & (mode[2] == lsb)
106 n3 = mask[3] & (mode[3] == lsb)
107 result = n0 || n1 || n2 || n3
109 result |= CR{BF} & ~mask
112 Note that when M=1 this operation is a Read-Modify-Write on the CR Field
113 BF. Masked-out bits of the 4-bit CR Field BF will not be changed when
114 M=1. Correspondingly when M=0 this operation is an overwrite: no read
115 of BF is required because the masked-out bits of the BF CR Field are
118 When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type operation that has
119 3-bit Data-dependent and 3-bit Predicate-result capability
126 crweird: BF, BFA, M, mask.mode
129 n0 = mask[0] & (mode[0] == creg[0])
130 n1 = mask[1] & (mode[1] == creg[1])
131 n2 = mask[2] & (mode[2] == creg[2])
132 n3 = mask[3] & (mode[3] == creg[3])
133 result = n0 || n1 || n2 || n3
135 result |= CR{BF} & ~mask
138 Note that when M=1 this operation is a Read-Modify-Write on the CR Field
139 BF. Masked-out bits of the 4-bit CR Field BF will not be changed when
140 M=1. Correspondingly when M=0 this operation is an overwrite: no read
141 of BF is required because the masked-out bits of the BF CR Field are
144 When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type operation that has
145 3-bit Data-dependent and 3-bit Predicate-result capability
152 crweirder: BT, BFA, mask.mode
155 n0 = mask[0] & (mode[0] == creg[0])
156 n1 = mask[1] & (mode[1] == creg[1])
157 n2 = mask[2] & (mode[2] == creg[2])
158 n3 = mask[3] & (mode[3] == creg[3])
159 BF = BT[2:4] # select CR
160 bit = BT[0:1] # select bit of CR
161 result = n0|n1|n2|n3 if M else n0&n1&n2&n3
164 When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64 type operation that has
165 5-bit Data-dependent and 5-bit Predicate-result capability
168 **Example Pseudo-ops:**
170 mtcri BF, mode mtcrweird BF, r0, 0, 0b1111.~mode
171 mtcrset BF, mask mtcrweird BF, r0, 1, mask.0b0000
172 mtcrclr BF, mask mtcrweird BF, r0, 1, mask.0b1111
174 # Vectorised versions
176 The name "weird" refers to a minor violation of SV rules when it comes to deriving the Vectorised versions of these instructions.
178 Normally the progression of the SV for-loop would move on to the next register.
179 Instead however in the scalar case these instructions **remain in the same register** and insert or transfer between **bits** of the scalar integer source or destination.
181 Further useful violation of the normal SV Elwidth override rules allows
182 for packing (or unpacking) of multiple CR test results into
183 (or out of) an Integer Element. Note
184 that the CR (source operand) elwidth field is utilised to determine the bit-
185 packing size (1/2/4/8 with remaining bits within the Integer element
186 set to zero) whilst the INT (dest operand) elwidth field still sets
187 the Integer element size as usual (8/16/32/default)
189 crrweird: RT, BB, mask.mode
196 n0 = mask[0] & (mode[0] == creg[0])
197 n1 = mask[1] & (mode[1] == creg[1])
198 n2 = mask[2] & (mode[2] == creg[2])
199 n3 = mask[3] & (mode[3] == creg[3])
200 # OR or AND to a single bit
201 result = n0|n1|n2|n3 if M else n0&n1&n2&n3
203 # TODO: RT.elwidth override to be also added here
204 # note, yes, really, the CR's elwidth field determines
205 # the bit-packing into the INT!
206 if BB.elwidth == 0b00:
207 # pack 1 result into 64-bit registers
208 iregs[RT+i][0..62] = 0
209 iregs[RT+i][63] = result # sets LSB to result
210 if BB.elwidth == 0b01:
211 # pack 2 results sequentially into INT registers
212 iregs[RT+i//2][0..61] = 0
213 iregs[RT+i//2][63-(i%2)] = result
214 if BB.elwidth == 0b10:
215 # pack 4 results sequentially into INT registers
216 iregs[RT+i//4][0..59] = 0
217 iregs[RT+i//4][63-(i%4)] = result
218 if BB.elwidth == 0b11:
219 # pack 8 results sequentially into INT registers
220 iregs[RT+i//8][0..55] = 0
221 iregs[RT+i//8][63-(i%8)] = result
223 iregs[RT][63-i] = result # results also in scalar INT
227 * in the scalar case the CR-Vector assessment
228 is stored bit-wise starting at the LSB of the
229 destination scalar INT
230 * in the INT-vector case the results are packed into LSBs
231 of the INT Elements, the packing arrangement depending on both
232 elwidth override settings.
234 # v3.1 setbc instructions
236 there are additional setb conditional instructions in v3.1 (p129)
238 RT = (CR[BI] == 1) ? 1 : 0
240 which also negate that, and also return -1 / 0. these are similar to crweird but not the same purpose. most notable is that crweird acts on CR fields rather than the entire 32 bit CR.
242 # Predication Examples
244 Take the following example:
247 sv.mtcrweird/dm=r10/dz cr8.v, 0, 0b0011.0000
249 Here, RA is zero, so the source input is zero. The destination
250 is CR Field 8, and the destination predicate mask indicates
251 to target the first two elements. Destination predicate zeroing is
252 enabled, and the destination predicate is only set in the 2nd bit.
253 mask is 0b0011, mode is all zeros.
255 Let us first consider what should go into element 0 (CR Field 8):
257 * The destination predicate bit is zero, and zeroing is enabled.
258 * Therefore, what is in the source is irrelevant: the result must
260 * Therefore all four bits of CR Field 8 are therefore set to zero.
262 Now the second element, CR Field 9 (CR9):
264 * Bit 2 of the destination predicate, r10, is 1. Therefore the computation
265 of the result is relevant.
266 * RA is zero therefore bit 2 is zero. mask is 0b0011 and mode is 0b0000
267 * When calculating n0 thru n3 we get n0=1, n1=2, n2=0, n3=0
268 * Therefore, CR9 is set (using LSB0 ordering) to 0b0011, i.e. to mask.
270 It should be clear that this instruction uses bits of the integer
271 predicate to decide whether to set CR Fields to `(mask & ~mode)`
272 or to zero. Thus, in effect, it is the integer predicate that has
273 been copied into the CR Fields.
275 By using twin predication, zeroing, and inversion (sm=~r3, dm=r10) for example, it becomes possible to combine two Integers together in
276 order to set bits in CR Fields.
277 Likewise there are dozens of ways that CR Predicates can be used, on the
278 same sv.mtcrweird instruction.