openpower/sv/cr_int_predication.mdwn

   1 # New instructions for CR/INT predication
   2
   3 See:
   4
   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=533>
   6 * <https://bugs.libre-soc.org/show_bug.cgi?id=527>
   7 * <https://bugs.libre-soc.org/show_bug.cgi?id=569>
   8
   9 Basic concept:
  10
  11 * CR-based instructions that perform simple AND/OR/XOR from all four bits
  12   of a CR to create a single bit value (0/1) in an integer register
  13 * Inverse of the same, taking a single bit value (0/1) from an integer
  14   register to selectively target all four bits of a given CR
  15 * CR-to-CR version of the same, allowing multiple bits to be AND/OR/XORed
  16   in one hit.
  17 * Vectorisation of the same
  18
  19 Purpose:
  20
  21 * To provide a merged version of what is currently a multi-sequence of
  22   CR operations (crand, cror, crxor) with mfcr and mtcrf, reducing
  23   instruction count.
  24 * To provide a vectorised version of the same, suitable for advanced
  25   predication
  26
  27 Side-effects:
  28
  29 * mtcrweird when RA=0 is a means to set or clear arbitrary CR bits from immediates
  30
  31 (Twin) Predication interactions:
  32
  33 * INT twin predication with zeroing is a way to copy an integer into CRs without necessarily needing the INT register (RA).  if it is, it is effectively ANDed (or negate-and-ANDed) with the INT Predicate
  34 * CR twin predication with zeroing is likewise a way to interact with the incoming integer
  35
  36 this gets particularly powerful if data-dependent predication is also enabled.
  37
  38 # Bit ordering.
  39
  40 IBM chose MSB0 for the OpenPOWER v3.0B specification.  This makes things slightly hair-raising.  Our desire initially is therefore to follow the logical progression from the defined behaviour of `mtcr` and `mfcr` etc.
  41 In [[isa/sprset]] we see the pseudocode for `mtcrf` for example:
  42
  43     mtcrf FXM,RS
  44
  45     do n = 0 to 7
  46       if FXM[n] = 1 then
  47         CR[4*n+32:4*n+35] <- (RS)[4*n+32:4*n+35]
  48
  49 This places (according to a mask schedule) `CR0` into MSB0-numbered bits 32-35 of the target Integer register `RS`, these bits of `RS` being the 31st down to the 28th.  Unfortunately, even when not Vectorised, this inserts CR numbering inversions on each batch of 8 CRs, massively complicating matters.  Predication when using CRs would have to be morphed to this (unacceptably complex) behaviour:
  50
  51     for i in range(VL):
  52          n = (7-(i%8)) | (i & ~0x7) # total mess
  53          CRpredicate = CR{n}        # select CR0, CR1, ....
  54          predbit = CRpredicate[offs]  # select eq..ov bit
  55
  56 Which is nowhere close to matching the straightforward obvious case:
  57
  58     for i in range(VL):
  59          if INTpredmode:
  60              predbit = (r3)[63-i] # IBM MSB0 spec sigh
  61          else:
  62              CRpredicate = CR{i} # start at CR0, work up
  63              predbit = CRpredicate[offs]
  64
  65 In other words unless we do something about this, when we transfer bits from an Integer Predicate into a Vector of CRs, our numbering of CRs, when enumerating them in a CR Vector, would be **CR7** CR6 CR5.... CR0 **CR15** CR14 CR13... CR8 **CR23** CR22 etc. **not** the more natural and obvious CR0 CR1 ... CR23.
  66
  67 Therefore the instructions below need to **redefine** the relationship so that CR numbers (CR0, CR1) sequentially match the arithmetically-ordered bits of Integer registers.  By `arithmetic` this is deduced from the fact that the ibsteuction `addi r3, r0, 1` it will result in the **LSB** (numbered 63 in IBM MSB0 order) of r3 being set to 1 and all other bits,set to zero.  We therefore refer, below, to this LSB as "Arithmetic bit 0", and it is this bit which is used - defined - as being the first bit used in predication (on element 0).
  68
  69 Below is some pseudocode that, given a CR offset `offs` to represent `CR.eq` thru to `CR.ov` respectively, will copy the INT predicate bits in the correct order into the first 8 CRs:
  70
  71     do n = 0 to 7
  72         CR[4*n+32+offs] <- (RS)[63-n]
  73
  74 Assuming that `offs` is set to `CR.eq` this results in:
  75
  76 * Arithmetic bit 0 (the LSB) of RS being inserted into CR0.eq
  77 * Arithmetic bit 1  of RS being inserted into CR1.eq
  78 * ...
  79 * Arithmetic bit 7 of RS being inserted into CR7.eq
  80
  81 To clarify, then: all instructions below do **NOT** follow the IBM convention, they follow the natural sequence CR0 CR1 instead.  However it is critically important to note that the offsets **in** a CR (`CR.eq` for example) continue to follow the v3.0B definition and convention.
  82
  83
  84 # Instruction form and pseudocode
  85
  86 Note that `CR{n}` refers to `CR0` when `n=0` and consequently, for CR0-7, is defined, in v3.0B pseudocode, as:
  87
  88      CR{7-n} = CR[32+n*4:35+n*4]
  89
  90 Instruction format:
  91
  92     | 0-5 | 6-10  | 11 | 12-15 | 16-18 | 19-20 | 21-25   | 26-30   | 31 |
  93     | --- | ----  | -- | ----- | ----- | ----- | -----   | -----   | -- |
  94     | 19  | RT    |    | mask  | BB    |    /  | XO[0:4] | XO[5:9] | /  |
  95     | 19  | RT    | 0  | mask  | BB    |  0 /  | XO[0:4] | 0 mode  | /  |
  96     | 19  | RA    | 1  | mask  | BB    |  0 /  | XO[0:4] | 0 mode  | /  |
  97     | 19  | BT // | 0  | mask  | BB    |  1 /  | XO[0:4] | 0 mode  | /  |
  98     | 19  | BFT   | 1  | mask  | BB    |  1 /  | XO[0:4] | 0 mode  | /  |
  99
 100 mode is encoded in XO and is 4 bits
 101
 102 bit 11=0, bit 19=0
 103
 104     crrweird: RT, BB, mask.mode
 105
 106     creg = CR{BB}
 107     n0 = mask[0] & (mode[0] == creg[0])
 108     n1 = mask[1] & (mode[1] == creg[1])
 109     n2 = mask[2] & (mode[2] == creg[2])
 110     n3 = mask[3] & (mode[3] == creg[3])
 111     RT[0] = n0|n1|n2|n3
 112
 113 bit 11=1, bit 19=0
 114
 115     mtcrweird: RA, BB, mask.mode
 116
 117     reg = (RA|0)
 118     n0 = mask[0] & (mode[0] == reg[0])
 119     n1 = mask[1] & (mode[1] == reg[0])
 120     n2 = mask[2] & (mode[2] == reg[0])
 121     n3 = mask[3] & (mode[3] == reg[0])
 122     CR{BB} = n0 || n1 || n2 || n3
 123
 124 bit 11=0, bit 19=1
 125
 126     crweird: BT, BB, mask.mode
 127
 128     creg = CR{BB}
 129     n0 = mask[0] & (mode[0] == creg[0])
 130     n1 = mask[1] & (mode[1] == creg[1])
 131     n2 = mask[2] & (mode[2] == creg[2])
 132     n3 = mask[3] & (mode[3] == creg[3])
 133     CR{BT} = n0 || n1 || n2 || n3
 134
 135 bit 11=1, bit 19=1
 136
 137     crweirder: BFT, BB, mask.mode
 138
 139     creg = CR{BB}
 140     n0 = mask[0] & (mode[0] == creg[0])
 141     n1 = mask[1] & (mode[1] == creg[1])
 142     n2 = mask[2] & (mode[2] == creg[2])
 143     n3 = mask[3] & (mode[3] == creg[3])
 144     BF = BFT[2:4] # select CR
 145     bit = BFT[0:1] # select bit of CR
 146     CR{BF}[bit] = n0|n1|n2|n3
 147
 148 Pseudo-op:
 149
 150     mtcri BB, mode    mtcrweird r0, BB, 0b1111.~mode
 151     mtcrset BB, mask  mtcrweird r0, BB, mask.0b0000
 152     mtcrclr BB, mask  mtcrweird r0, BB, mask.0b1111
 153
 154