openpower/sv/cr_int_predication.mdwn

   1 # New instructions for CR/INT predication
   2
   3 See:
   4
   5 * <https://bugs.libre-soc.org/show_bug.cgi?id=533>
   6
   7 Basic concept:
   8
   9 * CR-based instructions that perform simple AND/OR/XOR from all four bits
  10   of a CR to create a single bit value (0/1) in an integer register
  11 * Inverse of the same, taking a single bit value (0/1) from an integer
  12   register to selectively target all four bits of a given CR
  13 * Vectorisation of the same
  14
  15 Purpose:
  16
  17 * To provide a merged version of what is currently a multi-sequence of
  18   CR operations (crand, cror, crxor) with mfcr and mtcrf
  19 * To provide a vectorised version of the same, suitable for advanced
  20   predication
  21
  22 # Instruction form and pseudocode
  23
  24     | 0-5 | 6-10 | 11 | 12-15 | 16-18 | 19-20 | 21-30 | 31 |
  25     | 19  | RT   | 0  | mask  | BB    |  m2   | XO    | /  |
  26     | 19  | RA   | 1  | mask  | BB    |  m2   | XO    | /  |
  27
  28 mode is encoded in XO and from m2 to produce 4 bits
  29
  30 bit 11=0:
  31
  32     crweird: RT, BB, mask.mode
  33
  34     creg = CRfile[32+BB*4:36+BB*4]
  35     n0 = mask[1] & (mode[0] == creg[0])
  36     n1 = mask[1] & (mode[1] == creg[1])
  37     n2 = mask[2] & (mode[2] == creg[2])
  38     n3 = mask[3] & (mode[3] == creg[3])
  39     RT[0] = n0 | n1 | n2 | b3
  40
  41 bit 11=1:
  42
  43     mfcrweird: RA, BB, mask.mode
  44
  45     reg = GPR(RA|0)
  46     n0 = mask[1] & (mode[0] == reg[0])
  47     n1 = mask[1] & (mode[1] == reg[0])
  48     n2 = mask[2] & (mode[2] == reg[0])
  49     n3 = mask[3] & (mode[3] == reg[0])
  50     creg = n0 | n1 | n2 | b3
  51     CRfile[32+BB*4:36+BB*4] = creg
  52