openpower/sv/cr_ops.mdwn

   1 # Condition Register SVP64 Operations
   2
   3 Condition Register Fields are only 4 bits wide: this presents some
   4 interesting conceptual challenges for SVP64, with respect to element
   5 width (which is clearly meaningless).
   6
   7
   8 Note that these rules and
   9 the alternative mapping **only** applies to instructions that **only**
  10 reference a CR Field or CR bit as the sole exclusive result. This section
  11 **does not** apply to instructions which primarily produce arithmetic
  12 results that also produce a CR Field (such as when Rc=1).
  13
  14
  15 SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations:
  16
  17 | 4 | 5 | 19-20 |  21 | 22   23 |  description     |
  18 | - | - | ----- | --- |---------|----------------- |
  19 |dz |VLi| 01    | inv |  CR-bit | normal mode      |
  20 |sz |VLi| 01    | inv |  dz Rc1 | VLSET mode       |
  21 | / | / | 00    |   0 |  dz  sz | normal mode                      |
  22 | / | / | 00    |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
  23 | / | / | 00    |   1 | 1  CRM  | parallel reduce mode (mapreduce), SUBVL=1 |
  24 | / | / | 00    |   1 | SVM RG  | subvector reduce mode, SUBVL>1   |
  25 | / | / | 10    |   / | /   /   |  RESERVED |
  26 |dz | / | 11    | inv | CR-bit  |  Rc=1: pred-result CR sel |
  27 |sz | / | 11    | inv | dz  RC1 |  Rc=0: pred-result z/nonz |
  28
  29 Fields:
  30
  31
  32 # Data-dependent fail-first and Pred-result on CR operations
  33
  34 Data-dependent SVP64 Vectorised Operations involving the creation or
  35 modification of a CR require an extra two bits, which are not available
  36 in the compact space of the `MODE` Field. With the concept of element
  37 width overrides being meaningless for CR Fields it is possible to use the
  38 `ELWIDTH` field for extra fields.
  39
  40 Condition Register based operations such as `mfcr` and `crand` can thus
  41 be made more flexible.  However the rules that apply in this section
  42 also apply to future CR-based instructions.
  43
  44 There are two primary different types of CR operations:
  45
  46 * Those which have a 3-bit operand field (referring to a CR Field)
  47 * Those which have a 5-bit operand (referring to a bit within the
  48    whole 32-bit CR)
  49
  50 Examining these two as has already been done it is observed that the
  51 difference may be considered to be that the 5-bit variant provides
  52 additional information about which CR Field bit (EQ, GE, LT, SO) is to
  53 be operated on by the instruction.
  54
  55 Thus, logically, we may set the following rule:
  56
  57 * When a 5-bit CR Result field is used in an instruction, the
  58   `inv, VLi and RC1` variant of Data-Dependent Fail-First
  59   must be used. i.e. the bit of the CR field to be tested is
  60   the one that has just been modified by the operation.
  61 * When a 3-bit CR Result field is used the `inv CRbit` variant
  62   must be used in order to select which CR Field bit shall
  63   be tested (EQ, LE, GE, SO)
  64
  65 The reason why the 3-bit CR variant needs the additional CR-bit
  66 field should be obvious from the fact that the 3-bit CR Field
  67 from the base Power ISA v3.0B operation clearly does not contain
  68 and is missing the two CR Field Selector bits. Thus, these two
  69 bits (to select EQ, LE, GE or SO) must be provided in another
  70 way.
  71
  72 Examples of the former type:
  73
  74 * crand, cror, crnor. These all are 5-bit (BA, BB, BT). The bit
  75   to be tested against `inv` is the one selected by `BT`
  76 * mcrf. This has only 3-bit (BF, BFA). In order to select the
  77   bit to be tested, the alternative FFirst encoding must be used.
  78
  79 This limits sv.mcrf in that it may not use the `VLi` (VL inclusive)
  80 Mode. This is unfortunste but unavoidable due to encoding pressure
  81 on SVP64.
  82